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fujitsu semiconductor controller manual f 2 mc-16lx 16-bit microcontroller MB90560 series hardware manual cm44-10107-1e

i preface n objectives and intended reader thank you for purchasing fujitsu semiconductor products. the MB90560 series was developed as a group of general-purpose models in the f2mc-16 lx series, which is a family of original 16-bit single-chip microcontrollers that can be used for application specific ics (asics). this manual is intended for engineers who design products using the MB90560 series of microcontrollers. the manual describes the functions and operation of the MB90560 series. n trademarks f2mc is a registered trademark of fujitsu limited and stands for fujitsu flexible microcontroller.
ii ? 1998 fujitsu limited printed in japan 1. the contents of this document are subject to change without notice. customers are advised to consult with fujitsu sales representatives before ordering. 2. the information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. also, fujitsu is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. 3. the contents of this document may not be reproduced or copied without the permission of fujitsu limited. 4. fujitsu semiconductor devices are intended for use in standard applications (computers, office automation and other office equipment, industrial, communications, and measurement equipment, personal or household devices, etc.). caution: customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with fujitsu sales representatives before such use. the company will not be responsible for damages arising from such use without prior approval. 5. any semiconductor devices have an inherent chance of failure.you must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. 6. if any products described in this document represent goods or technologies subject to certain restrictions on export under the foreign exchange and foreign trade law of japan, the prior authorization by japanese government will be required for export of those products from japan.
MB90560 series iii contents chapter 1 overview ....................................................................................................1 1.1 features .................................................................................................................... .............................2 1.2 product lineup .............................................................................................................. .........................4 1.3 block diagram ............................................................................................................... .........................5 1.4 pin assignments ............................................................................................................. ........................6 1.5 package dimensions .......................................................................................................... ..................10 1.6 pin functions ............................................................................................................... .........................14 1.7 i/o circuit types ........................................................................................................... ........................18 1.8 notes on handling devices ................................................................................................... ...............20 chapter 2 cpu ..............................................................................................................23 2.1 cpu ......................................................................................................................... .............................24 2.2 memory space ................................................................................................................ ......................26 2.3 memory maps ................................................................................................................. ......................28 2.4 addressing .................................................................................................................. ..........................29 2.4.1 linear addressing ........................................................................................................ ...................30 2.4.2 bank addressing ........................................................................................................... ...................32 2.5 memory location of multibyte data ........................................................................................... ...........34 2.6 registers ................................................................................................................... ............................36 2.7 dedicated registers ......................................................................................................... ....................38 2.7.1 accumulator (a) ........................................................................................................... ....................40 2.7.2 stack pointers (usp, ssp) ................................................................................................. ............44 2.7.3 processor status (ps) ..................................................................................................... ................46 2.7.4 condition code register (ps: ccr) ......................................................................................... .........48 2.7.5 register bank pointer (ps: rp) ............................................................................................ ...........50 2.7.6 interrupt level mask register (ps: ilm) ................................................................................... .........51 2.7.7 program counter (pc) ...................................................................................................... ...............52 2.7.8 direct page register (dpr) ................................................................................................ ............53 2.7.9 bank registers (pcb, dtb, usb, ssb, adb) ................................................................................54 2.8 general-purpose registers ................................................................................................... ...............56 2.9 prefix codes ................................................................................................................ .........................58 2.9.1 bank select prefix (pcb, dtb, adb, spb) ................................................................................... ...60 2.9.2 common register bank prefix (cmr) ......................................................................................... ......62 2.9.3 flag change suppression prefix (ncc) ...................................................................................... .....63 2.9.4 restrictions on prefix codes .............................................................................................. .............64 chapter 3 resets .......................................................................................................67 3.1 resets ...................................................................................................................... ............................68 3.2 reset causes and oscillation stabilization wait intervals ................................................................... 70 3.3 external reset pin .......................................................................................................... ......................72 3.4 reset operation ............................................................................................................. .......................74 3.5 reset cause bits ............................................................................................................ ......................76 3.6 status of pins in a reset ................................................................................................... ...................78
iv MB90560 series chapter 4 clocks ...................................................................................................... 81 4.1 clocks ...................................................................................................................... ............................ 82 4.2 block diagram of the clock generator ........................................................................................ ........ 84 4.3 clock selection register (ckscr) ............................................................................................ .......... 86 4.4 clock mode .................................................................................................................. ........................ 88 4.5 oscillation stabilization wait interval ..................................................................................... .............. 90 4.6 connection of an oscillator or an external clock ............................................................................ .... 91 chapter 5 low power consumption mode ...................................................... 93 5.1 low power consumption mode .................................................................................................. ......... 94 5.2 block diagram of the low power consumption control circuit ........................................................... 96 5.3 low power mode control register (lpmcr) ..................................................................................... .98 5.4 cpu intermittent operation mode ............................................................................................. ......... 102 5.5 standby mode ................................................................................................................ .................... 103 5.5.1 sleep mode ................................................................................................................ ................... 104 5.5.2 timebase timer mode ....................................................................................................... ............ 108 5.5.3 stop mode ................................................................................................................. ................... 110 5.6 status change diagram ....................................................................................................... .............. 112 5.7 status of pins in standby mode and reset .................................................................................... ... 115 5.8 notes on using low power consumption mode ............................................................................... 116 chapter 6 interrupts ............................................................................................ 119 6.1 interrupts .................................................................................................................. .......................... 120 6.2 interrupt causes and interrupt vectors ...................................................................................... ........ 122 6.3 interrupt control registers and peripheral functions ........................................................................ 124 6.3.1 interrupt control registers (icr00 to icr15) ............................................................................. ... 126 6.3.2 interrupt control register functions ...................................................................................... .......... 128 6.4 hardware interrupts ......................................................................................................... .................. 132 6.4.1 operation of hardware interrupts .......................................................................................... ........ 136 6.4.2 processing for interrupt operation ........................................................................................ ......... 138 6.4.3 procedure for using hardware interrupts ................................................................................... ... 139 6.4.4 multiple interrupts ....................................................................................................... .................. 140 6.4.5 hardware interrupt processing time ........................................................................................ ...... 142 6.5 software interrupts ......................................................................................................... .................... 144 6.6 interrupt of extended intelligent i/o service (ei2os) ......................................................................... 1 46 6.6.1 extended intelligent i/o service (ei2os) descriptor (isd) ............................................................. 148 6.6.2 registers of the extended intelligent i/o service (ei2os) descriptor (isd) ................................... 150 6.7 operation of the extended intelligent i/o service (ei2os) .................................................................. 1 54 6.7.1 procedure for using the extended intelligent i/o service (ei2os) ................................................. 155 6.7.2 processing time of the extended intelligent i/o service (ei2os) ................................................... 156 6.8 exception processing interrupt .............................................................................................. ............ 158 6.9 stack operations for interrupt processing ................................................................................... ...... 160 6.10 sample programs for interrupt processing ................................................................................... ..... 162 chapter 7 setting a mode .................................................................................... 167 7.1 setting a mode .............................................................................................................. ..................... 168 7.2 mode pins (md2 to md0) ...................................................................................................... ............ 169
MB90560 series v 7.3 mode data ................................................................................................................... .......................170 chapter 8 i/o ports ..................................................................................................173 8.1 overview of i/o ports ....................................................................................................... ...................174 8.2 port register ............................................................................................................... ........................175 8.3 port 0 ..................................................................................................................... ............................176 8.3.1 port 0 registers (pdr0, ddr0, and rdr0) .................................................................................17 8 8.3.2 operation of port 0 ....................................................................................................... .................180 8.4 port 1 ...................................................................................................................... ............................182 8.4.1 port 1 registers (pdr1, ddr1, and rdr1) .................................................................................18 4 8.4.2 operation of port 1 ....................................................................................................... .................186 8.5 port 2 ...................................................................................................................... ............................188 8.5.1 port 2 registers (pdr2 and ddr2) .......................................................................................... ....190 8.5.2 operation of port 2 ....................................................................................................... .................192 8.6 port 3 ...................................................................................................................... ............................194 8.6.1 port 3 registers (pdr3 and ddr3) .......................................................................................... ....196 8.6.2 operation of port 3 ....................................................................................................... .................198 8.7 port 4 ...................................................................................................................... ............................200 8.7.1 port 4 registers (pdr4 and ddr4) .......................................................................................... ....202 8.7.2 operation of port 4 ....................................................................................................... .................204 8.8 port 5 ...................................................................................................................... ............................206 8.8.1 port 5 registers (pdr5, ddr5, and ader) .................................................................................20 8 8.8.2 operation of port 5 ....................................................................................................... .................210 8.9 port 6 ...................................................................................................................... ............................212 8.9.1 port 6 registers (pdr6 and ddr6) .......................................................................................... ....214 8.9.2 operation of port 6 ....................................................................................................... .................216 8.10 sample i/o port program .................................................................................................... ...............218 chapter 9 timebase timer ....................................................................................221 9.1 overview of the timebase timer .............................................................................................. ..........222 9.2 configuration of the timebase timer ......................................................................................... ........224 9.3 timebase timer control register (tbtc) ...................................................................................... ....226 9.4 timebase timer interrupts ................................................................................................... ...............228 9.5 operation of the timebase timer ............................................................................................. ..........230 9.6 usage notes on the timebase timer ........................................................................................... ......232 9.7 sample program for the timebase timer program ............................................................................234 chapter 10 watchdog timer ..................................................................................237 10.1 overview of the watchdog timer ............................................................................................. ..........238 10.2 configuration of the watchdog timer ........................................................................................ .........239 10.3 watchdog timer control register (wdtc) ..................................................................................... ...240 10.4 operation of the watchdog timer ............................................................................................ ...........242 10.5 usage notes on the watchdog timer .......................................................................................... .......244 10.6 sample program for the watchdog timer ...................................................................................... ....245 chapter 11 16-bit reload timer ............................................................................247 11.1 overview of the 16-bit reload timer ........................................................................................ ..........248
vi MB90560 series 11.2 configuration of the 16-bit reload timer ................................................................................... ........ 252 11.3 16-bit reload timer pins ................................................................................................... ................ 254 11.4 16-bit reload timer registers .............................................................................................. ............. 255 11.4.1 timer control status register, upper part (tmcsr0, tmcsr1: h) ............................................... 256 11.4.2 timer control status register, lower part (tmcsr0, tmcsr1: l) ............................................... 258 11.4.3 16-bit timer register (tmr0, tmr1) ....................................................................................... ....... 260 11.4.4 16-bit reload register (tmrlr0, tmrlr1) .................................................................................. .261 11.5 16-bit reload timer interrupts ............................................................................................. .............. 262 11.6 operation of the 16-bit reload timer ....................................................................................... ......... 264 11.6.1 reload mode (internal clock mode) ........................................................................................ ..... 266 11.6.2 single-shot mode (internal clock mode) ................................................................................... ... 268 11.6.3 event count mode ......................................................................................................... ................ 270 11.7 usage notes on the 16-bit reload timer ..................................................................................... ..... 272 11.8 sample programs for the 16-bit reload timer ................................................................................ .. 273 chapter 12 multi-function timer ........................................................................ 277 12.1 overview of multi-function timer ........................................................................................... ............ 278 12.2 block diagram of multi-function timer ...................................................................................... ......... 280 12.3 register of multi-function timer ........................................................................................... ............. 284 12.3.1 registers of 16-bit free-run timer ...................................................................................... ........ 290 12.3.1.1 compare clear register (cpclr) ........................................................................................ .291 12.3.1.2 timer data register (tcdt) ............................................................................................ ....... 292 12.3.1.3 timer control status register (tccs) .................................................................................. .294 12.3.2 registers of 16-bit output compare ...................................................................................... ....... 298 12.3.2.1 compare registers (occp0~5) ........................................................................................... .. 299 12.3.2.2 compare control registers (osc0/1/2/3/4/5) ........................................................................ 300 12.3.3 registers of 16-bit input capture ........................................................................................ .......... 304 12.3.3.1 input capture register (ipcp0~3) ...................................................................................... .... 305 12.3.3.2 capture control registers (ics23, ics01) ............................................................................. 3 06 12.3.4 register of 8/16-bit ppg timer ........................................................................................... .......... 310 12.3.4.1 ppg reload register (prlh0~5, prll0~5) ......................................................................... 311 12.3.4.2 ppg control register (ppgc0~5) ........................................................................................ .312 12.3.4.3 ppg clock control register (pcs01/23/45) .......................................................................... 316 12.3.5 registers of waveform generator .......................................................................................... ...... 318 12.3.5.1 8-bit reload register (tmrr0/1/2) ..................................................................................... ... 319 12.3.5.2 8-bit timer control register (dtcr0/1/2) .............................................................................. 320 12.3.5.3 waveform control register (sigcr) ..................................................................................... .322 12.4 operation of multi-function timer .......................................................................................... ........... 324 12.4.1 operation of 16-bit free-run timer ....................................................................................... ........ 326 12.4.2 operation of 16-bit output compare ...................................................................................... ...... 328 12.4.3 operation of 16-bit input capture ....................................................................................... .......... 332 12.4.4 operation of 8/16-bit ppg timers ........................................................................................ ........ 334 12.4.5 operation of waveform generator ......................................................................................... ...... 340 12.4.5.1 operation of dead-timer control circuit ............................................................................... .. 342 12.4.5.2 operation of ppg output and gate signal control circuit ................................................... 346 12.4.5.3 operation of dtti pin control ......................................................................................... ....... 348 chapter 13 uart ......................................................................................................... 351 13.1 overview of uart ........................................................................................................... .................. 352 13.2 configuration of uart ...................................................................................................... ................. 354
MB90560 series vii 13.3 uart pins .................................................................................................................. ........................358 13.4 uart registers ............................................................................................................. .....................360 13.4.1 serial control register 1 (scr0/1) ....................................................................................... ........362 13.4.2 serial mode control register (smr0/1) ................................................................................... ....364 13.4.3 serial status register (ssr0/1) ........................................................................................ ..........366 13.4.4 serial input data register (sidr0/1) and serial output data register (sor0/1) ........................368 13.4.5 communication prescaler control register (cdcr0/1) ................................................................370 13.5 uart interrupts ............................................................................................................ ......................372 13.5.1 reception interrupt generation and flag set timing ....................................................................374 13.5.2 transmission interrupt generation and flag set timing ...............................................................375 13.6 uart baud rates ............................................................................................................ ..................376 13.6.1 baud rates determined using the dedicated baud rate generator ............................................378 13.6.2 baud rates determined using the internal timer (16-bit reload timer 0) ...................................382 13.6.3 baud rates determined using the external clock ........................................................................384 13.7 operation of uart .......................................................................................................... ...................386 13.7.1 operation in asynchronous mode (operation modes 0 and 1) .....................................................388 13.7.2 operation in synchronous mode (operation mode 2) ...................................................................390 13.7.3 bidirectional communication function (normal mode) .................................................................392 13.7.4 master-slave communication function (multiprocessor mode) ....................................................394 13.8 notes on using uart ........................................................................................................ ................396 13.9 sample program for uart .................................................................................................... .............398 chapter 14 dtp/external interrupt circuit ...................................................401 14.1 overview of the dtp/external interrupt circuit ............................................................................. ......402 14.2 configuration of the dtp/external interrupt circuit ........................................................................ ....404 14.3 dtp/external interrupt circuit pins ........................................................................................ .............406 14.4 dtp/external interrupt circuit registers ................................................................................... ..........408 14.4.1 dtp/interrupt cause register (eirr) ...................................................................................... ........409 14.4.2 dtp/interrupt enable register (enir) ................................................................................... .......410 14.4.3 request level setting register (elvr) .................................................................................. .......412 14.5 operation of the dtp/external interrupt circuit ............................................................................ ......414 14.5.1 external interrupt function ............................................................................................ ................417 14.5.2 dtp function ........................................................................................................... .....................418 14.6 usage notes on the dtp/external interrupt circuit .......................................................................... ..420 14.7 sample programs for the dtp/external interrupt circuit ....................................................................4 22 chapter 15 delayed interrupt generator module ......................................................427 15.1 overview of the delayed interrupt generator module ........................................................................4 28 15.2 operation of the delayed interrupt generator module .......................................................................4 29 chapter 16 8/10-bit a/d converter .......................................................................431 16.1 overview of the 8/10-bit a/d converter ..................................................................................... .........432 16.2 configuration of the 8/10-bit a/d converter ................................................................................ .......434 16.3 8/10-bit a/d converter pins ................................................................................................ ................436 16.4 8/10-bit a/d converter registers ........................................................................................... ............438 16.4.1 a/d control status register 1 (adcs1) .................................................................................. .......439 16.4.2 a/d control status register 0 (adcs0) .................................................................................. .......442
viii MB90560 series 16.4.3 a/d data register (adcr0, 1) ............................................................................................ .......... 444 16.5 8/10-bit a/d converter interrupts .......................................................................................... ............. 446 16.6 operation of the 8/10-bit a/d converter .................................................................................... ........ 447 16.6.1 conversion using ei2os ....................................................................................................... ...... 450 16.6.2 a/d conversion data protection function ................................................................................ ..... 452 16.7 usage notes on the 8/10-bit a/d converter .................................................................................. .... 454 16.8 sample program 1 for single conversion mode using ei2os ........................................................... 456 16.9 sample program 2 for continuous conversion mode using ei2os .................................................. 458 16.10 sample program 3 for stop conversion mode using ei2os ............................................................. 461 chapter 17 address match detection function .......................................... 465 17.1 overview of the address match detection function .......................................................................... 4 66 17.2 example of using the address match detection function ................................................................. 469 chapter 18 rom mirroring function selection module ........................... 473 18.1 overview of the rom mirroring function selection module .............................................................. 474 appendix ................................................................................................................... 477 appendix a i/o map ..................................................................................................... 479 appendix b instructions ........................................................................................ 485 b.1 instructions ................................................................................................................ ......................... 486 b.2 addressing ................................................................................................................. ........................ 488 b.3 direct addressing .......................................................................................................... ..................... 490 b.4 indirect addressing ........................................................................................................ .................... 496 b.5 number of execution cycles ................................................................................................. ............. 503 b.6 effective-address field .................................................................................................... .................... 506 b.7 reading the instruction list ............................................................................................... ................ 507 b.8 list of f2mc-16lx instructions ............................................................................................. ............. 510 b.9 instruction maps ........................................................................................................... ...................... 523 appendix c 512k-bit flash memory ..................................................................... 545 appendix d example of f2mc-16lx mb90f562 connection for serial writing ............................................................................. 551
MB90560 series ix figures figure 1.3-2 block diagram ...................................................................................................... ....................5 figure 1.4-1 pin assignment of fpt-64p-m09 ..................................................................................... .......6 figure 1.4-2 pin assignment of fpt-64p-m09 ...................................................................................... ......7 figure 1.4-3 pin assignment of dip-64p-m01 ..................................................................................... ........8 figure 1.5-1 dimensions of fpt-64p-m06 package ................................................................................. 10 figure 1.5-2 dimensions of fpt-64p-m09 package .................................................................................1 1 figure 1.5-3 dimensions of dip-64p-m01 package ................................................................................. .12 figure 1.8-1 sample connection of external clock ................................................................................ .....21 figure 2.2-1 sample relationship between the f2mc-16lx system and the memory map ......................26 figure 2.3-1 memory maps ........................................................................................................ ................28 figure 2.4-1 linear addressing and bank addressing memory management ...........................................29 figure 2.4-2 example of direct specified 24-bit physical address in linear addressing .............................30 figure 2.4-3 example of indirect specified address with a 32-bit general-purpose register in linear addressing ........................................................................................................... ....30 figure 2.4-4 sample bank addressing ............................................................................................. ..........33 figure 2.5-1 storage of multibyte data in ram .................................................................................. ........34 figure 2.5-2 storage of a multibyte operand ..................................................................................... ........34 figure 2.5-3 storage of multibyte data in a stack ............................................................................... .......35 figure 2.5-4 multibyte data access on a bank boundary ........................................................................... 35 figure 2.6-1 dedicated registers and general-purpose registers .............................................................36 figure 2.7-1 configuration of dedicated registers .............................................................................. ........39 figure 2.7-2 data transfer to the accumulator ................................................................................... ........40 figure 2.7-3 example of al-ah transfer in the accumulator (a) (8-bit immediate value, zero extension) 41 figure 2.7-4 example of al-ah transfer in the accumulator (a) (8-bit immediate value, sign extension) .41 figure 2.7-5 example of 32-bit data transfer to the accumulator (a) (register indirect) .............................41 figure 2.7-6 example of al-ah transfer in the accumulator (a) (16 bits, register indirect) .......................42 figure 2.7-7 stack operation instruction and stack pointer ...................................................................... ..45 figure 2.7-8 processor status (ps) configuration ................................................................................ ......46 figure 2.7-9 condition code register (ccr) configuration ........................................................................ .48 figure 2.7-10 configuration of the register bank pointer (rp) ................................................................... ..50 figure 2.7-11 conversion rules for physical address of general-purpose register area ..............................50 figure 2.7-12 configuration of the interrupt level mask register (ilm) ........................................................51 figure 2.7-13 program counter (pc) .............................................................................................. .............52 figure 2.7-14 physical address generation by the direct page register (dpr) ............................................53 figure 2.7-15 example of direct page register (dpr) setting and data access ...........................................53
x MB90560 series figure 2.8-1 location and configuration of the general-purpose register banks in the memory space .... 56 figure 2.9-1 interrupt/hold suppression ......................................................................................... ........... 64 figure 2.9-2 interrupt/hold suppression instructions and prefix codes ..................................................... 65 figure 2.9-3 consecutive prefix codes ........................................................................................... .......... 65 figure 3.3-1 block diagram of internal reset .................................................................................... ......... 72 figure 3.3-2 block diagram of internal reset for external pin ................................................................... .73 figure 3.4-1 reset operation flow ............................................................................................... .............. 74 figure 3.4-2 transfer of reset vector and mode data ............................................................................. .. 75 figure 3.5-1 block diagram of reset cause bits .................................................................................. ....... 76 figure 3.5-2 configuration of reset cause bits (watchdog timer control register) ..................................... 77 figure 4.1-1 clock supply map ................................................................................................... .............. 83 figure 4.2-1 block diagram of the clock generator ............................................................................... .... 84 figure 4.3-1 configuration of the clock selection register (ckscr) ......................................................... 86 figure 4.4-1 status change diagram for machine clock selection ............................................................ 89 figure 4.5-1 operation when oscillation starts .................................................................................. ........ 90 figure 4.6-1 example of connecting a crystal or ceramic oscillator to the microcontroller ....................... 91 figure 4.6-2 example of connecting an external clock to the microcontroller ........................................... 91 figure 5.1-1 cpu operating modes and current consumption .................................................................. 94 figure 5.2-1 block diagram of the low power consumption control circuit ................................................ 96 figure 5.3-1 configuration of the low power consumption mode control register (lpmcr) ..................... 98 figure 5.4-1 clock pulses during cpu intermittent operation ................................................................. 102 figure 5.5-1 release of sleep mode for an interrupt ............................................................................. .105 figure 5.5-2 release of pll sleep mode (by external reset) ................................................................. 106 figure 5.5-3 release of timebase timer mode (by an external reset) ..................................................... 109 figure 5.5-4 release of stop mode (by external reset) ........................................................................... 111 figure 5.6-1 status change diagram .............................................................................................. ......... 112 figure 6.1-1 overall flow of interrupt operation ................................................................................ ....... 121 figure 6.3-1 interrupt control registers (icr00 to icr15) during writing ................................................ 126 figure 6.3-2 interrupt control registers (icr00 to icr15) during reading ............................................... 127 figure 6.3-3 configuration of interrupt control registers (icr) ................................................................ 1 28 figure 6.4-1 hardware interrupt request while writing to the peripheral function control register area .......................................................................................................... .. 134 figure 6.4-2 hardware interrupt operation ....................................................................................... ....... 137 figure 6.4-3 flow of interrupt processing ....................................................................................... ........ 138 figure 6.4-4 procedure for using hardware interrupts ............................................................................ 139 figure 6.4-5 example of multiple interrupts ..................................................................................... ....... 141 figure 6.4-6 interrupt processing time .......................................................................................... .......... 142 figure 6.5-1 software interrupt operation ....................................................................................... ........ 145
MB90560 series xi figure 6.6-1 extended intelligent i/o service (ei2os) operation .............................................................147 figure 6.6-2 configuration of ei2os descriptor (isd) ............................................................................ .148 figure 6.6-3 configuration of dct ............................................................................................... ............150 figure 6.6-4 configuration of i/o register address pointer (ioa) .............................................................150 figure 6.6-5 configuration of ei2os status register (iscs) ....................................................................15 1 figure 6.6-6 configuration of buffer address pointer (bap) ....................................................................15 2 figure 6.7-1 flow of extended intelligent i/o service (ei2os) operation .................................................154 figure 6.7-1 procedure for using the extended intelligent i/o service (ei2os) .......................................155 figure 6.9-1 stack operations at the start of interrupt processing ...........................................................160 figure 6.9-2 stack area ......................................................................................................... ..................161 figure 7.1-1 mode classification ................................................................................................ ..............168 figure 7.3-1 mode data configuration ............................................................................................ ..........170 figure 7.3-2 correspondence between access areas and physical addresses in single-chip mode ......171 figure 8.3-1 block diagram of port 0 pins ....................................................................................... .........177 figure 8.4-1 block diagram of port 1 pins ....................................................................................... .........183 figure 8.5-1 block diagram of port 2 pins ....................................................................................... .........189 figure 8.6-1 block diagram of port 3 pins ....................................................................................... .........195 figure 8.7-1 block diagram of port 4 pins ....................................................................................... .........201 figure 8.8-1 block diagram of port 5 pins ....................................................................................... .........207 figure 8.9-1 block diagram of port 6 pins ....................................................................................... .........213 figure 8.10-1 example of eight-segment led connection ........................................................................218 figure 9.2-1 block diagram of the timebase timer ................................................................................ ...224 figure 9.3-1 timebase timer control register (tbtc) ............................................................................. .226 figure 9.5-1 setting of the timebase timer ...................................................................................... .........230 figure 9.6-1 effect on ppg when clearing timebase timer ......................................................................232 figure 9.6-2 timebase timer operations .......................................................................................... ........233 figure 10.2-1 block diagram of the watchdog timer ............................................................................... ...239 figure 10.3-1 watchdog timer control register (wdtc) ............................................................................ 240 figure 10.4-1 setting of the watchdog timer ..................................................................................... .........242 figure 10.4-2 clear timing and watchdog timer intervals ......................................................................... .243 figure 11.2-1 block diagram of the 16-bit reload timer .......................................................................... ....252 figure 11.3-1 block diagram of the 16-bit reload timer pins ..................................................................... .254 figure 11.4-1 16-bit reload timer registers ..................................................................................... ............255 figure 11.4-2 timer control status register, upper part (tmcsr0, tmcsr1: h) .....................................256 figure 11.4-3 timer control status register, low part (tmcsr0, tmcsr1: l) .........................................258 figure 11.4-4 16-bit timer register (tmr0, tmr1) ................................................................................ ....260 figure 11.4-5 16-bit reload register (tmrlr0, tmrlr1) .........................................................................26 1 figure 11.6-1 internal clock mode setting ....................................................................................... ...........264
xii MB90560 series figure 11.6-2 event counter mode setting ........................................................................................ ........ 264 figure 11.6-3 counter status transition ......................................................................................... ............ 265 figure 11.6-4 count operation in reload mode (software trigger operation) ............................................. 266 figure 11.6-5 counting in reload mode (external trigger operation) ......................................................... 267 figure 11.6-6 count operation in reload mode (software trigger and gate input operation) ..................... 267 figure 11.6-7 count operation in single-shot mode (software trigger operation) ...................................... 268 figure 11.6-8 count operation in single-shot mode (external trigger operation) ...................................... 269 figure 11.6-9 count operation in single-shot mode (software trigger and gate input operation) .............. 269 figure 11.6-10 count operation in reload mode (event count mode) ......................................................... 270 figure 11.6-11 counter operation in single-shot mode (event count mode) ............................................... 271 figure 12.2-1 block diagram of realtime i/o ..................................................................................... ..... 280 figure 12.2-2 block diagram of 8/16-bit ppg timer ............................................................................... .281 figure 12.2-3 block diagram of waveform generator .............................................................................. 2 82 figure 12.3-1 registers of 16-bit free-run timer ................................................................................ .... 284 figure 12.3-2 registers of output compare ....................................................................................... ...... 285 figure 12.3-3 registers of 16-bit input capture ................................................................................. ....... 286 figure 12.3-4 registers of 8/16-bit ppg timers .................................................................................. ..... 287 figure 12.3-5 registers of waveform generator ................................................................................... ... 288 figure 12.3.1-1 registers of 16-bit free-run timer .............................................................................. ...... 290 figure 12.3.1.1-1compare clear register (cpcr) ................................................................................ ....... 291 figure 12.3.1.2-1timer data register .......................................................................................... ................. 292 figure 12.3.1.3-1timer control status register (upper) ........................................................................ ....... 294 figure 12.3.1.3-2timer control status register (lower) ........................................................................ ....... 296 figure 12.3.2-1 registers of output compare ..................................................................................... ........ 298 figure 12.3.2.1-1compare registers (occp0~5) .................................................................................. ....... 299 figure 12.3.2.2-1compare control register (upper, osc1/3/5) ................................................................... 300 figure 12.3.2.2-2compare control register (lower, osc0/2/4) ................................................................... 302 figure 12.3.3-1 registers of 16-bit input capture ............................................................................... ......... 304 figure 12.3.3.1-1input capture registers (ipcp0~3) ............................................................................ ........ 305 figure 12.3.3.2-1capture control register (ics23) ............................................................................. ......... 306 figure 12.3.3.2-2capture control register (ics01) ............................................................................. ......... 308 figure 12.3.4-1 registers of 8/16-bit ppg timers ................................................................................ ....... 310 figure 12.3.4.1-1ppg reload register (prlh0~5, prll0~5) ..................................................................... 31 1 figure 12.3.4.2-1ppg1/3/5 control register (ppgc1/3/5) ........................................................................ ... 312 figure 12.3.4.2-2ppg0/2/4 control register (ppgc0/2/4) ........................................................................ ... 314 figure 12.3.4.3-1ppg0/1/2/3/4/5 clock control register (pcd01/23/45) ..................................................... 316 figure 12.3.5-1 registers of waveform generator ................................................................................. ..... 318 figure 12.3.5.1-18-bit reload registers (tmrr0/1/2) ........................................................................... ....... 319
MB90560 series xiii figure 12.3.5.2-18-bit timer control register (dtcr0/1/2) ..................................................................... ......320 figure 12.3.5.3-1waveform control register (sigcr) ............................................................................ ......322 figure 12.4.1-1 clearing the counter by an overflow ............................................................................. .......326 figure 12.4.1-2 clearing the counter upon a match with compare clear register .........................................326 figure 12.4.1-3 16-bit free-run timer count timing .............................................................................. .........327 figure 12.4.1-4 16-bit free-run timer clear timing .............................................................................. ..........327 figure 12.4.2-1 sample output waveform when compare registers 0 and 1 are used individually when the initial output value is 0. ........................................................................................................... ....328 figure 12.4.2-2 sample output waveform when compare registers 0 and 1 are used in a pair when the initial output value is 0. ........................................................................................................... ....329 figure 12.4.2-3 compare operation upon update of compare registers .......................................................330 figure 12.4.2-4 compare interrupt timing ........................................................................................ .............330 figure 12.4.2-5 output pin change timing ........................................................................................ ............330 figure 12.4.3-1 sample input capture timing ..................................................................................... ...........332 figure 12.4.3-2 16-bit input capture timing for input signals ................................................................... ......333 figure 12.4.4-1 ppg output operation, output waveform ........................................................................... ..335 figure 12.4.4-2 8+8 ppg output operation waveform ............................................................................... ...337 figure 12.4.4-3 write timing chart .............................................................................................. ..................338 figure 12.4.4-4 prl write operation block diagram ............................................................................... ......338 figure 12.4.5-1 waveform generator .............................................................................................. .............340 figure 12.4.5.1-1positive polarity non-overlap signal generation by rt1/3/5 ..............................................342 figure 12.4.5.1-2negative polarity non-overlap signal generation by rt1/3/5 ............................................343 figure 12.4.5.1-3positive polarity non-overlap signal generation by ppg timer ..........................................344 figure 12.4.5.1-4negative polarity non-overlap signal generation by ppg timer ........................................345 figure 12.4.5.2-1generating ppg output/gate signal during each rt is at h level ..................................346 figure 12.4.5.2-2generating ppg output/gate signal until the value 8-bit timer and 8-bit reload register is matched. ................................................................................................................... .......347 figure 12.4.5.3-1operation when dtti input is enabled ......................................................................... .......348 figure 13.1-1 uart operation mode ............................................................................................... ..........353 figure 13.2-1 block diagram of uart ............................................................................................. ..........354 figure 13.3-1 block diagram of uart pins ........................................................................................ ......359 figure 13.4-1 uart registers .................................................................................................... ................360 figure 13.4-2 serial control register (scr0/1) .................................................................................. ........362 figure 13.4-3 serial mode control register (smr0/1) ............................................................................. ...364 figure 13.4-4 status register (ssr0/1) .......................................................................................... ...........366 figure 13.4-5 serial input data register (sidr0/1) .............................................................................. ......368 figure 13.4-6 output data register (sodr0/1) .................................................................................... ......368 figure 13.5-1 reception operation and flag set timing ........................................................................... ...374 figure 13.5-2 transmission operation and flag set timing ........................................................................ .375
xiv MB90560 series figure 13.6-1 baud rate selection circuit ....................................................................................... ............ 377 figure 13.6-2 baud rate selection circuit for the internal timer (16-bit reload timer 0) .............................. 382 figure 13.6-3 baud rate selection circuit for the external clock ................................................................ 384 figure 13.7-1 transfer data format (operation modes 0 and 1) ................................................................ 388 figure 13.7-2 transmission data when parity is enabled ......................................................................... 3 89 figure 13.7-3 transfer data format (operation mode 2) ........................................................................... .390 figure 13.7-4 settings for uart1 operation mode 0 ............................................................................... .392 figure 13.7-5 connection example of uart1 bidirectional communication ............................................. 392 figure 13.7-6 example of bidirectional communication flowchart ............................................................. 393 figure 13.7-7 settings for uart operation mode 1 ................................................................................ .. 394 figure 13.7-8 connection example of uart master-slave communication ............................................. 394 figure 13.7-9 master-slave communication flowchart .............................................................................. 395 figure 14.2-1 block diagram of the dtp/external interrupt circuit ............................................................ 404 figure 14.3-1 block diagram of the dtp/external interrupt circuit pins (for p10/int0 ~ p16/int6 only) . 407 figure 14.3.2 block diagram of the dtp/external interrupt circuit pins (for p63/ int7 only) ................... 407 figure 14.4-2 dtp/external interrupt circuit registers .......................................................................... ..... 408 figure 14.4-2 dtp/interrupt cause register (eirr) ............................................................................... .... 409 figure 14.4-3 dtp/interrupt enable register (enir) .............................................................................. ... 410 figure 14.4-4 request level setting register (elvr) ............................................................................. ... 412 figure 14.5-1 dtp/external interrupt circuit .................................................................................... .......... 414 figure 14.5-2 operation of the dtp/external interrupt circuit ................................................................... 416 figure 14.5-3 example of interfacing to the external peripheral ............................................................... 41 8 figure 14.6-1 clearing the cause retention circuit when a level is specified ............................................ 420 figure 14.6-2 dtp/external interrupt cause and interrupt request when the output of interrupt requests is enabled .......................................................................................... 420 figure 15.1-1 block diagram of the delayed interrupt generator module .................................................. 428 figure 15.2-1 operation of the delayed interrupt generator module ......................................................... 429 figure 16.2-1 block diagram of the 8/10-bit a/d converter ....................................................................... 434 figure 16.3-1 block diagram of the p50/an0 to p57/an7 pins ................................................................ 437 figure 16.4-1 8/10-bit a/d converter registers .................................................................................. ........ 438 figure 16.4-2 a/d control status register 1 (adcs1) ............................................................................. ... 439 figure 16.4-3 a/d control status register 0 (adcs0) ............................................................................. ... 442 figure 16.4-4 a/d data register (adcr0, 1) ...................................................................................... ....... 444 figure 16.6-1 settings for single conversion mode ............................................................................... .... 447 figure 16.6-2 settings for continuous conversion mode ........................................................................... 448 figure 16.6-3 settings for stop conversion mode ................................................................................. .... 449 figure 16.6-4 sample operation flowchart when ei2os is used ............................................................... 450 figure 16.6-5 operation flowchart of the data protection function when ei2os is used ........................... 453
MB90560 series xv figure 16.8-1 flowchart of program using ei2os (single conversion mode) .............................................456 figure 16.9-1 flowchart of program using ei2os (continuous conversion mode) .....................................458 figure 16.10-1 flowchart of program using ei2os (stop conversion mode) ...............................................461 figure 17.1-1 block diagram ..................................................................................................... .................466 figure 17.2-1 system configuration example ...................................................................................... ......469 figure 17.2-2 system configuration example ...................................................................................... ......470 figure 17.2-3 flowchart of program patch processing ............................................................................. .471 figure 18.1-1 block diagram ..................................................................................................... .................474 figure 18.1-2 memory space ...................................................................................................... ...............475 figure b.3-1 example of immediate addressing (#imm) ..........................................................................490 figure b.3-2 example of register direct addressing .............................................................................. ...491 figure b.3-3 example of direct branch addressing (addr16) ...................................................................491 figure b.3-4 example of physical direct branch addressing (addr24) .....................................................492 figure b.3-5 example of i/o direct addressing (io) .............................................................................. ....492 figure b.3-6 example of condensed direct addressing (dir) ....................................................................492 figure b.3-7 example of direct addressing (addr16) .............................................................................. .493 figure b.3-8 example of i/o direct bit addressing (io:bp) ....................................................................... .493 figure b.3-9 example of condensed direct bit addressing (dir:bp) ..........................................................494 figure b.3-10 example of direct bit addressing (addr16:bp) ...................................................................... 494 figure b.3-11 example of vector addressing (#vct) ............................................................................... ....494 figure b.4-1 example of register indirect addressing (@rwj j = 0 to 3) ................................................496 figure b.4-3 example of register indirect addressing with displacement (@rwi+disp8 i = 0 to 7, @rwj+disp16 j = 0 to 3) ....................................................................................................497 figure b.4-4 example of long-word register indirect addressing with displacement (@rli+disp8 i = 0 to 3) ......................................................................................................4 97 figure b.4-5 example of program counter indirect addressing with displacement (@pc+disp16) .........498 figure b.4-6 example of register indirect addressing with base index (@rw0+rw7, @rw1+rw7) ....499 figure b.4-7 example of program counter relative branch addressing (rel) ............................................499 figure b.4-8 register list configuration ........................................................................................ ............500 figure b.4-9 example of register list (rlst) .................................................................................... ............500 figure b.4-10 example of accumulator indirect addressing (@a) .............................................................500 figure b.4-11 example of accumulator indirect branch addressing (@a) .................................................501 figure b.4-12 example of indirect designation branch addressing (@ear) ................................................501 figure b.4-13 example of indirect designation branch addressing (@eam) ..............................................502 figure b.9-1 configuration of instruction maps .................................................................................. ......523 figure b.9-2 relationship between actual instruction codes and instruction maps .................................524 figure c-1 sector configuration of 512k-bit flash memory ...................................................................545 figure d-1 standard configuration for fujitsu standard serial on-board writing ....................................551
xvi MB90560 series figure d.2 connection example for mb90f562 serial writing .............................................................. 553
MB90560 series xvii tables table 1.2-1 product lineup of the MB90560 series ................................................................................ ....4 table 1.6-1 pin functions ....................................................................................................... ...................14 table 1.6-2 pin functions (continued) ........................................................................................... ...........15 table 1.6-3 pin functions (continued) ........................................................................................... ...........16 table 1.7-1 i/o circuit types ................................................................................................... ...................18 table 1.7-2 i/o circuit types (continued) ....................................................................................... ...........19 table 2.4-1 access space and main function of each bank register ........................................................32 table 2.4-2 addressing and default spaces ....................................................................................... ......33 table 2.7-1 initial values of the dedicated registers ........................................................................... ......39 table 2.7-2 stack address specification ......................................................................................... ..........44 table 2.7-3 interrupt level mask register (ilm) and interrupt level priority ...............................................51 table 2.8-1 typical functions of general-purpose registers ...................................................................... 57 table 2.9-1 bank select prefix codes and selected memory spaces ........................................................60 table 2.9-2 instructions not affected by bank select prefix codes ............................................................60 table 2.9-3 instructions which use requires caution when bank select prefix codes are used ................61 table 2.9-4 instructions whose use requires caution when the common register bank prefix (cmr) is used ........................................................................................................................ ...........62 table 2.9-5 instructions requiring caution when the flag change suppression prefix (ncc) is used .......63 table 2.9-6 prefix codes and interrupt/hold suppression instructions .....................................................64 table 3.1-1 reset causes ........................................................................................................ .................68 table 3.2-1 reset causes and oscillation stabilization wait intervals .......................................................70 table 3.2-2 oscillation stabilization wait intervals set by the clock selection register (ckscr) .............70 table 3.5-1 correspondence between reset cause bits and reset causes ...............................................77 table 4.3-1 function description of each bit of the clock selection register (ckscr) .............................87 table 5.3-1 function description of each bit of the low power consumption mode control register (lpmcr) ........................................................................................................................ .......99 table 5.3-2 instructions to be used for switching to low power consumption mode ...............................100 table 5.5-1 operation statuses during standby mode ............................................................................10 3 table 5.6-1 low power consumption mode operating states .................................................................113 table 5.6-2 clock mode switching and release .................................................................................... ..113 table 5.6-3 switching to and release of standby mode ..........................................................................11 4 table 5.7-1 state of pins in single-chip mode ................................................................................... .....115 table 6.2-1 interrupt vectors ................................................................................................... ...............122 table 6.2-2 interrupt causes, interrupt vectors, and interrupt control registers ......................................123 table 6.3-1 interrupt control registers ......................................................................................... ...........124 table 6.3-2 correspondence between the interrupt level setting bits and interrupt levels .....................129
xviii MB90560 series table 6.3-3 correspondence between the ei2os channel selection bits and descriptor addresses .......................................................................................................... 1 29 table 6.3-4 relationship between ei2os status bits and the ei2os status ......................................... 130 table 6.4-1 mechanisms used for hardware interrupts ........................................................................ 133 table 6.4-2 hardware interrupt suppression instruction ........................................................................ 13 4 table 6.4-3 compensation values (z) for the interrupt handling time .................................................... 143 table 6.6-1 correspondence between channel numbers and descriptor addresses ............................ 148 table 6.7-1 extended intelligent i/o service execution time ................................................................. 156 table 6.7-2 data transfer compensation value for ei2os execution time ............................................. 156 table 6.7-3 interpolation value (z) for the interrupt handling time ......................................................... 157 table 7.2-1 mode pin settings ................................................................................................... ............ 169 table 7.3-1 bus mode setting bits and functions ................................................................................. .. 170 table 7.3-2 relationship between mode pins and mode data ............................................................... 171 table 8.1-1 functions of individual ports ....................................................................................... ........ 174 table 8.2-1 registers and corresponding ports ................................................................................... .. 175 table 8.3-1 port 0 pins ......................................................................................................... ................. 176 table 8.3-2 port 0 pins and their corresponding register bits ................................................................ 177 table 8.3-3 port 0 register functions ........................................................................................... ........... 178 table 8.3-4 states of port 0 pins ............................................................................................... ............. 181 table 8.4-1 port 1 pins ......................................................................................................... ................. 182 table 8.4-2 port 1 pins and their corresponding register bits ................................................................ 183 table 8.4-3 port 1 register functions ........................................................................................... ........... 184 table 8.4-4 states of port 1 pins ............................................................................................... ............. 187 table 8.5-1 port 2 pins ......................................................................................................... ................. 188 table 8.5-2 port 2 pins and their corresponding register bits ................................................................ 189 table 8.5-3 port 2 register functions ........................................................................................... ........... 190 table 8.5-4 states of port 2 pins ............................................................................................... ............. 193 table 8.6-1 port 3 pins ......................................................................................................... ................. 194 table 8.6-2 port 3 pins and their corresponding register bits ................................................................ 195 table 8.6-3 port 3 register functions ........................................................................................... ........... 196 table 8.6-4 states of port 3 pins ............................................................................................... ............. 199 table 8.7-1 port 4 pins ......................................................................................................... ................. 200 table 8.7-2 port 4 pins and their corresponding register bits ................................................................ 201 table 8.7-3 port 4 register functions ........................................................................................... ........... 202 table 8.7-4 states of port 4 pins ............................................................................................... ............. 205 table 8.8-1 port 5 pins ......................................................................................................... ................. 206 table 8.8-2 port 5 pins and their corresponding register bits ................................................................ 207 table 8.8-3 port 5 register functions ........................................................................................... ........... 208
MB90560 series xix table 8.8-4 states of port 5 pins ............................................................................................... .............211 table 8.9-1 port 6 pins ......................................................................................................... ..................212 table 8.9-2 port 6 pins and their corresponding register bits .................................................................21 3 table 8.9-3 port 6 register functions ........................................................................................... ...........214 table 8.9-4 states of port 6 pins ............................................................................................... .............217 table 9.1-1 intervals for the timebase timer .................................................................................... .......222 table 9.1-2 clock cycle time supplied from the timebase timer .............................................................223 table 9.3-1 function description of each bit in the timebase timer control register (tbtc) ...................227 table 9.4-1 timebase interrupts and ei2os ....................................................................................... ...228 table 9.5-1 timebase timer counter clearing and oscillation stabilization wait intervals ........................231 table 10.1-1 intervals for the watchdog timer .................................................................................. .......238 table 10.3-1 function description of each bit of the watchdog timer control register (wdtc) ................241 table 11.1-1 16-bit reload timer operating modes ................................................................................ ....248 table 11.1-2 intervals for the 16-bit reload timer .............................................................................. ........249 table 11.1-3 16-bit reload timer interrupts and ei2os ........................................................................... ..250 table 11.3-1 16-bit reload timer pins ........................................................................................... .............254 table 11.4-1 function description of each bit of the upper part of the timer control status register (tmcsr0, tmcsr1: h) .................................................................................................................... ...257 table 11.4-2 function description of each bit of the low part of the timer control status register (tmcsr0, tmcsr1: l) ........................................................................................259 table 11.5-1 interrupt control bits and interrupt causes of the 16-bit reload timer ...................................262 table 11.5-2 16-bit reload timer interrupts and ei2os ........................................................................... ..262 table 12.3.1.3-1 timer control status register (upper) bit ..................................................................... ......295 table 12.3.1.3-2 timer control status register (lower) ......................................................................... .......297 table 12.3.2.2-1 compare control register (upper, osc1/3/5) bit ..............................................................30 1 table 12.3.2.2-2 compare control register (lower, osc0/2/4) .................................................................... 303 table 12.3.3.2-1 capture control register (ics23) bit .......................................................................... ........307 table 12.3.3.2-2 capture control register (ics01) .............................................................................. .........309 table 12.3.4.1-1 function of ppg reload registers .............................................................................. .........311 table 12.3.4.2-1 ppg1/3/5 control register (ppgc1/3/5) bit ..................................................................... ..313 table 12.3.4.2-2 ppg0/2/4 control register (ppg0/2/4) .......................................................................... .....315 table 12.3.4.3-1 ppg0/1/2/3/4/5 clock control register (ppg0/2/4) ............................................................31 7 table 12.3.5.2-1 8-bit timer control registers (dtcr0/1/2) bit ................................................................. ...321 table 12.3.5.3-1 waveform control register (sigcr) ............................................................................. .....323 table 12.4.4-1 reload operation and pulse output ................................................................................ .....334 table 13.1-1 uart functions ..................................................................................................... ..............352 table 13.1-2 uart interrupt and ei2os ..................................................................................................353 table 13.3-1 uart pins .......................................................................................................... .................358 table 13.4-1 functions of each bit of serial control register (scr0/1) .....................................................363
xx MB90560 series table 13.4-2 functions of each bit of serial mode control register (smr0/1) .......................................... 365 table 13.4-3 functions of each bit of serial status register (ssr0/1) ..................................................... 367 table 13.4-4 communication prescaler ............................................................................................ ....... 370 table 13.5-1 interrupt control bits and interrupt causes of uart ........................................................... 372 table 13.5.2 uart interrupts and ei2os ................................................................................................ 373 table 13.6-1 selection of each division ratio for the machine clock prescaler ........................................ 378 table 13.6-2 selection of synchronous baud rate division ratios ............................................................ 379 table 13.6-3 selection of synchronous baud rate division ratios ............................................................ 379 table 13.6-4 baud rates and reload values ....................................................................................... ...... 383 table 13.7-1 uart operation mode ................................................................................................ ........ 386 table 13.7-2 selection of the master-slave communication function ...................................................... 395 table 14.1-1 overview of the dtp/external interrupt circuit .................................................................... 4 02 table 14.1-2 interrupt of the dtp/external interrupt circuit and ei2os .................................................. 403 table 14.3-1 dtp/external interrupt circuit pins ................................................................................ ...... 406 table 14.4-1 function description of each bit of the dtp/interrupt cause register (eirr) ..................... 409 table 14.4-2 function description of each bit of the dtp/interrupt enable register (enir) .................... 410 table 14.4-3 correspondence between the dtp/interrupt control registers (eirr and enir) and each channel .................................................................................. 411 table 14.4-4 function description of each bit of the request level setting register (elvr) .................... 412 table 14.4-5 correspondence between request level setting register (elvr) and each channel ......... 413 table 14.5-1 control bit and interrupt cause of the dtp/external interrupt circuit .................................. 415 table 16.1-1 8/10-bit a/d converter conversion modes .......................................................................... 43 2 table 16.1-2 8/10-bit a/d converter interrupts and ei2os ....................................................................... 4 33 table 16.3-1 8/10-bit a/d converter pins ........................................................................................ ......... 436 table 16.4-1 function description of each bit of a/d control status register 1 (adcs1) ......................... 440 table 16.4-2 function description of each bit of a/d control status register 0 (adcs0) ......................... 443 table 16.4-3 function description of each bit of a/d control status register 0 (adcs0) ......................... 445 table 16.5-1 interrupt control bits of the 8/10-bit a/d converter and the interrupt cause ........................ 446 table 16.5-2 8/10-bit a/d converter interrupts and ei2os ....................................................................... 4 46 table a i/o map ................................................................................................................ .............. 479 table a i/o map (continued) ..................................................................................................... ....... 480 table a i/o map (continued) ..................................................................................................... ....... 481 table a i/o map (continued) ..................................................................................................... ....... 482 table a i/o map (continued) .................................................................................................... ....... 483 table a i/o map (continued) ..................................................................................................... ....... 484 table b.2-1 effective-address field ............................................................................................. ........... 489 table b.3-1 callv vectors ....................................................................................................... ............. 495 table b.5-1 number of execution cycles for each type of addressing .................................................. 503
MB90560 series xxi table b.5-1 number of execution cycles for each type of addressing (continued) ................................504 table b.5-2 compensation values for calculating the number of execution cycles ................................504 table b.5-3 compensation values for calculating number of cycles for program fetch ..........................505 table b.6-1 effective-address field ............................................................................................. ............506 table b.7-1 items covered in instruction list .................................................................................. ........507 table b.7-1 symbols used in the instruction list (continued) ..................................................................50 8 table b.7-1 symbols used in the instruction list (continued) ..................................................................50 9 table b.8-1 transfer instructions (byte): 41 instructions ...................................................................... .510 table b.8-2 transfer instructions (word, long-word): 38 instructions .....................................................511 table b.8-3 addition/subtraction (byte, word, long-word): 42 instructions .............................................512 table b.8-4 increment/decrement (byte, word, long-word): 12 instructions ..........................................513 table b.8-5 comparison (byte, word, long-word): 11 instructions .........................................................513 table b.8-6 unsigned multiplication/division (word, long-word): 11 instructions ...................................514 table b.8-7 logical 1 (byte, word): 39 instructions ............................................................................ ....515 table a.2-1 logical 2 (long-word): 6 instructions .............................................................................. .....516 table b.8-9 sign inversion (byte, word): 6 instructions ........................................................................ ..516 table b.8-10 normalization (long-word): 1 instruction .......................................................................... ...516 table b.8-11 shift instructions (byte, word, long-word): 18 instructions ..................................................517 table b.8-12 branching instructions (1): 31 instructions ....................................................................... ..518 table b.8-13 branch instructions (2): 19 instructions .......................................................................... ....519 table b.8-14 other control instructions (byte, word, long-word): 28 instructions ....................................520 table b.8-15 bit operation instructions: 21 instructions ....................................................................... ....521 table b.8-16 accumulator operation instructions (byte, word): 6 instructions .........................................521 table b.8-17 string instructions: 10 instructions .............................................................................. ........522 table b.9-1 example instruction codes ........................................................................................... .......524 table b.9-2 basic page map ...................................................................................................... .............525 table b.9-3 bit operation instruction map (1st byte = 6ch) ....................................................................52 6 table b.9-4 character string operation instruction map (1st byte = 6eh) ..............................................527 table b.9-5 2-byte instruction map (1st byte = 6fh) ............................................................................. .528 table b.9-6 ea instruction map (1) (1st byte = 70h) ............................................................................. ..529 table b.9-7 ea instruction map (2) (1st byte = 71h) ............................................................................. ..530 table b.9-8 ea instruction map (3) (1st byte = 72h) ............................................................................. ..531 table b.9-9 ea instruction map (4) (1st byte = 73h) ............................................................................. ..532 table b.9-10 ea instruction map (5) (1st byte = 74h) ............................................................................ ...533 table b.9-11 ea instruction map (6) (1st byte = 75h) ............................................................................ ...534 table b.9-12 ea instruction map (7) (1st byte = 76h) ............................................................................ ...535 table b.9-13 ea instruction map (8) (1st byte = 77h) ............................................................................ ...536 table b.9-14 ea instruction map (9) (1st byte = 78h) ............................................................................ ...537
xxii MB90560 series table b.9-15 movea rwi,ea instruction map (1st byte = 79h) .............................................................. 538 table b.9-16 mov ri,ea instruction map (1st byte = 7ah) ...................................................................... 539 table b.9-17 movw rwi,ea instruction map (1st byte = 7bh) .............................................................. 540 table b.9-18 mov ea,ri instruction map (1st byte = 7ch) ..................................................................... 541 table b.9-19 movw ea,rwi instruction map (1st byte = 7dh) ............................................................... 542 table b.9-20 xch ri,ea instruction map (1st byte = 7eh) ...................................................................... 543 table b.9-21 xchw rwi,ea instruction map (1st byte = 7fh) ................................................................ 544 table c-1 correspondence between external control pins and flash memory control signals ............ 546 table c-2 pin settings for read/write access in flash memory mode .................................................. 548
chapter 1 overview this chapter describes the features of the MB90560 series. 1.1 features ............................................................................................. 2 1.2 product lineup ................................................................................... 4 1.3 block diagram .................................................................................... 5 1.4 pin assignments................................................................................. 6 1.5 package dimensions........................................................................ 10 1.6 pin functions.................................................................................... 14 1.7 i/o circuit types............................................................................... 18 1.8 notes on handling devices .............................................................. 20
2 chapter 1 overview MB90560 series 1.1 features the MB90560 series of general-purpose 16-bit microcontrollers was developed for applications that require high-speed real-time processing in a variety of industrial systems, oa equipment, and process control systems. a specific feature of the series is a built-in multifunctional timer that can easily output desired waveforms. the instruction set inherits the at architecture of the original fujitsu fmc-8l and fmc-16l, and has additional instructions supporting high-level languages. in addition, it has an extended addressing mode, enhanced multiply/divide instructions (signed), and reinforced bit manipulation instructions. the chip also has a 32-bit accumulator that enables long-word data to be processed. n features of the MB90560 series l clock ? built-in pll clock multiplying circuit ? selectable operating clock (pll clock): the source oscillation can be divided by two or multiplied by 1 to 4 (4 to 16 mhz when the source oscillation is 4 mhz). ? minimum instruction execution time: 62.5 ns (when the source oscillation is 4 mhz, pll clock is multiplied by 4, and vcc is 5 v) l maximum memory address space: 16m bytes internal 24-bit addressing l optimum instruction set for controller applications ? many data types (bit, byte, word, and long word) ? as many as 23 addressing modes ? high code efficiency ? enhanced high-precision arithmetic operation by a 32-bit accumulator ? enhanced signed multiply/divide instructions and reti instruction function l instruction set supporting high-level language (c) and multitasking ? system stack pointer ? instruction set symmetry and barrel shift instructions l sleep mode (the operating clock of the cpu stops.) l program patch function (two-address pointer) l increased execution speed 4-byte instruction queue l enhanced interrupt function (eight programmable priority levels) powerful interrupt function of 32 factors l data transfer function (extended intelligent i/o service function using up to 16 channels) l lower-power consumption (standby mode)
MB90560 series chapter 1 overview 3 ? sleep mode (in which the cpu operating clock stops) ? time-base timer mode (in which only the source oscillation and time-base timer are active) ? stop mode (in which the source oscillation stops) ? cpu intermittent operation mode l packages ? qfp-64 (fpt-64p-m09: 0.65 mm pin pitch, fpt-64p-m06: 1.00 mm pin pitch) ? sh-dip (dip-64-m01: 1.778 pin pitch) l process : cmos technology n internal peripheral functions (resources) l i/o ports: up to 50 posts l 18-bit time-base timer: 1 channel l watchdog timer: 1 channel l 16-bit reload timer: 2 channels l advanced timer: 1 channel ? 16-bit free running timer: 1 channel ? 16-bit output compare: 6 channels when the count of the 16-bit free running timer matches the count set for comparison, the output compare unit inverts the output and generates an interrupt request. ? 16-bit input capture: 4 channels when the edge of the pin input is detected, the input capture unit latches the count of the 16-bit free running timer and generates an interrupt request. ? 8-/16-bit ppg timer: 8 bits x 6 channels or 16 bits x 3 channels capable of changing the period or duty cycle of the output pulses as desired. ? waveform generation circuit (8-bit timer: 3 channels) capable of generating optimum waveforms for inverter control. l uart: 2 channels ? with full duplex double buffer (8-bit length) ? capable of asynchronous or synchronous transfer (i/o extended serial) l dtp/external interrupt (8 channels) module for activating the extended intelligent i/o service by external input and for generating an external interrupt l delayed interrupt generator module generates an interrupt request for task switching. l 8/10-bit a/d converter (8 channels) ? selectable resolution of 8 or 10 bits ? capable of activation by external trigger
4 chapter 1 overview MB90560 series 1.2 product lineup table 1.2-1 shows the product lineup of the MB90560 series. the specifications excluding the rom and ram capacities are common for the series. n product lineup table 1.2-1 product lineup of the MB90560 series device mb90v560 mb90f562 mb90561 mb90562 type evaluation device flash type rom mass-production product (mask rom) rom size 64k byte 32k byte ram size 4k byte 2k byte 1k byte cpu function number of basic instructions : 351 minimum instruction execution time : 62.5 ns/4 mhz (when pll clock is multiplied by 4) number of addressing modes : 23 program patch function : 2-address pointer maximum memory address space : 16m bytes port i/o ports (cms): 50 uart with a full duplex double buffer. capable of synchronous or asynchronous clock transfer. usable also for serial i/o. dedicated built-in baud rate generator. two channels built-in 16-bit reload timer 16-bit reload timer operation (toggle output or one-shot selectable) choice of the event count function. two channels built-in. advanced timer 16-bit free running timer x 1 channel, 16-bit output compare x 6 channels, 16-bit input capture x 4 channels 8-/16-bit ppg timer (8-bit mode x 6 channels, 16-bit mode x 3 channels) waveform generation circuit: 8-bit timer x 3 channels three-phase waveform output, dead time output 10-bit a/d con- verter 10-bit resolution x 8 channels (input multiplex) conversion time:6.13 m or less (operation at internal 16 mhz clock) external inter- rupt independent 8 channels interrupt cause: l-to-h edge, h-to-l edge, l-level, or h-level selectable low-power con- sumption mode sleep mode, stop mode, and cpu intermittent mode process cmos package pga256 qfp-64 (0.65 or 1.00 mm pitch), shdip-64 operating volt- age 5v10% @16mhz
MB90560 series chapter 1 overview 5 1.3 block diagram figure 1.3-1 shows the block diagram of the MB90560 series. n block diagram figure 1.3-2 block diagram x0 rstx ram rom 7 note: p00 to p07 (8 channels): with registers that can be used as input pull-up resistors p10 to p17 (8 channels): with registers that can be used as input pull-up resistors f 2 mc-16lx bus clock control interrupt controller dtp/external interrupt circuit p00-07 cmos i/o port 0 cmos i/o port 5 cmos i/o port 1, 2, 3, 4 ,6 8 address match detect rom mirroring p30/rto0 (u) p31/rto1 (x) p32/rto2 (v) p33/rto3 (y) p34/rto4 (w) p35/rto5 (z) p63/int7/dtt p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 cpu f 2 mc-16lx series core delayed interrupt generator timebase timer avcc avr avss a/d converter 8 (8/10 bits) reset circuit (watch-dog timer) vss x2, vcc x 1, md0-2 and c other pins 8/16-bit ppg (ch0/1/2) 16-bit input capture (ch0/1/2/3) 16-bit free-run timer 16-bit output (ch0~5) compare waveform generator multi-function timer 6 4 p41/ppg0 to p46/ppg6 p24/in0 to p27/in3 p17/frck uart (ch 0) uart (ch 1) 16-bit timer 16-bit timer (ch 0) (ch 1) p36/sin0 p37/sout0 p40/sck0 p60/sin1 p61/sout1 p62/sck1 p20/tin0 p21/to0 p22/tin1 p23/to1 p10/int0 to p16/int6 8 x1 4 6
6 chapter 1 overview MB90560 series 1.4 pin assignments this section provides the pin assignments for the following three MB90560 series packages: ? fpt-64p-m06 ? fpt-64p-m09 ? dip-64p-m01 n pin assignment of fpt-64p-m06 figure 1.4-1 shows the pin assignment of the fpt-64p-m06. figure 1.4-1 pin assignment of fpt-64p-m09 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 20 21 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 52 53 54 55 56 57 58 59 60 61 62 63 64 p45/ppg4 p46/ppg5 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 avcc avr avss p60/sin1 p61/sot1 p62/sck1 rstx md1 md2 x0 x1 vss p00 p01 p02 p03 p04 p05 p06 p10/int0 p11/int1 p12/int2 p13/int3 p14/int4 p15/int5 p16/int6 p17/frck p20/tin0 p21/to0 p22/tin1 p23/to1 p24/in0 p25/in1 p26/in2 p27/in3 vcc p31/rto1 p32/rto2 p33/rto3 p34/rto4 p35/rto5 c p36/sin0 p37/sot0 p40/sck0 p41/ppg0 p42/ppg1 p43/ppg2 < top view > 17 p63/int7/dtti 18 md0 19 p07 49 50 51 vss p30/rto0 p45/ppg3 28 29 26 27 24 25 22 23 30 31 32
MB90560 series chapter 1 overview 7 n pin assignment of fpt-64p-m09 figure 1.4-2 shows the pin assignment of the fpt-64p-m09. figure 1.4-2 pin assignment of fpt-64p-m09 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p45/ppg4 p46/ppg5 p50/an0 p51/an1 p52/an2 p53/an3 p54/an4 p55/an5 p56/an6 p57/an7 avcc avr avss p60/sin1 p61/sot1 p62/sck1 p63/in7/dtti md0 rstx md1 md2 x0 x1 vss p00 p01 p02 p03 p04 p05 p06 p07 p10/int0 p11/int p12/int2 1 p13/int3 p14/int4 p15/int5 p16/int6 p17/frck p20/tin0 p21/to0 p22/tin p23/to1 p24/in0 p25/in1 p26/in2 p27/in3 vcc p30/rto0 p31/rto1 p32/rto2 p33/rto3 p34/rto4 p35/rto5 c p36/sin0 p37/sot0 p40/sck0 p41/ppg0 p42/ppg1 p43/ppg2 p44/ppg3 vss < top view > 22 23 24 25 26 27 28 29 30 31
8 chapter 1 overview MB90560 series n pin assignment of dip-64p-m01 figure 1.4-3 shows the pin assignment of the dip-64p-m01. figure 1.4-3 pin assignment of dip-64p-m01 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 p44/ppg3 p45/ppg4 p27/in3 p26/in2 p25/in1 p24/in0 vcc vss p00 p01 p02 p03 p04 p05 p06 p07 p10/int0 p11/int1 p12/int2 p13/int3 p14/int4 p15/int5 p16/int6 p17/frck p20/tin0 p21/to0 p22/tin1 p23/to1 p35/rto5 p34/rto4 p33/rto3 p32/rto2 p31/rto1 p30/rto0 p51/an1 p53/an3 p55/an5 avr p50/an0 p52/an2 p54/an4 p56/an6 p57/an7 avcc avss p40/sck0 md0 rstx md1 md2 x0 x1 vss p60/sin1 p61/sot1 p62/sck1 c p37/sot0 p41/ppg0 p42/ppg1 p43/ppg2 p46/ppg5 p36/sin0 < top view > p63/int7/dtti
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10 chapter 1 overview MB90560 series 1.5 package dimensions this section provides the dimensions of the following three MB90560 series packages: ? fpt-64p-m06 ? fpt-64p-m09 ? dip-64p-m01 n fpt-64p-m06 figure 1.5-1 shows the dimensions of the fpt-64p-m06 package. figure 1.5-1 dimensions of fpt-64p-m06 package c 1994 fujitsu limited f64013s-3c-2 0.20(.008) m "b" 0.10(.004) 0.63(.025)max 0.18(.007)max details of "a" part 0 10 1.20?.20 details of "b" part (.047?008) 24.70?.40(.972?016) 20.00?.20(.787?008) 18.70?.40 (.736?016) 12.00(.472) ref 16.30?.40 (.642?016) 14.00?.20 (.551?008) 0.05(.002)min (stand off) 22.30?.40(.878?016) 18.00(.709)ref 0.15?.05(.006?002) 1.00(.0394) 0.40?.10 (.016?004) typ index 20 19 1 33 51 0.30(.012) 0.25(.010) 32 52 64 lead no. "a" 3.35(.132)max (mounting height)
MB90560 series chapter 1 overview 11 n fpt-64p-m09 figure 1.5-1 shows the dimensions of the fpt-64p-m09 package. figure 1.5-2 dimensions of fpt-64p-m09 package c 1994 fujitsu limited f64018s-1c-2 0.13(.005) m 0.10(.004) 1 pin index .005 ?001 +.002 ?.02 +0.05 0.127 .059 ?004 +.008 ?.10 +0.20 1.50 "a" details of "a" part 0 10 0.50?.20 0.10?.10 (.004?004) (.020?008) 14.00?.20(.551?008)sq 12.00?.10(.472?004)sq 0.65(.0256)typ 0.30?.10 (.012?004) 9.75 13.00 (.384) ref (.512) nom 116 17 32 33 48 49 64 (stand off) lead no. (mounting height)
12 chapter 1 overview MB90560 series n dip-64p-m01 figure 1.5-3 shows the dimensions of the dip-64p-m01 package. figure 1.5-3 dimensions of dip-64p-m01 package c 1994 fujitsu limited d64001s-3c-4 58.00 +0.22 ?.55 +.008 ?022 2.283 17.00?.25 (.669?010) index-1 5.65(.222)max 3.00(.118)min 0.51(.020)min 0.45?.10 (.018?004) +.020 ? .039 ? +0.50 1.00 1.778?.18 (.070?007) 1.778(.070) max 0.25?.05 (.010?002) 19.05(.750) typ 15?ax index-2 55.118(2.170)ref
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14 chapter 1 overview MB90560 series 1.6 pin functions tables 1.6-1 to 1.6-3 summarize the pin names, circuit types, states at reset time, and functions. n pin functions table 1.6-1 pin functions * 1 : fpt-64p-m09 * 2 : fpt-64p-m06 * 3 : dip-64p-m01 pin no. pin name circuit type pin status during reset function qfpm09* 1 qfpm06* 2 sdip* 3 22,23 23,24 30,31 x0x1 a oscillating oscillation input pins 19 20 27 rstx b reset input external reset input pin 25~32 26~33 33~40 p00~p07 c port input general-purpose i/o ports 33~39 39~40 41~47 p10~p16 c general-purpose i/o ports int0~6 can be used as interrupt request input channels 0 to 6. input is enabled when 1 is set in en0 to en6 in standby mode. 40 41 48 p17 c general-purpose i/o ports frck external clock input pin for free running timer 41 42 49 p20 d general-purpose i/o ports tin0 external clock input pin for reload timer 0 42 43 50 p21 d general-purpose i/o ports t00 event output pin for reload timer 0 43 44 51 p22 d general-purpose i/o ports tin1 external clock input pin for reload timer 1 44 45 52 p23 d general-purpose i/o ports t01 event output pin for reload timer 1 45~48 46~49 53~56 p24~27 d general-purpose i/o ports in0~3 trigger input pins for input capture channels 0 to 3. when input capture channels 0 to 3 are used for input operation, these pins are enabled as required and must not be used for any other i/p
MB90560 series chapter 1 overview 15 table 1.6-2 pin functions (continued) * 1 : fpt-64p-m09 * 2 : fpt-64p-m06 * 3 : dip-64p-m01 pin no. pin name circuit type pin status during reset function qfpm09* 1 qfpm06* 2 sdip* 3 50~55 51~56 58~63 p30~p35 d port input general-purpose i/o ports rt00~5 compare event output pints or waveform generator output pins. these pins output the waveforms specified at the waveform generator. they output compare events when waveforms are not generated. out- put is generated when compare event out- put is enabled. 58 59 2 p36 d port input general-purpose i/o ports sin0 serial data input pin for uart channel 0. while uart channel 0 is operating for input, the input of this pin is used as required and must not be used for any other input. 59 60 3 p37 d general-purpose i/o ports s0t0 serial data output pin for uart channel 0. this function is enabled when uart channel 0 enables data output. 60 61 4 40 d general-purpose i/o ports sck0 serial clock i/o pin for uart channel 0. this function is enabled when uart channel 0 enables clock output. 61~64, 1,2 62~64, 1~3 5~10 p41~p46 f general-purpose i/o ports ppg0~5 output pins for ppg channels 0 to 5. this function is enabled when ppg channels 0 to 5 enable output. 3~10 4~11 11~18 p50~p57 e analog input general-purpose i/o ports an0~7 a/d converter analog input pins. this function is enabled when the analog input specification is enabled. (ader) 11 12 19 avcc g power input vss power input pin for analog circuits
16 chapter 1 overview MB90560 series table 1.6-3 pin functions (continued) * 1 : fpt-64p-m09 * 2 : fpt-64p-m06 * 3 : dip-64p-m01 pin no. pin name circuit type pin status during reset function qfpm09* 1 qfpm06* 2 sdip* 3 12 13 20 avr h vref+ input pin for the a/d converter. this voltage must not exceed vcc. vref- is fixed to avss. 13 14 21 avss g power input vss power input pin for analog circuits 14 15 22 p60 d power input general-purpose i/o ports sin1 serial data input pin for uart channel 1. while uart channel 1 is operating for input, the input of this pin is used as required and must not be used for any other input. 15 16 23 p61 d general-purpose i/o ports s0t1 serial data output pin for uart channel 0. this function is enabled when uart channel 1 enables data output. 16 17 24 p62 d port input general-purpose i/o port sck1 serial clock i/o pin for uart channel 1. this function is enabled when uart channel 1 enables clock output. 17 18 25 p63 d general-purpose i/o port dtt1 rton pins for fixed-level input. this function is enabled when the waveform generator enables input. int7 usable as interrupt request input channel 7. input is enabled when 1 is set in en7 in standby mode. 57 58 1 c g capacitance pin power input capacitance pin for power stabilization. connect a ceramic capacitor of about 0.1 m f to the outside. 18 19 26 md0 b input pin for operation mode specifica- tion. connect this pin directly to vcc or vss. 20,21 21,22 28,29 md1,md2 b input pin for operation mode specifica- tion. connect this pin directly to vcc or vss. 24,49 25,50 32,57 vss C power (5 v) input pin 56 57 64 vcc C power (5 v) input pin
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18 chapter 1 overview MB90560 series 1.7 i/o circuit types table 1.7-1 summarizes the i/o circuit types of the MB90560 series. n i/o circuit types table 1.7-1 i/o circuit types classification circuit type remarks a ? oscillation circuit oscillation feedback resistance: about 1 m w b ? hysteresis input pin resistance: about 50k w (typ) c ? cmos hysteresis input pin with pull-up control cmos level output cmos hysteresis input (with standby control for input rejection) pull-up resistance: about 50k w (typ) i ol =4ma d ? cmos hysteresis i/o pin cmos level output cmos hysteresis input (with standby control for input rejection) i ol =4ma x1 x0 standby control signal xout r pull-up control signal pout nout hysteresis inpu t standby control r r pout nout hysteresis input standby control r
MB90560 series chapter 1 overview 19 table 1.7-2 i/o circuit types (continued) classification circuit type remarks e ? analog/cmos hysteresis i/o pin cmos level output cmos hysteresis input (with standby control for input rejection) analog input (analog input is enabled when the bit corresponding to ader is 1.) i ol =4ma f ? cmos hysteresis i/o pin cmos level output cmos hysteresis input (with standby control for input rejection) i ol =12ma g ? analog power input protection circuit h ? a/d converter ref+ (avr) power input pin with power protection circuit pout nout hysteresis input standby control r analog input pout nout hysteresis input standby control r in in analog input enable signal analog input enable signal
20 chapter 1 overview MB90560 series 1.8 notes on handling devices when handling devices, pay special attention to the following eight items or procedures: ? restriction of maximum rated voltage (latchup prevention) ? stabilization of supply voltage ? power-on ? treatment of unused input pins ? treatment of a/d converter power pin ? notes on external clock ? power supply pin ? analog power-on sequence of a/d converter n notes on handling devices l be sure that the maximum rated voltage is not exceeded (latchup prevention). a latchup may occur on a cmos ic if a voltage higher than vcc or lower than vss is applied to an input or output pin other than medium-to-high voltage pins. a latchup may also occur if a voltage higher than the rating is applied between vcc and vss. a latchup causes a rapid increase in the power supply current, which can result in thermal damage to an element. take utmost care that the maximum rated voltage is not exceeded. when turning the power on or off to analog circuits, be sure that the analog supply voltages (avcc, avr) and analog input voltage do not exceed the digital supply voltage (vcc). l try to keep supply voltages stable. even within the operation guarantee range of the vcc supply voltage, a malfunction can be caused if the supply voltage undergoes a rapid change. for voltage stabilization guidelines, the vcc ripple fluctuations (p-p value) at commercial frequencies (50 to 60 hz) should be suppressed to "10%" or less of the reference vcc value. during a momentary change such as when switching a supply voltage, voltage fluctuations should also be suppressed so that the "transient fluctuation rate" is 0.1 v/ms or less. l notes on power-on to prevent a malfunction in the built-in voltage regulator circuit, secure "50 m s (between 0.2 v and 2.7 v)" or more for the voltage rise time during power-on. l treatment of unused input pins an unused pin may cause a malfunction if it is left open. every unused pin should be pulled up or down. l treatment of a/d converter power pin when the a/d converter is not used, connect the pins as follows: avcc =vcc, avss = avr = vss.
MB90560 series chapter 1 overview 21 l notes on external clock when an external clock is used, the oscillation stabilization wait time is required at power-on reset or at cancellation of stop mode. as shown in figure 1.8-1, when an external clock is used, connect only the x0 pin and leave the x1 pin open. figure 1.8-1 sample connection of external clock l power supply pins when a device has two or more vcc or vss pins, the pins that should have equal potential are connected within the device in order to prevent a latchup or other malfunction. to reduce extraneous emission, to prevent a malfunction of the strobe signal due to an increase in the group level, and to maintain the local output current rating, connect all these power supply pins to an external power supply and ground them. the current source should be connected to the vcc and vss pins of the device with minimum impedance. it is recommended that a bypass capacitor of about 0.1 m f be connected near the terminals between vcc and vss. l analog power-on sequence of a/d converter the power to the a/d converter (avcc, avrh, avrl) and analog inputs (an0 to an7) must be turned on after the power to the digital circuits (vcc) is turned on. when turning off the power, turn off the power to the digital circuits (vcc) after turning off the power to the a/d converter and analog inputs. when the power is turned on or off, avr should not exceed avcc. also, when a pin that is used for analog input is also used as an input port, the input voltage should not exceed avcc. (the power to the analog circuits and the power to the digital circuits can be simultaneously turned on or off.) x0 x1 open MB90560 series

chapter 2 cpu this chapter describes memory space for the MB90560 series. 2.1 cpu.................................................................................................. 24 2.2 memory space ................................................................................. 26 2.3 memory maps................................................................................... 28 2.4 addressing ....................................................................................... 29 2.5 memory location of multibyte data.................................................. 34 2.6 registers .......................................................................................... 36 2.7 dedicated registers ......................................................................... 38 2.8 general-purpose registers.............................................................. 56 2.9 prefix codes..................................................................................... 58
24 chapter 2 cpu MB90560 series 2.1 cpu the f2mc-16lx cpu core is a 16-bit cpu designed for use in applications, such as consumer and mobile equipment, which require high-speed real-time processing. the instruction set of the f2mc-16lx was designed for controllers so that it can perform various types of control at high speeds and efficiencies. the f2mc-16lx cpu core process not only 16-bit data but also 32-bit data using a built- in 32-bit accumulator. memory space, which can be extended up to 16m bytes, can be accessed in either linear or bank access mode. the instruction set inherits the at architecture of f2mc-8l, and has additional instructions supporting high-level languages. in addition, it has an extended addressing mode, enhanced multiply/divide instructions, and reinforced bit manipulation instructions. n cpu l minimum instruction execution time: 62.5 ns (source oscillation at 4 mhz and pll clock multiplication by 4) l maximum memory address space: 16m bytes. access in linear or bank mode l instruction set optimum for controller applications many data types (bit, byte, word, and long word) as many as 23 addressing modes enhanced high-precision arithmetic operation by a 32-bit accumulator enhanced signed multiply/divide instructions and reti instruction function l enhanced interrupt function eight programmable priority levels l automatic transfer function independent of cpu extended intelligent i/o service using up to 16 channels l instruction set supporting high-level language (c language) and multitasking system stack pointer, instruction set symmetry, and barrel shift instructions l increased execution speed: 4-byte instruction queue the MB90560 series runs only in single-chip mode so only internal rom and ram and internal peripheral address space can be accessed.
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26 chapter 2 cpu MB90560 series 2.2 memory space all i/o, programs, and data are located in the 16-megabyte memory space of the f 2 mc-16lx. a part of the memory space is used for special purposes, such as extended intelligent i/o service (ei2os) descriptors, general-purpose registers, and vector tables. n memory space all i/o, programs, and data are located in the 16-megabyte memory space of the f 2 mc-16lx cpu. the cpu is able to access each resource through an address indicated by the 24-bit address bus. figure 2.2-1 shows a sample relationship between the f 2 mc-16lx system and the memory map. figure 2.2-1 sample relationship between the f 2 mc-16lx system and the memory map f 2 mc-16l device programs internal bus data interrupts peripheral circuits general-purpose ports vector table area program area rom area external area (*4) rom area (ff data area general-purpose register ei2os de- ram area i/o area peripheral function control i/o port control register area bank image) control register area interrupt control register area scriptor area *1 the size of internal rom differs for each model. *2 the area accessible by the image differs for each model. *3 the size of internal ram differs for each model. *4 there is no access in single-chip mode. register area external area (*4) external area (*4)
MB90560 series chapter 2 cpu 27 n rom area l vector table area (address: fffc00 h to ffffff h ) ? this area is used as a vector table for vector call instructions, interrupt vectors, and reset vectors. ? this area is allocated at the highest addresses of the rom area. the starting address of the corresponding processing routine is stored as data in each vector table address. l program area (address: up to fffbff h ) ? rom is built in as an internal program area. ? the size of internal rom differs for each device. n ram area l data area (address: from 000100 h ) ? the static ram is built in as an internal data area. ? the size of internal ram differs for each device. l general-purpose register area (address: 000180 h to 00037f h ) ? auxiliary registers used for 8-bit, 16-bit, and 32-bit arithmetic operations and transfer operation are allocated in this area. ? since this area is allocated to a part of the ram area, it can be used as ordinary ram. ? when this area is used as a general-purpose register, general-purpose register addressing enables high-speed access with short instructions. l extended intelligent i/o service (ei2os) descriptor area (address: 000100 h to 00017f h ) ? this area retains the transfer modes, i/o addresses, transfer count, and buffer addresses. ? since this area is allocated to a part of the ram area, it can be used as ordinary ram. n i/o area l interrupt control register area (address: 0000b0 h to 0000bf h ) the interrupt control registers (icr00 to icr15) correspond to all peripheral functions that have an interrupt function. these registers set interrupt levels and control the extended intelligent i/o service (ei2os). l peripheral function control register area (address: 000020 h to 0000af h ) this register controls the built-in peripheral functions and inputs and outputs data. l i/o port control register area (address: 000000 h to 00001f h ) this register controls i/o ports, and inputs and outputs data.
28 chapter 2 cpu MB90560 series 2.3 memory maps this section shows the memory map for each MB90560 series device. n memory maps figure 2.3-1 shows the memory maps for the MB90560 series. figure 2.3-1 memory maps notes: if single chip mode (without mirror rom function) is selected, see "mirror rom function selection module." : rom data in the ff bank can be seen as an image in the higher 00 bank to validate the small model c compiler. because addresses of the 16 low-order bits in the ff bank are the same, the table in rom can be referenced without the "far" specification. for example, when 00c000h is accessed, the contents of rom at ffc000h are actually accessed. the rom area in the ff bank exceeds 48 kilobytes, and all areas cannot be seen as images in the 00 bank. because rom data from ff4000h to ffffffh is seen as an image at 004000h to 00ffffh, the rom data table should be stored in the area from ff4000h to ffffffh. : internal access memory : access not allowed ffffff h address #1 ff0000 h rom area 010000 h address #2 rom area (ff bank image) 004000 h address #3 000100 h ram area register *1 *1 000000 h 0000c0 h peripheral area single chip mode (with mirror rom function) model address #1 address #2 address #3 mb90561 ff8000h 008000h 000500h mb90562 ff0000h 004000h 000900h mb90f562 ff0000h 004000h 000900h mb90v560 ff0000h 004000h 001100h *1: the mb90v560 does not contain rom. assume these areas such that the development tool uses there for its rom decode areas.
MB90560 series chapter 2 cpu 29 2.4 addressing the methods for generating addresses are linear addressing and bank addressing. in linear addressing, the complete 24-bit address is specified directly by an instruction. in bank addressing, the upper 8 bits of the address are specified by a appropriate bank register, and the lower 16 bits of the address are specified by the instruction. the f 2 mc-16lx series generally uses bank addressing. n linear addressing and bank addressing in linear addressing, the 16-megabyte space is accessed as consecutive address spaces. in bank addressing, the 16-megabyte space is managed by dividing into 256 64-kilobyte banks. figure 2.4-1 is an overview of linear addressing and bank addressing memory management. figure 2.4-1 linear addressing and bank addressing memory management linear addressing bank addressing ff bank fe bank fd bank 00 bank 01 bank 02 bank 03 bank 04 bank 12 bank specified entirely by an instruction specified by an instruction specified by a bank register for the required purpose 64 kilobytes
30 chapter 2 cpu MB90560 series 2.4 addressing 2.4.1 linear addressing the two types of address in linear addressing are specified by a 24-bit address directly in the operand and specified by the lower 24 bits of a 32-bit general-purpose register. n linear addressing specified by 24-bit operand figure 2.4-2 example of direct specified 24-bit physical address in linear addressing n addressing by indirect specification with a 32-bit register figure 2.4-3 example of indirect specified address with a 32-bit general-purpose register in linear addressing old program counter + program bank new program counter + program bank next instruction old al new al (upper 8 bits are ignored) rl1: 32-bit (long-word) general-purpose register
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32 chapter 2 cpu MB90560 series 2.4 addressing 2.4.2 bank addressing in bank addressing, the 16-megabyte memory space is divided into 256 64-kilobyte banks. a bank address that corresponds to each space is specified in the bank register to determine the upper 8 bits of the address. the lower 16 bits of the address are specified by the instruction. the five types of bank register classified by function are as follows: ? program bank register (pcb) ? data bank register (dtb) ? user stack bank register (usb) ? system stack bank register (ssb) ? additional bank register (adb) n bank registers and access space table 2.4-1 lists the access space and main function of each bank register. table 2.4-1 access space and main function of each bank register *1 the ssb is always used as an interrupt stack. figure 2.4-4 shows the relationship between the memory space divisions and each register. see section 2.7.9, "bank registers (pcb, dtb, usb, ssb, adb)," for details. bank register name access space main function initial value after a reset program bank register (pcb) program (pc) space instruction codes, vector tables, and immediate-value data are stored. ff h data bank regis- ter (dtb) data (dt) space read/write data is stored. internal or external peripheral control registers and data registers are accessed. 00 h user stack bank register (usb) stack (sp) space this area is used for stack accesses such as when push/ pop instructions and interrupt registers are saved. the ssb is used when the stack flag in the condition code reg- ister (ccr:s) is 1. the usb is used when the stack flag in the condition code register (ccr:s) is 0. (*1) 00 h system stack bank register (ssb) (*1) 00 h additional bank register (adb) additional (ad) space data that overflows from the data (dt) space is stored. 00 h
MB90560 series chapter 2 cpu 33 figure 2.4-4 sample bank addressing n bank addressing and default space to improve instruction coding efficiency, each instruction has a pre-determined default space for each addressing mode, as shown in table 2.4-2. to use a space other than the default space, specify a prefix code for a bank before the instruction. this enables the bank space that corresponds to the specified prefix code to be accessed.see section 2.9, "prefix codes," for details about prefix codes. table 2.4-2 addressing and default spaces default space addressing program space pc indirect, program access, branching data space addressing using @rw0, @rw1, @rw4, and @rw5, @a, addr16, dir stack space addressing using pushw, popw, @rw3, and @rw7 additional space addressing using @rw2 and @rw6 physical address program additional space user stack space data space space system stack space : program bank register (pcb) : additional bank register (adb) : user stack bank register (usb) : data bank register (dtb) : system stack bank register (ssb)
34 chapter 2 cpu MB90560 series 2.5 memory location of multibyte data multibyte data is written to memory sequentially from the lower address. if multibyte data is 32-bit data, the lower 16 bits are transferred before the upper 16 bits. if a reset signal is input immediately after the low-order data is written, the high-order bits may not be written. n storage of multibyte data in ram figure 2.5-1 shows the data configuration of multibyte data in memory. the lower 8 bits of the data is located at address n, and subsequent data is located at address n + 1, address n + 2, address n + 3, and so on, in this sequence. figure 2.5-1 storage of multibyte data in ram n storage of multibyte operand figure 2.5-2 shows the configuration of a multibyte operand in memory. figure 2.5-2 storage of a multibyte operand address n msb: most significant bit lsb: least significant bit address n
MB90560 series chapter 2 cpu 35 n storage of multibyte data in a stack figure 2.5-3 shows the configuration of multibyte data in a stack. figure 2.5-3 storage of multibyte data in a stack n multibyte data access accessing is generally performed within a bank. for an instruction that accesses multibyte data, the address following ffff h is 0000 h in the same bank. figure 2.5-4 shows an example of executing an instruction that accesses multibyte data on a bank boundary. figure 2.5-4 multibyte data access on a bank boundary address n rw1: 35a4h rw3: 6df0h *1 stack status after execution of the pushw instruction al before execution al after execution
36 chapter 2 cpu MB90560 series 2.6 registers f 2 mc-16lx registers are classified into internal dedicated registers and built-in ram general-purpose registers. n dedicated registers and general-purpose registers dedicated registers are dedicated hardware inside the cpu and their usage are limited by cpu architecture. general-purpose registers are shared the cpu address space with ram. just like dedicated registers, general-purpose registers can be accessed without addressing. just like ordinary memory, the user can specify how the register is used. figure 2.6-1 shows the location of the dedicated registers and general-purpose registers in the device. figure 2.6-1 dedicated registers and general-purpose registers dedicated register accumulator user stack pointer system stack pointer processor status program counter direct page register program bank register data bank register user stack bank register system stack bank register additional data bank register internal bus general-purpose register
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38 chapter 2 cpu MB90560 series 2.7 dedicated registers the following 11 registers are dedicated registers in the cpu. ? accumulator (a) ? system stack pointer (ssp) ? program counter (pc) ? program bank register (pcb) ? user stack bank register (usb) ? additional data bank register (adb) ? user stack pointer (usp) ? processor status (ps) ? direct page register (dpr) ? data bank register (dpp) ? system stack bank register (ssb) n configuration of dedicated registers figure 2.7-1 shows the configuration of dedicated registers; table 2.7-1 lists the initial values of the dedicated registers. : accumulator (a) two 16-bit registers used for the storage of arithmetic operation results. the two registers can combined as a contiguous 32-bit register. be : user stack ointer (usp) 16-bit register that indicates the user stack address : system stack pointer (ssp) 16-bit register that indicates the system stack address : processor status (ps) 16-bit register that indicates the system status : direct page register (dpr) 8-bit register that specifies bits 8 to 15 of the operand address in short direct addressing : program bank register (pcb) 8-bit register that indicates the program space : data bank register (dtb) 8-bit register that indicates the data space : user stack bank register (usb) 8-bit register that indicates the user stack space : system stack bank register (ssb) 8-bit register that indicates the system stack space : additional data bank register (adb) 8-bit register that indicates the additional space : program counter (pc) 16-bit register that indicates the current instruction storage location 8 bits 16 bits 32 bits
MB90560 series chapter 2 cpu 39 figure 2.7-1 configuration of dedicated registers table 2.7-1 initial values of the dedicated registers - :not used x:undefined the above initial values are the initial values for the device. they are different from the ice (emulator, etc.) values. dedicated register initial value accumulator (a) undefined user stack pointer (usp) undefined system stack pointer (ssp) undefined processor status (ps) program counter (pc) value in reset vector (contents of ffffdc h , ffffdd h ) direct page register (dpr) 01 h program bank register (pcb) value in reset vector (contents of ffffde h ) data bank register (dtb) 00 h user stack bank register (usb) 00 h system stack bank register (ssb) 00 h additional data bank register (adb) 00 h bit15 to bit13 bit12 to bit8 bit7 to bit0
40 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.1 accumulator (a) the accumulator (a) consists of two 16-bit arithmetic operation registers (ah and al). the accumulator is used to temporarily store the results of an arithmetic operation and data. the a register can be used as a 32-bit, 16-bit, or 8-bit register. various arithmetic operations can be performed between memory and other registers or between the ah register and the al register. the a register has a data retention function that automatically transfers pre-transfer data from the al register to the ah register when data of word length or less is transferred to the al register. (data is not retained with some instructions.) n accumulator (a) l data transfer to the accumulator the accumulator can process 32-bit (long word), 16-bit (word), and 8-bit (byte) data. the 4-bit data transfer instruction (movn) is an exception. the explanation of 8-bit data also applies to 4- bit data. ? for 32-bit data processing, the ah register and al register are combined. ? for 16-bit data and 8-bit data, only the al register is used. ? when data of byte length or less is transferred the al register, data becomes 16 bits long by sign extension or zero extension, and is stored in the al register. data in the al register can be handled as word-length or byte-length data. figure 2.7-2 shows data transfer to the accumulator. figures 2.7-3 to 2.7-6 show specific transfer examples. figure 2.7-2 data transfer to the accumulator 32-bit data transfer 16-bit data transfer 8-bit data transfer 32-bit data transfer data save data transfer 00 h or ff h (*1) *1 becomes 000 h or fff h for a 4-bit transfer instruction. data transfer data save data transfer (zero extension or sign extension)
MB90560 series chapter 2 cpu 41 figure 2.7-3 example of al-ah transfer in the accumulator (a) (8-bit immediate value, zero extension) figure 2.7-4 example of al-ah transfer in the accumulator (a) (8-bit immediate value, sign extension) figure 2.7-5 example of 32-bit data transfer to the accumulator (a) (register indirect) (an instruction that zero-extends the contents at address 3000 h and stores the result in the al register) before execution after execution memory space x: msb: most significant bit lsb: least significant bit dtb: data bank register undefined (an instruction that stores the contents at address 3000 h in the al register) before execution after execution memory space x: msb: most significant bit lsb: least significant bit dtb: data bank register undefined (instruction that performs a long-word-length read using the result of the before execution after execution memory space x: msb: most significant bit lsb: least significant bit dtb: data bank register undefined rw1 contents + an 8-bit offset as the address and stores the read value in the a register)
42 chapter 2 cpu MB90560 series figure 2.7-6 example of al-ah transfer in the accumulator (a) (16 bits, register indirect) l accumulator byte-processing arithmetic operation when a byte-processing arithmetic operation instruction is executed for the al register, the upper 8 bits of the al register before the arithmetic operation is executed are ignored. the upper 8 bits of the arithmetic operation results are all zeros. l initial value of the accumulator the initial value after a reset is undefined. (instruction that performs a word-length read using the result of the before execution after execution memory space x: msb: most significant bit lsb: least significant bit dtb: data bank register undefined rw1 contents + an 8-bit offset as the address and stores the read value in the a register)
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44 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.2 stack pointers (usp, ssp) there are two types of stack pointers: a user stack pointer (usp) and a system stack pointer (ssp). each stack pointer is a register that indicates the memory address of the location of the destination for saved data or a return address when push instructions, pop instructions, and subroutines are executed. the upper 8 bits of the stack address are specified by the user stack bank register (usb) or system stack bank register (ssb). when the s flag of the condition code register (ccr) is 0, the usp and usb registers are valid. when the s flag is 1, the ssp and ssb registers are valid. n stack selection the f 2 mc-16lx uses two types of stack: a system stack and a user stack. the stack address is determined, as shown in table 2.7-2, by the s flag in the processor status register (ps:ccr). table 2.7-2 stack address specification : initial value because the s flag is initialized to 1 by a reset, the system stack is used as the default. ordinarily, the system stack is used for interrupt routine stack operations, and the user stack is used for all other types of stack operation. when separation of the stack space is not particularly necessary, only the system stack should be used. since the s flag is set to 1 when an interrupt is accepted, the system stack is always used for interrupts. figure 2.7-7 shows an example of stack operation with the system stack. s flag stack address upper 8 bits lower 16 bits 0 user stack bank register (usb) user stack pointer (usp) 1 system stack bank register (ssb) system stack pointer (ssp)
MB90560 series chapter 2 cpu 45 figure 2.7-7 stack operation instruction and stack pointer ? to set a value for the stack pointer, always use an even-numbered address. if an odd- numbered address is used, a word access is split into two parts, lowering efficiency. ? the initial values of the usp register and ssp register after a reset are undefined. n system stack pointer (ssp) to use the system stack pointer (ssp), set the s flag in the condition code register (ccr) of the processor status (ps) to 1. the upper 8 bits of the address that will be used for the stack operation are indicated by the system stack bank register (ssb). n user stack pointer (usp) to use the user stack pointer (usp), set the s flag in the condition code register (ccr) of the processor status (ps) to 0. the upper 8 bits of the address that will be used for the stack operation are indicated by the user stack bank register (usb). pushw a with the s flag set to 0 pushw a with the s flag set to 1 before execution after execution s flag s flag s flag s flag before execution after execution the user stack is used because the s flag is 0 the system stack is used because the s flag is 1 x: undefined msb: lsb: most significant bit least significant bit
46 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.3 processor status (ps) the processor status (ps) consists of cpu control bits and bits that indicate the cpu status. the ps register consists of the following three registers: ? interrupt level mask register (ilm) ? register bank pointer (rp) ? condition code register (ccr) n processor status (ps) configuration the processor status (ps) consists of cpu control bits and bits that indicate the cpu status. figure 2.7-8 shows the configuration of the processor status (ps). figure 2.7-8 processor status (ps) configuration l interrupt level mask register (ilm) this register indicates the level of the interrupt currently accepted by the cpu. the value is compared with the value of the interrupt level setting bits (icr: il0 to il2) in the interrupt control register for the peripheral resource interrupt request. l register bank pointer (rp) this pointer points to the first address of the memory block (register bank) used as the general- purpose register in the ram area. there are 32 banks for general-purpose registers. values 0 to 31 are set in the rp to specify a bank. l condition code register (ccr) this register consists of flags that are set to 1 or reset to 0 by instruction execution results and by interrupts. initial value -: x: not used undefined
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48 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.4 condition code register (ps: ccr) the condition code register (ccr) is an 8-bit register that consists of the bits that indicate the results of an arithmetic operation and the contents of transfer data and bits that control interrupt request acceptance. n condition code register (ccr) configuration figure 2.7-9 shows the configuration of the ccr register. refer to the programming manual for details about the status of the condition code register (ccr) during instruction execution. figure 2.7-9 condition code register (ccr) configuration l interrupt enable flag (i) in response to all interrupt requests other than software interrupts, when the i flag is 1, interrupts are enabled. when the i flag is 0, interrupts are disabled. this flag is cleared by a reset. l stack flag (s) this flag indicates which pointer is used for a stack operation. when the s flag is 0, the user stack pointer (usp) is valid. when the s flag is 1, the system stack pointer (ssp) is valid. set when an interrupt is accepted or when a reset occurs. l sticky bit flag (t) 1 is set in the t flag when there is at least one 1 in the data shifted out from the carry after execution of a logical/arithmetic right shift instruction. otherwise, 0 is set in t flag. in addition, 0 is set in t flag when the shift value is zero. l negative flag (n) set to 1 when the msb is 1 as the result of an arithmetic calculation. cleared to 0 when the msb is 0. l zero flag (z) set to 1 when the result of an arithmetic calculation is all zeros. otherwise, set to 0. ccr initial value interrupt enable flag stack flag sticky bit flag negative flag zero flag overflow flag carry flag -: x: not used undefined
MB90560 series chapter 2 cpu 49 l overflow flag (v) set to 1 if a signed numeric value overflows because of an arithmetic calculation. cleared to 0 if no overflow occurs. l carry flag (c) set to 1 when there is an overflow from the msb or an underflow from the lsb because of an arithmetic calculation. cleared to 0 when there is no overflow or underflow because of an arithmetic calculation.
50 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.5 register bank pointer (ps: rp) the register bank pointer (rp) is a register that indicates the first address of the general-purpose register bank currently being used. the rp is used for real address conversion when general-purpose register addressing is used. n register bank pointer (rp) figure 2.7-10 shows the configuration of the register bank pointer (rp) register. figure 2.7-10 configuration of the register bank pointer (rp) n general-purpose register area and register bank pointer the register bank pointer points to the relationship between the general-purpose register of the f 2 mc-16lx and the address in internal ram where the general-purpose register exists. figure 2.7-11 shows the conversion rules used for the relationship between the contents of the rp and the real address. figure 2.7-11 conversion rules for physical address of general-purpose register area ? since the rp takes a value from 00 h to 1f h , the first address of the register bank can be set in the range from 000180 h to 00037f h . ? although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to the rp, in actuality only the lower 5 bits of the data are used. ? the initial value of the rp register after a reset is 00 h . rp initial value b4 b0 b1 b2 b3 conversion formula when rp = 10 h register bank 31 register bank 16 register bank 0
2.7 dedicated registers MB90560 series chapter 2 cpu 51 2.7.6 interrupt level mask register (ps: ilm) the interrupt level mask register (ilm) is a 3-bit register that indicates the level of the interrupt currently accepted by the cpu. n interrupt level mask register (ilm) figure 2.7-12 shows the configuration of the interrupt level mask register (ilm). see chapter 6, "interrupts," for details about interrupts. figure 2.7-12 configuration of the interrupt level mask register (ilm) the interrupt level mask register (ilm) indicates the level of the interrupt currently accepted by the cpu. the level is compared with the value of the il0 to il2 bits of the interrupt control register (icr00 to icr15) set according to the interrupt request from the peripheral function. if the interrupt enable flag has been set to enable (ccr: i = 1), the cpu processes the instruction only when the value (interrupt level) of the interrupt request is smaller than the value indicated by these bits. ? when an interrupt is accepted, the interrupt level value is set in the interrupt level mask register (ilm). thereafter, interrupts with the same or lower level are not accepted. ? the interrupt level is set to the highest level, which is the interrupts disabled status, because the interrupt level mask register (ilm) is initialized to all 0s by a reset. ? although an assembler instruction can use an 8-bit immediate value transfer instruction for transfer to the interrupt level mask register (ilm), only the lower 3 bits of the data are used. table 2.7-3 interrupt level mask register (ilm) and interrupt level priority ilm2 ilm1 ilm0 interrupt level interrupt level priority 0 0 0 0 highest (interrupts disabled) lowest 001 1 010 2 011 3 100 4 101 5 110 6 111 7 ilm initial value
52 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.7 program counter (pc) the program counter (pc) is a 16-bit counter that indicates the lower 16 bits of the memory address of the next instruction code to be executed by the cpu. n program counter (pc) the program bank register (pcb) specifies the upper 8 bits of the address where the next instruction code to be executed by the cpu is stored. the pc specifies the lower 16 bits. before being used, the actual address is combined to become 24 bits, as shown in figure 2.7-13. the contents of the pc are updated by conditional branch instructions, subroutine call instructions, interrupts, and resets. the pc can be used as a base pointer for reading operands. figure 2.7-13 program counter (pc) the pc and pcb cannot be rewritten directly by a program (such as by mov pc and #ff). upper 8 bits upper 16 bits next instruction to be executed
2.7 dedicated registers MB90560 series chapter 2 cpu 53 2.7.8 direct page register (dpr) the direct page register (dpr) is an 8-bit register that specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed. n direct page register (dpr) as shown in figure 2.7-14, the dpr specifies bits 8 to 15 (addr8 to addr15) of the operand address when a short direct addressing instruction is executed. the dpr is 8-bits long. the dpr is initialized to 01 h by a reset. the dpr can be read and written using an instruction. figure 2.7-14 physical address generation by the direct page register (dpr) figure 2.7-15 shows an example of direct page register (dpr) setting and data access figure 2.7-15 example of direct page register (dpr) setting and data access dtb register dpr register direct address during instruction 24 bit physical address msb: lsb: most significant bit least significant bit dtb register dpr register instruction execution results upper 8 bits lower 8 bits msb: lsb: most significant bit least significant bit
54 chapter 2 cpu MB90560 series 2.7 dedicated registers 2.7.9 bank registers (pcb, dtb, usb, ssb, adb) bank registers specify the highest 8-bit address by bank addressing. the five bank registers are as follows: ? program bank register (pcb) ? data bank register (dtb) ? user stack bank register (usb) ? system stack bank register (ssb) ? additional bank register (adb) the pcb, dtb, usb, ssb, and adb registers indicate the individual memory banks where the program space, data space, user stack space, system stack space, and additional space are located. n bank registers (pcb, dtb, usb, ssb, adb) l program bank register (pcb) the pcb is a bank register that specifies the program (pc) space. the pcb is updated when a software interrupt instruction is executed, when the jmpp, callp, retp, and reti instructions that branch anywhere within the 16-megabyte space are executed, or when a hardware interrupt or exception occurs. l data bank register (dtb) the dtb is a bank register that specifies the data (dt) space. l user stack bank register (usb), system stack bank register (ssb) the usb and ssb are bank registers that specify the stack (sp) space. whether the usb or the ssb is used depends on the s flag value in the processor status (ps: ccr). see section 2.7.2, "stack pointers (usp, ssp)," for details. l additional bank register (adb) the adb is a bank register that specifies the additional (ad) space. l bank setting and data access all bank registers are byte length. the pcb is initialized to ff h by a reset. the other bank registers are initialized to 00 h by a reset. the pcb can be read, but cannot be written to. the other bank registers can be read and written to. the MB90560 series supports up to the memory space contained in the device. see section 2.4.2, "address specification by bank addressing," for the operation of each register.
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56 chapter 2 cpu MB90560 series 2.8 general-purpose registers the general-purpose registers are a memory block allocated in ram at 000180 h to 00037f h as banks, each of which consists of eight 16-bit segments. the general-purpose registers can be used as general-purpose 8-bit registers (byte registers r0 to r7), 16-bit registers (word registers rw0 to rw7), or 32-bit registers (long-word registers rl0 to rl7). general-purpose registers can access ram with a short instruction at high speed. since general-purpose registers are blocked into register banks, protection of register contents and division into function units can readily be performed. when a general- purpose register is used as a long-word register, it can be used as a linear pointer that directly accesses the entire space. n configuration of a general-purpose register all general-purpose registers exist in ram at 000180 h to 00037f h and are configured as 32 banks. the register bank pointer (rp) specifies the bank that is to be used for a general-purpose register. the rp points to the bank currently being used. the rp determines the first address of each bank with the following formula: address of first general-purpose register = 000180 h + rp x 10 h figure 2.8-1 shows the location and configuration of the general-purpose register banks in the memory space. figure 2.8-1 location and configuration of the general-purpose register banks in the memory space the register bank pointer (rp) is initialized to 00 h after a reset. built-in ram register bank 31 register bank 30 register bank 21 register bank 20 register bank 19 register bank 2 register bank 1 register bank 0 conversion formula [000180 h + rp x 10 h ] byte address byte address r0 to r7: rw0 to rw7: rl0 to rl3: msb: lsb: byte registers word registers long-word registers most sifnificant bit least significant bit
MB90560 series chapter 2 cpu 57 n register bank a register bank can be used as general-purpose registers (byte registers r0 to r7, word registers rw0 to rw7, long-word registers rl0 to rl3) for various arithmetic operations and pointers. a long-word register can be used as a linear pointer that directly accesses the entire memory space. the contents of the register bank, like ordinary ram, are not initialized by a reset. the status before a reset is retained. at power-on, however, the contents are undefined. table 2.8-1 lists the typical functions of general-purpose registers. table 2.8-1 typical functions of general-purpose registers register name function r0 to r7 used as an operand in various instructions r0 is also used as a barrel shift counter and an instruction normalization counter rw0 to rw7 used as a pointer used as an operand in various instructions rw0 is used also as a string instruction counter rl0 to rl3 used as a long pointer used as an operand in various instructions
58 chapter 2 cpu MB90560 series 2.9 prefix codes prefix codes are placed before an instruction to partially change the operation of the instruction. the three types of prefix codes are as follows: ? bank select prefix (pcb, dtb, adb, spb) ? common register bank prefix (cmr) ? flag change suppression prefix (ncc) n prefix codes l bank select prefix (pcb, dtb, adb, spb) a bank select prefix is placed before an instruction to select the memory space to be accessed by the instruction regardless of the addressing method. l common register bank prefix (cmr) the common register bank prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank (register bank selected when rp = 0) at 000180 h to 00018f h regardless of the current register bank pointer (rp) value. l flag change suppression prefix (ncc) the flag change suppression prefix code is placed before an instruction to suppress a flag change accompanying the execution of the instruction.
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60 chapter 2 cpu MB90560 series 2.9 prefix codes 2.9.1 bank select prefix (pcb, dtb, adb, spb) a bank select prefix is placed before an instruction to select the memory space accessed by the instruction regardless of the addressing method. n bank select prefixes (pcb, dtb, adb, spb) the memory space used for data access is defined for each addressing method. if a bank select prefix is placed before an instruction, the memory space accessed by the instruction can be selected regardless of the addressing method. table 2.9-1 lists the bank select prefix codes and selected memory spaces. table 2.9-1 bank select prefix codes and selected memory spaces if a bank select prefix is used, some instructions perform an unexpected operation. table 2.9-2 lists the instructions that are not affected by bank select prefix codes. table 2.9-3 lists instructions that require caution when they are used. table 2.9-2 instructions not affected by bank select prefix codes bank select prefix selected space pcb program space dtb data space adb additional space spb when the value of the s flag in the condition code register (ccr) is 0 and the user stack space is 1, the system stack space is used. instruction type instruction effect of bank select prefix string instruction movs movsw sceq scweq fils filsw the bank register specified by the operand is used regardless of whether a prefix is used. stack opera- tion pushw popw when the s flag is 0, the user stack bank (usb) is used regardless of whether there is a prefix. when the s flag is 1, the system stack bank (ssb) is used regardless of whether a prefix is used.] i/o access instruction mov a movx a, io movw a, io mov io, a movw io, a mov io, #imm8 movw io, #imm16 movb a, io : bp movb io : bp, a setb io : bp clrb io : bp bbc io : bp, rel bbs io : bp, rel wbtc io, bp wbts io : bp the i/o space (000000 h to 0000ff h ) is accessed regardless of whether there is a prefix. interrupt return instruction reti the system stack bank (ssb) is used regardless of whether a prefix is used.
MB90560 series chapter 2 cpu 61 table 2.9-3 instructions which use requires caution when bank select prefix codes are used instruction type instruction explanation flag change instruction and ccr, #imm8 or ccr, #imm8 the effect of the prefix extends to the next instruction. ilm setting instruction mov ilm, #imm8 the effect of the prefix extends to the next instruction. ps return instruction popw ps do not place a bank select prefix before the ps return instruction.
62 chapter 2 cpu MB90560 series 2.9 prefix codes 2.9.2 common register bank prefix (cmr) the common register bank (cmr) prefix is placed before an instruction that accesses a register bank to change the register accessed by the instruction to the common bank (register bank selected when rp = 0) at 000180 h to 00018f h regardless of the current register bank pointer (rp) value. n common register bank prefix (cmr) to facilitate data exchange between multiple tasks, a relatively simple means of accessing a fixed register bank regardless of the current register bank pointer (rp) value is necessary. this is the reason that the f 2 mc-16lx provides a common register bank for tasks, which is called the common bank. the common bank is located at address 000180 h to 00018f h . if the common register bank prefix (cmr) is placed before an instruction that accesses a register bank, registers accessed by the instruction can be changed to the common bank (register bank selected when rp = 0) at 000180 h to 00018fh h regardless of the current register bank pointer (rp) value. note that caution is required when this prefix is used with the instructions listed in table 2.9-4. table 2.9-4 instructions whose use requires caution when the common register bank prefix (cmr) is used instruction type instruction explanation string instruc- tion movs movsw sceq scweq fils filsw do not place the cmr prefix before the string instruction. flag change instruction and ccr, #imm8 or ccr, #imm8 the effect of the prefix extends to the next instruction. ps return instruction popw ps the effect of the prefix extends to the next instruction. ilm setting instruction mov ilm, #imm8 the effect of the prefix extends to the next instruction.
2.9 prefix codes MB90560 series chapter 2 cpu 63 2.9.3 flag change suppression prefix (ncc) the flag change suppression prefix (ncc) code is placed before an instruction to suppress a flag change accompanying the execution of the instruction. n flag change suppression prefix (ncc) the flag change suppression prefix (ncc) is used to suppress unnecessary flag changes. if a flag change suppression prefix code is placed before an instruction, a flag change accompanying the execution of the instruction is suppressed. changes of the t, n, z, v, and c flags are suppressed. note that caution is required when this prefix is used with the instructions listed in table 2.9-5. table 2.9-5 instructions requiring caution when the flag change suppression prefix (ncc) is used instruction type instruction explanation string instruc- tion movs movsw sceq scweq fils filsw do not place the ncc prefix before the string instruction. flag change instruction and ccr, #imm8 or ccr, #imm8 the condition code register (ccr) changes as defined in the instruction specification regardless of whether a prefix is used. the effect of prefix extends to the next instruction. ps return instruction popw ps the condition code register (ccr) changes as defined in the instruction specification regardless of whether a prefix is used. the effect of prefix extends to the next instruction. ilm setting instruction mov ilm, #imm8 the effect of prefix extends to the next instruction. interrupt instruction interrupt return instruction int #vct8 int9 int adder16 intp addr24 reti the condition code register (ccr) changes as defined in the instruction specification regardless of whether a prefix is used. context switch instruction jctx @a the condition code register (ccr) changes as defined in the instruction specification regardless of whether a prefix is used.
64 chapter 2 cpu MB90560 series 2.9 prefix codes 2.9.4 restrictions on prefix codes the following three restrictions are imposed on the use of prefix codes: ? interrupt/hold requests are not accepted during the execution of prefix codes and interrupt/hold suppression instructions. ? if a prefix code is placed before an interrupt/hold instruction, the effect of the prefix code is delayed. ? if consecutively placed prefix codes conflict, the last prefix code is valid. n prefix codes and interrupt/hold suppression instructions table 2.9-6 lists the interrupt/hold suppression instructions and prefix codes that have restrictions. table 2.9-6 prefix codes and interrupt/hold suppression instructions l interrupt/hold suppression as shown in figure 2.9-1, an interrupt or hold request generated during the execution of prefix codes and interrupt/hold instructions is not accepted. the interrupt/hold is not processed until the first instruction that is not governed by a prefix code or that is not an interrupt/hold suppression instruction is executed. figure 2.9-1 interrupt/hold suppression prefix codes interrupt/hold suppression instructions (instructions that delay the effect of prefix codes) instructions that do not accept interrupt and hold requests pcb dtb adb spb cmr ncc mov ilm, #imm8 or ccr, #imm8 and ccr, #imm8 popw ps interrupt/hold suppression instruction interrupt request generated interrupt accepted (a) ordinary instruction
MB90560 series chapter 2 cpu 65 l delay of the effect of prefix codes as shown in figure 2.9-2, if a prefix code is placed before an interrupt/hold suppression instruction, the prefix code takes effect with the first instruction executed after the interrupt/hold suppression instruction. figure 2.9-2 interrupt/hold suppression instructions and prefix codes n consecutive prefix codes as shown in figure 2.9-3, when consecutive conflicting prefix codes (pcb, adb, dtb, and spb) are specified, the last prefix code is valid. figure 2.9-3 consecutive prefix codes interrupt/hold suppression instruction ncc does not cause the ccr to change. prefix code prefix code pcb is valid.

chapter 3 resets this chapter describes resets for the MB90560-series microcontrollers. 3.1 resets .............................................................................................. 68 3.2 reset causes and oscillation stabilization wait intervals ............... 70 3.3 external reset pin............................................................................ 72 3.4 reset operation ............................................................................... 74 3.5 reset cause bits.............................................................................. 76 3.6 status of pins in a reset .................................................................. 78
68 chapter 3 resets MB90560 series 3.1 resets if a reset cause is generated, the cpu immediately stops the current execution process and waits for the release of the reset. when the reset is released, the cpu begins processing at the address indicated by the reset vector. there are four causes of a reset: ? power-on reset ? watchdog timer overflow ? external reset request via the rstx pin ? software reset request n reset causes table 3.1-1 lists the reset causes. table 3.1-1 reset causes mclk: main clock (oscillation clock divided by 2) l external reset an external reset is generated by the l level input to an external reset pin (rstx pin). the minimum required period of the l level input to the rstx pin is 16 machine cycles (16/ f ). the oscillation stabilization wait interval is not required for external resets. for external reset requests via the rstx pin, if the reset cause is generated during a write operation (during the execution of a transfer instruction such as mov), the cpu waits for the reset to be released after the instruction is completed. the normal write operation is therefore completed even though a reset is input concurrently. note, however, that waiting for the reset to be released may not start before the transfer of the contents of a counter specified by a string-processing instruction (such as movs) is completed. type of reset cause machine clock watchdog timer oscillation stabilization wait external pin l level input to rst pin previous state retained previous state retained no software a 0 is written to the rst bit of the low power consumption mode control register (lpmcr). previous state retained previous state retained no watchdog timer watchdog timer overflow mclk stop yes power-on when the power is turned on mclk stop yes
MB90560 series chapter 3 resets 69 l software reset a software reset is an internal reset of three machine cycles (3/ f ) generated by writing 0 to the rst bit of the low power mode control register (lpmcr). the oscillation stabilization wait interval is not required for software resets. l watchdog timer reset a watchdog timer reset is generated by a watchdog timer overflow that occurs when a 0 is not written to the wte bit of the watchdog timer control register (wdtc) within a given time after the watchdog timer is activated. the watch-dog reset will wait for oscillation stabilization watch interval. the oscillation stabilization wait interval can be set by the clock selection register (ckscr). l power-on reset a power-on reset is generated when the power is turned on. the oscillation stabilization wait interval is fixed at 2 17 oscillation clock cycles (2 17 /hclk). after the oscillation stabilization wait interval has elapsed, the reset is executed. see also ? definition of clocks hclk: oscillation clock mclk: main clock f : machine clock (cpu operating clock) 1/ f : machine cycle (cpu operating clock cycle) see chapter 4, "clocks," for details.
70 chapter 3 resets MB90560 series 3.2 reset causes and oscillation stabilization wait intervals the f 2 mc-16lx has five reset causes. the oscillation stabilization wait interval for a reset depends on the reset cause. n reset causes and oscillation stabilization wait intervals tables 3.2-1 and 3.2-2 summarize reset causes and oscillation stabilization wait intervals. table 3.2-1 reset causes and oscillation stabilization wait intervals hclk:oscillation clock frequency, source oscillation table 3.2-2 oscillation stabilization wait intervals set by the clock selection register (ckscr) hclk: oscillation clock frequency ceramic and crystal oscillators generally require an oscillation stabilization wait interval of several milliseconds to 10 to 20 milliseconds until they stabilize at their natural frequency. be sure to set a proper oscillation stabilization wait interval for the particular oscillator used. see chapter 4, "clocks," for details. n oscillation stabilization wait and reset state a reset operation in response to a power-on reset and other externally activated resets during stop mode is performed after the oscillation stabilization wait interval has elapsed. this time interval is generated by the timebase timer. if the external reset has not been released after the interval, the reset operation is performed after the external reset is released. reset cause oscillation stabilization wait interval the corresponding time interval for an oscillation clock frequency of 4 mhz is given in parentheses. power-on reset 2 17 /hclk (32.768 ms) watchdog timer 2 17 /hclk (32.768 ms) external reset via the rstx pin none software reset none ws1 ws0 oscillation stabilization wait interval the corresponding time interval for an oscillation clock frequency of 4 mhz is given in parentheses. 0 0 no oscillation stabilization time. 01 2 13 /hclk (2.048 ms) 10 2 15 /hclk (8.192 ms) 11 2 17 /hclk (32.768 ms)
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72 chapter 3 resets MB90560 series 3.3 external reset pin the external reset pin (rst pin) is a dedicated pin for inputting, with an l level signal, a reset and generating an internal reset by the l level input. in MB90560 series microcontrollers, there are internal cpu synchronous reset and external synchronous reset. n block diagrams of the external reset pin l block diagram of internal reset figure 3.3-1 block diagram of internal reset inputs to the rstx pin are accepted during cycles in which memory is not affected to prevent memory from being destroyed by a reset during a write operation. a clock is required to initialize the internal circuit. in particular, an operation with an external clock requires clock input together with reset input. rstx pch nch cpu operating clock (pll multiplier circuit with a frequency of hclk divided by 2) input buffer hclk: oscillation clock internal reset signal synchronization curcuit pin
MB90560 series chapter 3 resets 73 l block diagram of internal reset for external pin figure 3.3-2 block diagram of internal reset for external pin rstx pch nch input buffer hclk: oscillation clock internal reset signal pin
74 chapter 3 resets MB90560 series 3.4 reset operation when a reset is released, the memory locations from which the mode data and the reset vector are read are selected according to the setting of the mode pins, and the mode setting data is fetched. mode setting data determines the cpu operating mode and the execution start address after a reset operation ends. for power-on or recovery from stop mode by a reset, the mode is fetched after the oscillation stabilization wait time has elapsed. n overview of reset operation figure 3.4-1 shows the reset operation flow. figure 3.4-1 reset operation flow n mode pins setting the mode pins (md0 to md2) specifies how to fetch the reset vector and the mode data. fetching the reset vector and the mode data is performed in the reset sequence. see chapter 7, "setting a mode," for details about mode pins. during a reset power-on reset stop mode watchdog timer reset external reset software reset oscillation stabilization wait and reset state fetching the mode data fetching the reset vector cpu executes an instruction, fetching instruction codes from the address indicated by the reset vector. pin state and function change mode fetch (reset operation) normal operation (run state)
MB90560 series chapter 3 resets 75 n mode fetch when the reset is cleared, the cpu transfers the reset vector and the mode data stored in the hardware memory to the appropriate registers in the cpu core. the reset vector and mode data are allocated to the four bytes from ffffdc h to ffffdf h . the cpu outputs these addresses to the bus immediately after the reset is cleared and fetches the reset vector and mode data. using mode fetching, the cpu can begin processing at the address indicated by the reset vector. figure 3.4-2 shows the transfer of the reset vector and mode data. figure 3.4-2 transfer of reset vector and mode data l mode data (address: ffffdf h ) only s reset operation changes the contents of the mode register. the mode register setting is valid after a reset operation. see section 7.1, "setting a mode," for details about mode data. l reset vector (address: ffffdc h to ffffde h ) the execution start address after the reset operation ends is written as the reset vector. execution starts at the address contained in the reset vector. memory space mode data bits 23 to 16 of the reset vector bits 15 to 8 of the reset vector bits 7 to 0 of the reset vector f 2 mc-16l cpu core mode micro-rom reset sequence register
76 chapter 3 resets MB90560 series 3.5 reset cause bits a reset cause can be identified by checking the watchdog timer control register (wdtc). n reset cause bits as shown in figure 3.5-1, a flip-flop is associated with each reset cause. the contents of the flip- flops are obtained by reading the watchdog timer control register (wdtc). if it is necessary to identify the cause of a reset after the reset has been released, the value read from the wdtc should be processed by the software and a branch made to the appropriate program. figure 3.5-1 block diagram of reset cause bits power-on detection circuit delay circuit external reset request detection cirtuit watchdog timer reset generation detection cirtuit watchdog timer control register (wdtc) reading of watchdog timer control register (wdtc) lpmcr:rst bit write detection circuit rstx pin rstx=l power-on sr f/f q sr f/f q sr f/f q sr f/f q f 2 mc-16lx @ internal bus clear rst bit set no periodic clear s : set r : reset q : output f/f : flip flop
MB90560 series chapter 3 resets 77 n correspondence between reset cause bits and reset causes figure 3.5-2 shows the configuration of the reset cause bits of the watchdog timer control register (wdtc). table 3.5-1 maps the correspondence between the reset cause bits and reset causes. figure 3.5-2 configuration of reset cause bits (watchdog timer control register) table 3.5-1 correspondence between reset cause bits and reset causes *:previous state retained x:undefined n notes about reset cause bits l multiple reset causes generated at the same time when multiple reset causes are generated at the same time, the corresponding reset cause bits of the watchdog timer control register (wdtc) are set to 1. if, for example, an external reset request via the rstx pin and the watchdog timer overflow occur at the same time, both the erst bit and the wrst bit are set to 1. l power-on reset for a power-on reset, the ponr bit is set to 1, but all other reset cause bits are undefined. consequently, program the software so that it will ignore all reset cause bits except the ponr bit if it is 1. l clearing the reset cause bits the reset cause bits are cleared only when the watchdog timer control register (wdtc) is read. once a reset is occurred, the corresponding reset cause bit remains to 1, even though another reset cause is occurred. reset cause ponr wrst erst srst power-on reset 1 x x x watchdog timer overflow * 1 * * external reset request via rst pin * * 1 * software reset request * * * 1 ponr - wrst erst srst wte wt1 wt0 r-rrrwww r : read only w : write only x : undefined address initial value bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit8 (tbtc) watchdog timer control register (wdtc) 0000a8 h 1xxxxxxx b
78 chapter 3 resets MB90560 series 3.6 status of pins in a reset this section describes the status of pins when a reset occurs. n status of pins during a reset the status of pins during a reset depends on the settings of mode pins (md2 to md0 = "011"). l when internal vector mode has been set: all i/o pins (resource pins) are high impedance, and mode data is read from the internal rom. n status of pins after mode data is read the status of pins after mode data has been read depends on the mode data (m1 and m0 = 00). l when single-chip mode has been selected (m1, m0 = 00 b ): all i/o pins (resource pins) are high impedance, and mode data is read from the internal rom. for those pins that change to high impedance when a reset cause is generated, take care that devices connected to them do not malfunction. see appendix, "state of pins for the MB90560 series," for information about the state of pins during a reset.
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chapter 4 clocks this chapter describes the clocks used by MB90560 series microcontrollers. 4.1 clocks............................................................................................... 82 4.2 block diagram of the clock generator............................................. 84 4.3 clock selection register (ckscr) .................................................. 86 4.4 clock mode ...................................................................................... 88 4.5 oscillation stabilization wait interval ............................................... 90 4.6 connection of an oscillator or an external clock............................. 91
82 chapter 4 clocks mb90620 series 4.1 clocks the clock generator controls the operation of the internal clock for the cpu and peripheral functions. this internal clock is called the machine clock. one internal clock cycle is regarded as one machine cycle. other clocks include a clock generated by source oscillation, called an oscillation clock, and a clock generated by the internal pll oscillation, called a pll clock. n clocks the clock generator block contains the oscillation circuit that generates the oscillation clock. an external oscillator is connected to this circuit. the oscillation clock can also be supplied by inputting an external clock to the clock generator. the clock generator also contains the pll clock multiplier circuit, which generates four types of clock, that are multiples of the oscillation clock. the clock generator controls the oscillation stabilization wait interval and pll clock multiplication as well as controls internal clock operation by changing the clock with a clock selector. l oscillation clock (hclk) the oscillation clock is generated either from an external oscillator connected to the oscillation circuit or by input of an external clock. l main clock (mclk) the main clock, which is the oscillation clock divided by 2, supplies the clock input to the timebase timer and the clock selector. l pll clock (pclk) the pll clock is obtained by multiplying the oscillation clock with the internal pll clock multiplier circuit (pll oscillation circuit). selection can be made from among four different pll clocks. l machine clock ( f ) the machine clock controls operation of the operation of the cpu and peripheral functions. one clock cycle is regarded as one machine cycle (1/ f ). an operating machine clock can be selected from among the main clock that is generated from the oscillation clock divided by 2 and the four types of clock, that are multiples of the source clock frequency. although an oscillation clock of 3 mhz to 32 mhz can be generated when the operating voltage is 5 v, the maximum operating frequency for the cpu and peripheral functions is 16 mhz. if a frequency multiplier rate exceeding the operating frequency is specified, devices will not operate correctly. if, for example, a source oscillation of 16 mhz is generated, only a multiplier of 1 can be specified. a pll oscillation of 3 to 16 mhz is possible, but this range depends on the operating voltage and multiplier. see "data sheet," for details.
mb90620 series chapter 4 clocks 83 n clock supply map since the machine clock generated by the clock generator is supplied as the operating clock for the cpu and peripheral functions, the operation of the cpu and peripheral functions is affected by switching of the main clock and the pll clock (clock mode) and a change in the pll clock multiplier. since the timebase timer output will supply the operating clock for some peripheral functions, a peripheral function can select the clock best suited for its operation. figure 4.1-1 shows the clock supply map. figure 4.1-1 clock supply map a/d converter watchdog timer peripheral function x0 x1 hclk mclk pclk 3 3 3 3 tin0 1234 to0 uart0 pll multipiler circuit clock selecter clock generator divide-by-2 uart1 cpu machine clock sck0 sck1 to1 i2c interface pin pin pin pin pin pin pin pin pin pin ppg0/2/4 ppg1/3/5 tin1 4 8/16-bit ppg timer 0/2/4 8/16-bit ppg timer 1/3/5 16-bit reload timer 0 system clock generation circuit timebase timer 16-bit reload timer 1 output compare unit input capture unit oscillation stabilization wait control 16-bit free-run timer hclk: oscillation clock mclk: main clock pclk: pll clock f :
84 chapter 4 clocks mb90620 series 4.2 block diagram of the clock generator the clock generator consists of five blocks: ? system clock generation circuit ? pll multiplier circuit ? clock selector ? clock selection register (ckscr) ? oscillation stabilization wait interval selector n block diagram of the clock generator figure 4.2-1 shows a block diagram of the clock generator and also includes the standby control circuit and timebase timer circuit. figure 4.2-1 block diagram of the clock generator ws1 mcm ws0 resv mcs cs1 cs0 resv spl slp rst resv cg1 cg0 resv stp sq r sq r sq r x0 x1 2 2 2 s: set r: reset q: output divide- by-2 divide- by-2048 divide- by-4 divide- by-4 divide- by-4 pin pin standby control circuit cpu clock control circuit peripheral clock control circuit pll multipiller circuit timebase timer to watchdog timer stop signal stop and sleep signals reset interrupt system clock generation circuit cpu operating clock machine clock peripheral function operating clock oscillation stabilization wait interval selector oscillation clock main clock clock selector low power mode control register (lpmcr) clock selection register (ckscr) cpu intermittent operation cycles selecter
mb90620 series chapter 4 clocks 85 l system clock generation circuit the system clock generation circuit generates an oscillation clock (hclk) from an external oscillator connected to it. alternatively, an external clock can be input to this circuit. l pll multiplier circuit the pll multiplier circuit multiplies the oscillation clock through pll oscillation and supplies this multiplied clock to the cpu clock selector. l clock selector from among the main clock and four different pll clocks, the clock selector selects the clock that is supplied to the cpu and peripheral clock control circuits. l clock selection register (ckscr) the clock selection register is used to set switching between the oscillation clock and a pll clock to select an oscillation stabilization wait interval, and to select a pll clock multiplier. l oscillation stabilization wait interval selector this selector selects an oscillation stabilization wait interval for the oscillation clock when returning from stop mode or after a watchdog timer reset. selection is made from among three kinds of timebase timer output. in all other cases, an oscillation stabilization wait interval is not selected.
86 chapter 4 clocks mb90620 series 4.3 clock selection register (ckscr) the clock selection register (ckscr) is used to switch between the main clock and a pll clock, to select an oscillation stabilization wait interval, and to select a pll clock multiplier. n configuration of the clock selection register (ckscr) figure 4.3-1 shows the configuration of the clock selection register (ckscr); table 4.3-1 describes the function of each bit of the clock selection register (ckscr). figure 4.3-1 configuration of the clock selection register (ckscr) if the machine clock selection bit is not set, the main clock is used as the machine clock. mcm 0 1 mcs 0 1 resv ws1 ws0 0 0 1 1 0 1 0 1 cs1 17 15 13 cs0 multiplier selection bits the resulting clock frequency is shown in parenthness oscillation stabilization wait interval selection bits the corresponding time interval for an oscillation clock frequency of 4 mhz is given in parentheses. machine clock selection bit 0 0 1 1 0 1 0 1 1 x hclk (4mhz) 2 x hclk (8mhz) 3 x hclk (12mhz) 4 x hclk (16mhz) no oscillation stabilization wait interval 2 / hclk (aprox. 2.05ms) 2 / hclk (aprox. 8.19ms) 2 / hclk (aprox. 32.768ms) pll clock selected. main clock selected. machine clock indication bit a pll clock is used as the machine clock. the main clock is usedas the machine clock. reserved bit 1 must always be written to these bits. hclk: oscillation clock frequency r/w: read/write r: read only - : unused : initial value ws0 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 (lpmsr) resv cs1 cs0 mcs resv mcm ws1 r/w address initial value r/w r/w r/w r r/w r/w r/w 0000a1 h 11111100 b
mb90620 series chapter 4 clocks 87 table 4.3-1 function description of each bit of the clock selection register (ckscr) hclk: oscillation clock frequency bit name function bit 15 bit 11 resv: reserved bit 1 must always be written to these bits. bit 14 mcm: machine clock indication bit this bit indicates whether the main clock or a pll clock has been selected as the machine clock. when this bit is set to 0, a pll clock has been selected. when it is set to 1, the main clock has been selected. if mcs = 0 and mcm = 1, the pll clock oscillation stabilization wait period is in effect. bit 13 bit 12 ws1, ws0: oscillation stabili- zation wait inter- val selection bits these bits select an oscillation stabilization wait interval of the oscillation clock after stop mode has been cancelled. these bits are initialized to 11 b by all reset causes. the oscillation stabilization wait interval must be set to a value appropriate for the oscillator used. see section 3.2, "reset causes and oscillation stabilization wait intervals," in chapter 3. the oscillation stabilization period for all pll clocks is fixed at 2 13 /hclk. bit 10 mcs: machine clock selection bit this bit specifies whether the main clock or a pll clock is selected as the machine clock. when this bit is 0, a pll clock is selected. when this bit is 1, the main clock is selected. 0 is written to this bit while it is 1, the oscillation stabilization wait inter- val for the pll clock starts. as a result, the timebase timer is automatically cleared, and the tbof bit of the timebase timer control register (tbtc) is also cleared. for pll clocks, the oscillation stabilization period is fixed at 2 13 /hclk (the oscillation stabilization wait interval is approx. 2 ms for an oscillation clock frequency of 4 mhz). when the main clock has been selected, the operating clock frequency is the frequency of the oscillation clock divided by 2 (e.g., the operating clock is 2 mhz when the oscillation clock frequency is 4 mhz). this bit is initialized to 1 by all reset causes. when the mcs bit is 1, write 0 to it only when the timebase timer inter- rupt is masked by the tbie bit of the timebase timer control register (tbtc) or the interrupt level register (ilm). for 8 machine cycles after 1 is written to the mcs bit, writing 0 to it may be disabled. write to the bit after 8 machine cycles have passed. bit 9 bit 8 cs1, cs0: multiplier selec- tion bits these bits select a pll clock multiplier. selection can be made from among four different multipliers. these bits are initialized to 00 b by all reset causes. when the mcs bit is 0, writing to these bits is not allowed. write to the cs1 and cs0 bits only after setting the mcs bit to 1 (main clock mode).
88 chapter 4 clocks mb90620 series 4.4 clock mode two clock modes are provided: main clock mode and pll clock mode. n main clock mode and pll clock mode l main clock mode in main clock mode, the main clock, which is the oscillation clock divided by 2 and is used as the operating clock for the cpu and peripheral resources. meanwhile, the pll clocks are disabled. l pll clock mode in pll clock mode, a pll clock is used as the operating clock for the cpu and peripheral resources. a pll clock multiplier is selected with the clock selection register (ckscr: cs1 and cs0). n clock mode transition switching between main clock mode and pll clock mode is done by writing to the mcs bit of the clock selection register (ckscr). l switching from main clock mode to pll clock mode when the mcs bit of ckscr is 1, writing 0 to it will switch the operating clock from the main clock to a pll clock after the pll clock oscillation stabilization wait period (2 13 /hclk). l switching from pll clock mode to main clock mode when the mcs bit of ckscr is 0, writing 1 to it will switch the operating clock from the pll clock to the main clock when the edges of the pll clock and the main clock coincide (after 1 to 8 pll clocks). even though the mcs bit of ckscr is rewritten, machine clock switching does not occur immediately. when operating a peripheral function that depends on the machine clock, make sure that machine clock switching has been done by referring to the mcm bit of ckscr before operating the peripheral function. n selection of a pll clock multiplier writing a value from 00 b to 11 b to the cs1 and cs0 bits of ckscr selects one to the four pll clock multipliers. n machine clock the machine clock may be either a pll clock output from the pll multiplier circuit or the clock that is the source oscillation clock divided by 2. this machine clock is supplied to the cpu and peripheral functions. either the main clock or a pll clock can be selected by writing to the mcs bit of ckscr.
mb90620 series chapter 4 clocks 89 figure 4.4-1 shows the status change caused by the machine clock switching. figure 4.4-1 status change diagram for machine clock selection the initial value for the machine clock setting is main clock (mcs of ckscr = 1) power-on main mcs = 1 mcm = 1 cs1, cs0 = xx main pllx mcs = 0 mcm = 1 cs1, cs0 = xx pll1 main mcs = 1 mcm = 1 cs1, cs0 = 00 pll1: multiplied by 1 mcs = 0 mcm = 0 cs1, cs0 = 00 pll2: multiplied by 2 mcs = 0 mcm = 0 cs1, cs0 = 01 pll3: multiplied by 3 mcs = 0 mcm = 0 cs1, cs0 = 10 pll4: multiplied by 4 mcs = 0 mcm = 0 cs1, cs0 = 11 pll2 main mcs = 1 mcm = 0 cs1, cs0 = 01 pll3 main mcs = 1 mcm = 0 cs1, cs0 = 11 pll4 main mcs = 1 mcm = 0 cs1, cs0 = 11 (1) (2) (3) (4) (5) (6) (7) (7) (7) (7) (6) (6) (6) (6) machine clock selection bit of ckscr machine clock indication bit of ckscr multiplier selection bits of ckscr (1) the mcs bit is cleared. (2) the pll clock oscillation stabilization wait ends with cs1 and cs0 = 00. (3) the pll clock oscillation stabilization wait ends with cs1 and cs0 = 01. (4) the pll clock oscillation stabilization wait ends with cs1 and cs0 = 10. (5) the pll clock oscillation stabilization wait ends with cs1 and cs0 = 11. (6) the mcs bit is set (including also watchdog timer resets). (7) pll clock and main clock synchronization timing mcs: mcm: cs1, cs0:
90 chapter 4 clocks mb90620 series 4.5 oscillation stabilization wait interval when the system changes operation from a state in which the main clock is stopped (such as at power-on, in stop mode and at watch-dog reset), a delay (an oscillation stabilization wait interval) is required to stabilize the clock oscillation before operation starts. when the switch from the main clock to a pll clock occurs, an oscillation stabilization wait interval is also required when pll oscillation starts. n oscillation stabilization wait interval ceramic and crystal oscillators generally take several milliseconds to 20 milliseconds to stabilize at their natural frequency when oscillation starts. for this reason, cpu operation is not allowed as soon as oscillation starts and is allowed only after full stabilization of oscillation. after the oscillation stabilization wait interval has elapsed, the clock is supplied to the cpu. because the oscillation stabilization time depends on the type of the oscillator (crystal, ceramic, etc.), the proper oscillation stabilization wait interval for the oscillator used must be selected. an oscillation stabilization wait interval is selected by setting the clock selection register (ckscr). in a switch from the main clock to a pll clock, the cpu continues to operate on the main clock during the oscillation stabilization wait interval for pll. after this interval, the operating clock switches to the pll clock. figure 4.5-1 shows the operation after oscillation starts. figure 4.5-1 operation when oscillation starts oscillator-activated oscillation stabilization normal operation start start of oscillation stable oscillation oscillation time wait interval or change to pll clock
mb90620 series chapter 4 clocks 91 4.6 connection of an oscillator or an external clock the f 2 mc-16lx microcontroller contains a system clock generation circuit. connecting an external oscillator to this circuit generates the system clock. alternatively, an externally generated clock can be input to the microcontroller. n connection of an oscillator or an external clock to the microcontroller l example of connecting a crystal or ceramic oscillator to the microcontroller connect a crystal or ceramic oscillator as shown in the example in figure 4.6-1. figure 4.6-1 example of connecting a crystal or ceramic oscillator to the microcontroller l example of connecting an external clock to the microcontroller as shown in figure 4.6-2, connect an external clock to pin x0. pin x1 must be open. figure 4.6-2 example of connecting an external clock to the microcontroller x0 MB90560 x1 x0 MB90560 ~ open

chapter 5 low power consumption mode this chapter describes the low power consumption mode of MB90560 series microcontrollers. 5.1 low power consumption mode ....................................................... 94 5.2 block diagram of the low power consumption control circuit ....... 96 5.3 low power mode control register (lpmcr)................................... 98 5.4 cpu intermittent operation mode .................................................. 102 5.5 standby mode ................................................................................ 103 5.6 status change diagram ................................................................. 112 5.7 status of pins in standby mode and reset.................................... 115 5.8 notes on using low power consumption mode............................ 116
94 chapter 5 low power consumption mode MB90560 series 5.1 low power consumption mode f 2 mc-16lx microcontrollers have the following cpu operating modes, any of which can be used depending on the operating clock selection and clock operation control: ? clock mode (pll clock mode and main clock mode) ? cpu intermittent operation mode (pll clock intermittent operation mode and main clock intermittent operation mode) ? standby mode (sleep, timebase timer and stop) all modes other than pll clock mode are low power consumption modes. n cpu operating modes and current consumption figure 5.1-1 shows the relation between the cpu operating modes and current consumption figure 5.1-1 cpu operating modes and current consumption current consumption several tens cpu operating of ma mode pll clock mode multiplied-by-four clock multiplied-by-three clock multiplied-by-two clock multiplied-by-1 clock multiplied-by-four clock multiplied-by-three clock multiplied-by-two clock multiplied-by-1 clock pll clock intermittent operation mode main clock mode (1/2 clock mode) main clock intermittent operation mode standby mode sleep mode timebase timer mode stop mode/hardware standby mode several ma several a low power consumption mode note: this figure is only an indication of power consumption for each mode. actual current consumption values may not agree with those in the figure.
MB90560 series chapter 5 low power consumption mode 95 n clock mode l pll clock mode a pll clock that is a multiple of the oscillation clock (hclk) frequency is used to operate the cpu and peripheral functions. l main clock mode the main clock, with a frequency one-half that of the oscillation clock (hclk), is used to operate the cpu and peripheral functions. in main clock mode, the pll multiplier circuit is inactive. see chapter 4, "clocks," for details about clock mode. n cpu intermittent operation mode cpu intermittent operation mode causes the cpu to operate intermittently, while high-speed clock pulses are supplied to peripheral functions, reducing power consumption. in cpu intermittent operation mode, intermittent clock pulses are only applied to the cpu when it is accessing a register, internal memory, a peripheral function, or an external unit. n standby mode in standby mode, the low power consumption control circuit stops supplying the clock to the cpu (sleep mode) or the cpu and peripheral functions (timebase timer mode), or stops the oscillation clock itself (stop mode), reducing power consumption. l pll sleep mode pll sleep mode is activated to stop the cpu operating clock when the microcontroller enters pll clock mode; other components continue to operate on the pll clock. l main sleep mode main sleep mode is activated to stop the cpu operating clock when the microcontroller enters main clock mode; other components continue to operate on the main clock. l timebase timer mode timebase timer mode causes microcontroller operation, with the exception of the oscillation clock and the timebase timer, to stop. all functions other than the timebase timer are deactivated. l stop mode stop mode causes the source oscillation to stop. all functions are deactivated. because stop mode turns the oscillation clock off, this mode saves the most power while data is being retained.
96 chapter 5 low power consumption mode MB90560 series 5.2 block diagram of the low power consumption control circuit the low power consumption control circuit consists of the following seven blocks: ? cpu intermittent operation selector ? standby clock control circuit ? cpu clock control circuit ? peripheral clock control circuit ? pin high-impedance control circuit ? internal reset generation circuit ? low power mode control register (lpmcr) n block diagram of the low power consumption control circuit figure 5.2-1 shows the block diagram of the low power consumption control circuit. figure 5.2-1 block diagram of the low power consumption control circuit x0 2 x1 rst rst stp rst slp cg1 cg0 resv spl resv resv ws0 mcm mcs cs1 cs0 ws1 resv 2 2 low power mode control register (lpmcr) pin pin pin divide- by-2 divide- by-2048 divide- by-4 divide- by-4 divide- by-8 pll multipiller circuit system clock generation circuit timebase timer stop signal release reset cancel interrupt cpu clock pin hi-z control clock selector clock selection register (ckscr) stop and sleep signals machine clock main clock oscillation stabilization wait interval selector oscillation stabiliz- -ation wait is passed cpu clock control circuit pin high impedance control circuit internal reset generation circuit internal reset peripheral clock control circuit cpu intermittent operation selecter select intermittent cycles standby control circuit peripheral clock clock generator
MB90560 series chapter 5 low power consumption mode 97 l cpu intermittent operation selector this selector selects the number of clock pulses the cpu is to be halted during cpu intermittent operation mode. l standby control circuit the standby control circuit controls the cpu clock control circuit and the peripheral clock control circuit, and turns the low power consumption mode on and off. l cpu clock control circuit this circuit controls the clocks supplied to the cpu. l peripheral clock control circuit this circuit controls the clocks supplied to peripheral functions. l pin high-impedance control circuit this circuit makes the external pins high-impedance when the microcontroller enters timebase timer mode and stop mode. for the pins with the pull-up option, this circuit disconnects the pull-up resistor when the microcontroller enters stop mode or hardware standby mode. l internal reset generation circuit this circuit generates an internal reset signal. l low power consumption mode control register (lpmcr) this register is used to switch to and return from standby mode and to set the cpu intermittent operation function.
98 chapter 5 low power consumption mode MB90560 series 5.3 low power mode control register (lpmcr) the low power mode control register (lpmcr) switches to or releases low power consumption mode. it is also used to set the number of cpu clock pulses the cpu is to be halted during cpu intermittent mode. n low power consumption mode control register (lpmcr) figure 5.3-1 shows the configuration of the low power consumption mode control register (lpmcr). figure 5.3-1 configuration of the low power consumption mode control register (lpmcr) address 0000a0 h initial value 00011001 b (ckscr) stp slp resv spl rst resv cg1 cg0 cg1 0 0 0 clock pulse (cpu clock = peripheral clock) 9 clock pulses (cpu clock: peripheral clock = 1: 3 to 4 approx.) 17 clock pulses (cpu clock: peripheral clock = 1: 5 to 6 approx.) 33 clock pulses (cpu clock: peripheral clock = 1: 9 to 10 approx.) 01 10 11 cg0 cpu halt clock pulses selection bits rst 0 generates an internal reset signal of 3 machine cycles. no change, no effect on operation 1 internal reset signal generation bit spl 0 retained high-impedance 1 pin state setting bit (for timebase timer mode and stop mode) slp 0 no change, no effect on operation switch to sleep mode. 1 sleep bit stp 0 no change, no effect on operation no change, no effect on operation switch to stop mode. switch to timebase timer mode. 1 stop bit pll clock mode (mcs of ckscr = 0) main clock mode (mcs of ckscr = 1) resv 1 must always be written to these bits. reserved bit bit15 w w r/w w r/w r/w r/w r/w bit8 bit7 bit6 bit5 bit4 bit2 bit1 bit0 r/w: read/write w: write-only : initial value
MB90560 series chapter 5 low power consumption mode 99 table 5.3-1 function description of each bit of the low power consumption mode control register (lpmcr) bit name function bit 7 stp: stop bit this bit indicates switching to timebase timer mode or stop mode. when 1 is written to this bit, a switch to timebase timer mode is performed if the pll clock has been selected (mcs of ckscr = 0) and a switch to stop mode is performed if the oscillation clock has been selected (mcs of ckscr = 1). even though 1 is writ- ten to the stp bit during the transition of clock selection, the mcs bit status determines whether timebase timer mode or stop mode is used. writing 0 to this bit has no effect on operation. this bit is cleared to 0 by a reset or by release of the timebase timer or of the stop state. the read value of this bit is always 0. bit 6 slp: sleep bit this bit indicates switching to sleep mode. when 1 is written to this bit, the mode switches to sleep mode. writing 0 to this bit has no effect on operation. this bit is cleared to 0 by a reset or by release of sleep or stop mode. if 1 is written to both the stp bit and slp bit at the same time, the mode switches to timebase timer mode or stop mode. the read value of this bit is always 0. bit 5 spl: pin state setting bit (for timebase timer mode and stop mode) this bit is enabled while either timebase timer mode or stop mode is in effect. when this bit is 0, the level of the external pins is retained. when this bit is 1, the status of the external pins changes to high-impedance. this bit is initialized to 0 by a reset. bit 4 rst: internal reset signal gen- eration bit when 0 is written to this bit, an internal reset signal of 3 machine cycles is generated. writing 1 to this bit has no effect on operation. the read value of this bit is always 1. bit 3 resv: reserved bit 1 must always be written to this bit. bit 2 bit 1 cg1, cg0: cpu halt clock pulses selection bits these bits set the number of cpu halt clock pulses for the cpu intermittent operation function. the clock supplied to the cpu is stopped after the execution of every instruction for the specified number of clock pulses. selection can be made from among four different clock pulses. these bits are initialized to 00 b by a power-on or watchdog timer reset. other resets do not initialize these bits. bit 0 resv: reserved bit 1 must always be written to this bit.
100 chapter 5 low power consumption mode MB90560 series n access to the low power mode control register (lpmcr) switching to low power consumption mode (including stop mode and sleep mode) is performed by writing to the low power mode control register (lpmcr). only the instructions listed in table 5.3-2 should be used for this purpose. if other instructions are used for switching to low power consumption mode, operation cannot be assured. to control functions other than switching to low power consumption mode, any instruction can be used. when word-length is used for writing to the low power consumption mode control register, even addresses must be used. writing with odd addresses to switch to low power consumption mode may cause a malfunction. table 5.3-2 instructions to be used for switching to low power consumption mode mov io,#imm8 mov io,a mov @rli+disp8,a movw io,#imm16 movw io,a movw @rli+disp8,a mov dir,#imm8 mov dir,a mov addr24,a movw dir,#imm16 movw dir,a movpw addr24,a mov eam,#imm8 mov addr,a movw eam,#imm16 movw addr16,a mov eam,ri mov eam,a movw eam,rwi movw eam,aa setb io:bp setb dir:bp setb addr16:bp
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102 chapter 5 low power consumption mode MB90560 series 5.4 cpu intermittent operation mode cpu intermittent operation mode is used for intermittent operation of the cpu while peripheral functions continue to operate at high speed. its purpose is to reduce power consumption. n cpu intermittent operation mode cpu intermittent operation mode halts the supply of the clock to the cpu for a certain period. the halt occurs after the execution of every instruction that accesses a register, internal memory (rom and ram), i/o, peripheral functions. and the external bus. internal bus cycle activation is therefore delayed. while a steady rate of peripheral clock pulses are supplied to the peripheral functions, the rate of cpu execution is reduced, enabling processing with low power consumption. ? the cg1 and cg0 bits of the low power mode control register (lpmcr) are used to select the number of clock pulses per halt cycle of the clock supplied to the cpu. ? instruction execution time in cpu intermittent mode can be calculated. a correction value should be obtained by multiplying the number of times instructions that access a register, internal memory and internal peripheral functions are executed by the number of clock pulses per halt cycle. add this correction value to the normal execution time. figure 5.4-1 shows the operating clock pulses during cpu intermittent operation mode. figure 5.4-1 clock pulses during cpu intermittent operation peripheral clock cpu clock halt cycle one instruction internal bus activation execution cycle
MB90560 series chapter 5 low power consumption mode 103 5.5 standby mode standby mode includes the sleep (pll sleep and main sleep), timebase timer, and stop modes. n operating status during standby mode table 5.5-1 summarizes the operating statuses during standby mode. table 5.5-1 operation statuses during standby mode *1 only the timebase timer is active. spl:pin state setting bit of low power consumption mode control register (lpmcr) slp:sleep bit of lpmcr stp:timebase timer or stop bit of lpmcr mcs:machine clock selection bit of clock selection register (ckscr) hi-z:high-impedance standby mode condition for switch oscil- lation clock cpu peripheral pin release event sleep mode pll sleep mode mcs = 0 slp = 1 active active stop active active reset interrupt main sleep mode mcs = 0 slp = 1 time- base timer mode timebase timer mode (spl = 0) mcs = 0 stp = 1 in- active stop (*1) hold timebase timer mode (spl = 1) mcs = 0 stp = 1 hi-z stop mode stop mode (spl = 0) mcs = 1 stp = 1 stop stop hold stop mode (spl = 1) mcs = 1 stp = 1 hi-z
104 chapter 5 low power consumption mode MB90560 series 5.5 standby mode 5.5.1 sleep mode sleep mode causes the cpu operating clock to stop while other peripheral functions continue to operate. when the low power mode control register (lpmcr) indicates a switch to sleep mode, a switch to pll sleep mode occurs if pll clock mode has been set. alternatively, a switch to main sleep mode occurs if main clock mode has been set. n switching to sleep mode writing 1 to the slp bit of lpmcr and 0 to the stp bit of lpmcr triggers a switch to sleep mode. at this time, if the mcs bit of the clock selection register (ckscr) is 0, the microcontroller enters pll sleep mode. if the mcs bit of ckscr is 1, the microcontroller enters main sleep mode. since the stp bit setting overrides the slp bit setting when 1 is written to the slp and stp bits at the same time, the mode switches to timebase timer mode or stop mode. l data retention function in sleep mode, the contents of dedicated registers, such as accumulators and internal ram, are retained. l operation during an interrupt request writing 1 to the slp bit of lpmcr during an interrupt request does not switch to sleep mode. if the cpu does not accept the interrupt, the cpu executes the next instruction. if the cpu accepts the interrupt, cpu operation immediately branches to the interrupt processing routine. l status of pins during sleep mode, all pins retain the state they had immediately before the switch to sleep mode. n release of sleep mode the low power consumption control circuit is used to release sleep mode. releasing is caused by the input of a reset or by an interrupt. l return to normal mode by a reset when sleep mode is released by a reset, the microcontroller is placed in the reset state on release from sleep mode.
MB90560 series chapter 5 low power consumption mode 105 l return to normal mode by an interrupt if an interrupt request of level 7 or higher is issued from a peripheral circuit during sleep mode, sleep mode is released. after release, the cpu handles the interrupt in normal manner. the cpu executes processing according to the settings of the i flag of the condition code register (ccr), interrupt level mask register (ilm), and interrupt control register (icr). if that interrupt is accepted, the cpu executes interrupt processing. if the interrupt is not accepted, the cpu resumes execution with the instruction that follows the instruction in which switching to sleep mode was specified. figure 5.5-1 shows the release of sleep mode for an interrupt. figure 5.5-1 release of sleep mode for an interrupt when interrupt processing is executed normally, the cpu first executes the instruction that follows the instruction in which switching to sleep mode was specified. the cpu then proceeds to interrupt processing. l return to normal mode from pll sleep mode by an external reset during pll sleep mode, the main clock and the pll clock generate clock pulses. since an external reset does not initialize the mcs bit in the clock selection register (ckscr) to 1, pll clock mode remains selected (mcs of ckscr = 0). on return from pll sleep mode by an external reset, the cpu starts operation using the pll clock immediately after pll sleep mode is released as shown in figure 5.5-2. interrupt from a peripheral circuit enable flag is set. int occurs (il smaller than 7) interrupt execution sleep mode is not execution of the sleep mode is next instruction execution of the next instruction released. sleep mode is not released. released.
106 chapter 5 low power consumption mode MB90560 series figure 5.5-2 release of pll sleep mode (by external reset) rst pin sleep mode main clock pll clock cpu clock cpu operation sleep mode released. inactive oscillating pll clock reset sequence execution reset released. oscillating
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108 chapter 5 low power consumption mode MB90560 series 5.5 standby mode 5.5.2 timebase timer mode timebase timer mode causes the microcontroller operation to stop except the source oscillation and the timebase timer. all functions other than timebase timer are deactivated. n switching to timebase timer mode when 1 is written to the stp bit of the low power consumption mode control register (lpmcr) in pll clock mode (mcs of ckscr = 0), switching to timebase timer mode occurs. also, in main clock mode (mcs of ckscr = 1), writing 0 to the mcs bit of the clock selection register (ckscr) and 1 to the stp bit of lpmcr triggers switching to timebase timer mode. l data retention function in timebase timer mode, the contents of dedicated registers, such as accumulators and internal ram, are retained. l operation during an interrupt writing 1 to the stp bit of lpmcr during an interrupt request does not trigger switching to timebase timer mode. l status of pins before switching to timebase timer mode, the spl bit of lpmcr controls external i/o pins to either retain the pervious state or go to high-impedance. n release of timebase timer mode the low power consumption control circuit is used to release timebase timer mode. release is caused by input of a reset or an interrupt. if timebase timer mode is released by a reset, the microcontroller is placed in the reset state after its release from timebase timer mode. for return to normal mode from timebase timer mode, the low power consumption control circuit releases timebase timer mode. the microcontroller then enters the pll clock oscillation stabilization wait state. if the pll clock is not used, change the mcs bit of ckscr to 1 with the instruction that is executed immediately after the reset or return from the interrupt. l return to normal mode by a reset if timebase timer mode is released by a reset, the microcontroller is placed in the reset state after release from timebase timer mode. l return to normal mode by an external reset since an external reset does not initialize the mcs bit of the clock selection register (ckscr) to 1, pll clock mode remains selected (mcs of ckscr = 0). if the reset period is shorter than the pll clock oscillation stabilization wait period, the reset sequence proceeds using the main clock. figure 5.5-3 shows the operation for return to normal mode from timebase timer mode triggered by an external reset.
MB90560 series chapter 5 low power consumption mode 109 figure 5.5-3 release of timebase timer mode (by an external reset) l return to normal mode by an interrupt if an interrupt request of level 7 or higher is issued from a peripheral circuit in timebase timer mode (when il2, il1, and il0 of the interrupt control register (icr) are set to a value other than 111 b ), the low power consumption control circuit releases timebase timer mode. after the release, the cpu handles the interrupt in a normal manner. the cpu executes processing according to the settings of the i flag of the condition code register (ccr), interrupt level mask register (ilm), and interrupt control register (icr). if the interrupt is accepted, the cpu executes interrupt processing. if the interrupt is not accepted, the cpu resumes execution with the instruction that follows the instruction in which switching to timebase timer mode was specified. when interrupt processing is executed normally, the cpu first executes the instruction that follows the instruction in which switching to timebase timer mode was specified. the cpu then proceeds to interrupt processing. l pll clock oscillation stabilization wait interval on release of timebase timer mode the period from the falling edge to the rising edge of the timebase timer output (2 13 x oscillation clock cycle) is allowed for the detection of the end of the pll clock oscillation wait interval. when timebase timer mode is released by an external reset or an interrupt, the timebase timer itself is not cleared. consequently, a delay of a maximum of one cycle (2 x 2 13 x oscillation clock cycle) occurs until the falling edge of the timer output has actually been detected after timebase timer mode is released. therefore, a certain amount of time (2 13 x oscillation clock cycle to 3 x 2 13 x oscillation clock cycle) is required before pll clock operation begins after the release of timebase timer mode. the cpu and peripheral functions operate using the main clock until the switch to the pll clock. rst pin timebase main clock pll clock cpu clock cpu operation inactive oscillating oscillation stabilization wait reset sequence timer mode oscillating main clock pll clock execution reset released. timebase timer mode released
110 chapter 5 low power consumption mode MB90560 series 5.5 standby mode 5.5.3 stop mode stop mode causes the source oscillation to stop and deactivates all functions. it is therefore the most power saving mode while data is being retained. n switching to stop mode when 1 is written to the stp bit of the low power consumption mode control register (lpmcr) is written in main clock mode (mcs of ckscr = 1), switching to stop mode occurs. during pll clock mode (mcs of ckscr = 0), writing 1 to the mcs bit of the clock selection register (ckscr) and writing 1 to the stp bit of lpmcr trigger switching to stop mode. l data retention function in stop mode, the contents of dedicated registers, such as accumulators and internal ram, are retained. l operation during an interrupt writing 1 to the stp bit of lpmcr during an interrupt request does not trigger switching to stop mode. l pin state setting before switching to stop mode, the spl bit of lpmcr controls the external pins to either retain the pervious state or go to high-impedance.
MB90560 series chapter 5 low power consumption mode 111 n release of stop mode the low power consumption control circuit is used release stop mode. the release is caused by input of a reset or by an interrupt. because the oscillation of the operating clock is stopped before return to normal mode from stop mode, the low power consumption control circuit puts the microcontroller into the oscillation stabilization wait state, then releases stop mode. l return to normal mode by a reset when stop mode is released by a reset cause, the microcontroller is placed in the oscillation stabilization wait and reset state after release from stop mode. the reset sequence proceeds after the oscillation stabilization wait interval has elapsed. l return to normal mode by a interrupt if an interrupt request of level 7 or higher is issued from a peripheral circuit during stop mode (when il2, il1, and il0 of the interrupt control register (icr) are set to a value other than 111 b ), the low power consumption control circuit releases stop mode. after release, the cpu handles the interrupt in a normal manner. however, the cpu starts after the main clock oscillation stabilization wait interval specified by the ws1 and ws0 bits of the clock selection register (ckscr) has elapsed. the cpu executes processing according to the settings of the i flag of the condition code register (ccr), interrupt level mask register (ilm), and interrupt control register (icr). if the interrupt is accepted, the cpu executes interrupt processing. if the interrupt is not accepted, the cpu resumes the execution with the instruction that follows the instruction in which switching to stop mode was specified. when interrupt processing is executed normally, the cpu first executes the instruction that follows the instruction in which switching to stop mode was specified. the cpu then proceeds to interrupt processing. figure 5.5-4 shows the operation of return to normal mode from stop mode. figure 5.5-4 release of stop mode (by external reset) rst pin stop mode main clock pll clock cpu clock cpu operation oscillation stabilization wait oscillating inactive inactive main clock reset sequence execution reset released. stop mode released.
112 chapter 5 low power consumption mode MB90560 series 5.6 status change diagram figure 5.6-1 shows the status change diagram of f2mc-16lx operation and gives change conditions. n status change diagram figure 5.6-1 status change diagram from all states power-on main clock mode hardware source source clock power-on reset stop state main clock main run main sleep pll cock mode timebase pll run state pll sleep main pll clock reset state clock reset state timer state state state state clock oscillation stabilization wait state reset state standby state oscillation stabiliza- tion wait and reset state
MB90560 series chapter 5 low power consumption mode 113 n low power consumption mode operating states table 5.6-1 lists the operating states of low power consumption mode. table 5.6-1 low power consumption mode operating states l clock mode switching and release (excluding standby mode) table 5.6-2 lists clock mode switching and release. table 5.6-2 clock mode switching and release *1the microcontroller operates using the main clock during the pll clock oscillation stabilization wait state. low power consumption mode condition for transition oscil- lation clock cpu peripheral pin release event main sleep mcs = 1 slp = 1 active active inactive active active reset or interrupt pll sleep mcs = 0 slp = 1 active active inactive active active reset or interrupt timebase timer (spl = 0) mcs = 0 stp = 1 active inactive inactive inactive hold reset or interrupt timebase timer (spl = 1) mcs = 0 stp = 1 active inactive inactive inactive hi-z reset or interrupt stop (spl = 0) mcs = 1 stp = 1 inactive inactive inactive inactive hold reset or interrupt stop (spl = 1) mcs = 1 stp = 1 inactive inactive inactive inactive hi-z reset or interrupt transition conditions after power-on, transition to the main run state [1] source clock oscillation stabilization wait interval ends. (timebase timer output) [2] reset input has been cleared. reset during main run state [3] external reset, software reset, or watchdog timer reset transition from main run state to pll run state [4] mcs = 0 (after pll clock oscillation stabilization wait, switch to pll clock) (*1) return to main run state from pll run state [5] mcs = 1 (pll clock deactivated) reset during pll run state [6] external reset or software reset ([7] after reset, return to pll run state) [8] watch dog reset ([3] after reset, return to main run state)
114 chapter 5 low power consumption mode MB90560 series l switching to and release from standby mode table 5.6-3 lists switching to and release from standby mode. table 5.6-3 switching to and release of standby mode *1the microcontroller operates using the main clock during the pll clock oscillation stabilization wait state. transition conditions transition to main sleep mode [1] slp = 1, mcs = 1 (transition from main run state) [2] slp =1, mcs = 1 (transition from pll run state) release of main sleep mode [3] interrupt input [4] external reset transition to stop mode [5] stp =1, mcs = 1 (transition from main run state) [6] stp =1, mcs = 1 (transition from pll run state) release of stop mode [7] interrupt input ([10] indicates return to main run state after oscillation stabilization wait.) [8] external reset ([9] indicates external reset during oscillation stabili- zation wait state.) transition to pll sleep mode <1>slp = 1, mcs = 0 (transition from pll run state) <2>slp = 1, mcs = 0 (transition from main run state, switch to pll clock after pll clock oscillation stabilization wait) (*1) release of pll sleep mode <3>interrupt input <4>external reset transition to timebase timer mode <5>stp = 1, mcs = 0 (transition from pll run state) <6>stp = 1, mcs = 0 (transition from main run state, switch to pll clock after pll clock oscillation stabilization wait) (*1) release of timebase timer mode <7>interrupt input(*1) <8>external reset (<9> after reset, return to pll run state) (*1)
MB90560 series chapter 5 low power consumption mode 115 5.7 status of pins in standby mode and reset the statues of pins in standby mode and reset are summarized below for each memory access mode. n software pull-up resistor for pins with a pull-up resistor selected by software, the pull-up resistor is disconnected during l level output. n status of pins in single-chip mode table 5.7-1 lists the state of pins in single-chip mode. table 5.7-1 state of pins in single-chip mode *1"input enabled" means that the input function is enabled. select either the pull-up or the pull- down option. alternatively, an external input is required. pins used as output ports are the same as other ports. *2"the preceding status is retained" means that the status of the pin output existing immediately before switching to this mode is retained. note that input is disabled if the preceding status was input. ? "status of the pin output is retained" means that the pin retains the value output from an operating internal peripheral unit or the value output from the port if the pin is used as a port. ? "input disabled" means that the input to the pin is not accepted because the internal circuit is inactive, although operation of the input gate adjacent to the pin is enabled. *3"input shut off" indicates the state in which operation of the input gate adjacent to the pin is disabled. "output hi-z" means that the pin state is high-impedance because driving of the pin driving transistor is disabled. pin name standby mode reset sleep stop spl = 0 spl = 1 p00 to p07 p17 p20 to p27 p30 to p37 p40 to p47 p50 to p57 p60 to p62 the preced- ing status is retained. (*2) the preced- ing status is retained. (*2) input shut off/output hi-z (*3) input disabled/ output hi-z (*1) p10 to p16 p63 input enabled (*1)
116 chapter 5 low power consumption mode MB90560 series 5.8 notes on using low power consumption mode note the following six items to use low power consumption mode: ? switching to standby mode and interrupts ? release of standby mode by an interrupt ? setting of standby mode ? release of stop mode ? release of timebase timer mode ? oscillation stabilization wait time n notes on standby mode l switching to standby mode and interrupts during an interrupt request to the cpu from a peripheral function, the cpu ignores the stp and slp bits of the low power consumption mode control register (lpmcr) even though 1 has been written to these bits. thus, switching to any standby mode is disabled (even after processing the interrupt is completed, there is no switch to standby mode). if the interrupt level is 7 or a higher priority, this action does not depend on whether the interrupt request is accepted by the cpu. however, during execution of interrupt processing by the cpu, if the interrupt request flag for the interrupt is cleared and no other interrupt requests have been issued, switching to standby mode can be done. l release of standby mode caused by an interrupt if an interrupt request of interrupt level 7 or a higher priority is issued from a peripheral function during the sleep, timebase timer, or stop modes, the standby mode is released. this action does not depend on whether the cpu accepts that interrupt. after the release of standby mode, normal interrupt processing is performed. the cpu branches to the interrupt handling routine provided that the priority of the interrupt request indicated by the interrupt level setting bits (il2, il1, and il0 of icr) is higher than the interrupt level mask register (ilm); and the interrupt enable flag (i) of the condition code register (ccr) is set to 1 (enabled). if the interrupt is not accepted, the cpu starts the execution with the instruction that follows the instruction in which switching to standby mode was specified. when interrupt processing is executed normally, the cpu first executes the instruction that follows the instruction in which switching to standby mode was specified. the cpu then proceeds to interrupt processing. depending on the condition when switching to standby mode was performed, however, the cpu may proceed to interrupt processing before executing the next instruction. if the cpu should not branch to the interrupt processing routine immediately on return to normal mode from standby mode, action must be taken to disable interrupts before standby mode is set. l setting of standby mode when 1 is written to the stp bit and slp bit of lpmcr at the same time, switching to standby mode is performed. if the mcs bit of the clock selection register (ckscr) is 0, switching to timebase timer mode is performed; if this bit is 1, switching to stop mode is performed.
MB90560 series chapter 5 low power consumption mode 117 n release of stop mode if an external interrupt is used to release stop mode, the input request level must be h. do not use an l level request because it may cause a malfunction. edge requests do not result in a return from the standby state in a mode in which the clock has stopped. n release of timebase timer mode when timebase timer mode is released, the microcontroller is placed in the pll clock oscillation stabilization wait state. if the pll clock is not used, change the mcs bit of the clock selection register (ckscr) to 1 with the instruction that is to be executed immediately after a reset or on return from an interrupt. if an external interrupt is used to release timebase timer mode, the input request level must be h. an l level request may cause a malfunction. edge requests do not result in a return from the standby state in a mode in which the clock has stopped. n oscillation stabilization wait interval l source clock oscillation stabilization wait interval because the oscillator for source oscillation is halted in stop mode, an oscillation stabilization wait interval is required. a time period selected by the ws1 and ws0 bits of ckscr is used as the oscillation stabilization wait interval. l pll clock oscillation stabilization wait interval the cpu may be working with the main clock and the pll clock may be stopped. if the microcontroller will enter a mode in which the cpu and peripheral functions work with the pll clock, the pll clock initially enters the oscillation stabilization wait state. in this state, the cpu still operates using the main clock. the pll clock oscillation stabilization wait interval is fixed at 2 13 /hclk (hclk: oscillation clock frequency). however, this interval may range from 2 3 /hclk to 3 x 2 13 /hclk depending on the status of the timebase timer, if the timebase timer is not cleared before the pll clock oscillation stabilization wait state is entered. (for example, return to the pll run state from timebase timer mode occurs because of an external reset.)

chapter 6 interrupts this chapter explains the interrupts and extended intelligent i/o service (ei 2 os) in the MB90560 series. 6.1 interrupts ........................................................................................ 120 6.2 interrupt causes and interrupt vectors .......................................... 122 6.3 interrupt control registers and peripheral functions .................... 124 6.4 hardware interrupts........................................................................ 132 6.5 software interrupts ......................................................................... 144 6.6 interrupt of extended intelligent i/o service (ei2os) ..................... 146 6.7 operation of the extended intelligent i/o service (ei2os) .............. 154 6.8 exception processing interrupt ...................................................... 158 6.9 stack operations for interrupt processing ..................................... 160 6.10 sample programs for interrupt processing .................................... 162
120 chapter 6 interrupts MB90560 series 6.1 interrupts this chapter explains the interrupts and extended intelligent i/o service (ei 2 os) in the MB90560 series. ? hardware interrupts ? software interrupts ? interrupts from extended intelligent i/o service (ei 2 os) ? exception processing n interrupt types and functions l hardware interrupt a hardware interrupt transfers control to a user-defined interrupt processing program in response to an interrupt request from a peripheral function. l software interrupt a software interrupt transfers control to a user-defined interrupt processing program triggered by the execution of a dedicated software interrupt instruction (such as the int instruction). l interrupt from extended intelligent i/o service (ei 2 os) the ei 2 os function automatically transfers data between a peripheral function and memory. data transfer, which has ordinarily been executed by an interrupt processing program, can be handled like a direct memory access (dma). when the specified number of data transfers has been terminated, the interrupt processing program is automatically executed. an instruction from ei 2 os is a type of hardware interrupt. l exception processing exception processing is basically the same as an interrupt. when an exception event (execution of an undefined instruction) is detected on the instruction boundary, ordinary processing is interrupted and exception processing is performed. this is equivalent to software interrupt instruction int10.
MB90560 series chapter 6 interrupts 121 n interrupt operation figure 6.1-1 shows the activation and return processing for the four types of interrupt functions. figure 6.1-1 overall flow of interrupt operation main program is there a valid hardware interrupt request? string type (*1) instruction being executed fetch the next instruc- tion and decode int instruction? reti instruction? execute ordinary instruction repetition of string type (*1) instruc- tion completed? move the pointer to the next instruction by pc update *1 when a string type instruction is being executed, the interrupt is evaluated in each step. interrupt activation/return processing ei2os processing ei 2 os? software hardware return interrupt/ exception processing interrupt processing ei 2 os save the dedicated disable acceptance of register on the system stack hardware interrupts (i = 0) save the dedicated register on the system stack return the dedicated register from the system stack, call the interrupt routine, and return to the previous routine specified count terminated? alternatively, is there an end request from the peripheral function? update the cpu inter- rupt processing level (ilm) read the interrupt vector, update pc and pcb, and branch to the interrupt routine
122 chapter 6 interrupts MB90560 series 6.2 interrupt causes and interrupt vectors the f 2 mc-16lx can handle 256 types of interrupt causes. the 256 interrupt vector tables are allocated to the memory at the highest addresses. these interrupt vectors are shared by all interrupts. software interrupts can use all these interrupt vectors (int0 to int256). software interrupts share some interrupt vectors with the hardware interrupts and exception processing interrupts. hardware interrupts used a fixed interrupt vector and interrupt control register (icr) for each peripheral function. n interrupt vectors interrupt vector tables referenced during interrupt processing are allocated to the highest addresses in the memory area (fffc00 h to ffffff h ). interrupt vectors share the same area with ei 2 os, exception processing, hardware, and software interrupts. table 6.2-1 shows the assignment of interrupt numbers and interrupt vectors. table 6.2-1 interrupt vectors reference unused interrupt vectors should be set as the exception processing address. software interrupt instruction vector address l vector address m vector address h mode data interrupt no. hardware interrupt int0 fffffc h fffffd h fffffe h not used #0 none :::::: : int7 ffffe0 h ffffe1 h ffffe2 h not used #7 none int8 ffffdc h ffffdd h ffffde h ffffdf h #8 (reset vector) int9 ffffd8 h ffffd9 h ffffda h not used #9 none int10 ffffd4 h ffffd5 h ffffd6 h not used #10 int11 ffffd0 h ffffd1 h ffffd2 h not used #11 hardware interrupt #0 int12 ffffcc h ffffcd h ffffce h not used #12 hardware interrupt #1 int13 ffffc8 h ffffc9 h ffffca h not used #13 hardware interrupt #2 int14 ffffc4 h ffffc5 h ffffc6 h not used #14 hardware interrupt #3 :::::: : int254 fffc04 h fffc05 h fffc06 h not used #254 none int255 fffc00 h fffc01 h fffc02 h not used #255 none
MB90560 series chapter 6 interrupts 123 n interrupt causes and interrupt vectors/interrupt control registers table 6.2-2 shows the relationship between interrupt causes (excluding software interrupts), interrupt vectors, and interrupt control registers. table 6.2-2 interrupt causes, interrupt vectors, and interrupt control registers o:can be used. x:cannot be used. ? :usable if used with the ei 2 os stop function. d :usable when an interrupt cause that shares the icr is not used. *1- for peripheral functions that share the icr register, the interrupt level will be the same. - if the extended intelligent i/o service is to be used with a peripheral function that shares the icr register with another peripheral function, the service can be used only for one of the functions. - if the extended intelligent i/o service is specified for a peripheral function that shares the icr register with another peripheral function, interrupts are disabled for the other peripheral function sharing the icr register.*1 *2 this priority is applied when interrupts of the same level occur simultaneously. interrupt cause ei 2 os support interrupt vector interrupt control register priority (*2) number address icr address reset x #08 08 h ffffdc h - - high int9 instruction x #09 09 h ffffd8 h -- exception processing x #10 0a h ffffd4 h -- a/d converter conversion termination o #11 0b h ffffd0 h icr00 0000b0 h output compare channel 0 match d #13 0d h ffffc8 h icr01 0000b1 h (*1) 8/16-bit ppg timer 0 counter borrow d #14 0e h ffffc4 h output compare channel 1 match d #15 0f h ffffc0 h icr02 0000b2 h (*1) 8/16-bit ppg timer 1 counter borrow d #16 10 h ffffbc h output compare channel 2 match d #17 11 h ffffb8 h icr03 0000b3 h (*1) 8/16-bit ppg timer 2 counter borrow d #18 12 h ffffb4 h output compare channel 3 match d #19 13 h ffffb0 h icr04 0000b4 h (*1) 8/16-bit ppg timer 3 counter borrow d #20 14 h ffffac h output compare channel 4 match d #21 15 h ffffa8 h icr05 0000b5 h (*2) 8/16-bit ppg timer 4 counter borrow d #22 16 h ffffa4 h output compare channel 5 match d #23 17 h ffffa0 h icr06 0000b6 h (*1) 8/16-bit ppg timer 5 counter borrow d #24 18 h ffff9c h dtp/external interrupt channels 0/1 detection d #25 19 h ffff98 h icr07 0000b7 h (*1) dtp/external interrupt channels 2/3 detection d #26 1a h ffff94 h dtp/external interrupt channels 4/5 detection d #27 1b h ffff90 h icr08 0000b8 h (*1) dtp/external interrupt channels 6/7 detection d #28 1c h ffff8c h 8-bit timer 0/1/2 counter borrow x #29 1d h ffff88 h icr09 0000b9 h (*1) 16-bit reload timer 0 underflow o #30 1e h ffff84 h 16-bit free-running timer overflow x #31 1f h ffff80 h icr10 0000ba h (*1) 16-bit reload timer 1 underflow o #32 20 h ffff7c h input capture channels 0/1 d #33 21 h ffff78 h icr11 0000bb h (*1) 16-bit free-running timer clear x #34 22 h ffff74 h input capture channels 2/3 d #35 23 h ffff70 h icr12 0000bc h (*1) timebase timer x #36 24 h ffff6c h uart1 receive ? #37 25 h ffff68 h icr13 0000bd h (*1) uart1 send d #38 26 h ffff64 h uart0 receive ? #39 27 h ffff60 h icr14 0000be h (*1) uart0 send d #40 28 h ffff5c h flash memory status x #41 29 h ffff58 h icr15 0000bf h (*1) delayed interrupt generator module x #42 2a h ffff54 h low
124 chapter 6 interrupts MB90560 series 6.3 interrupt control registers and peripheral functions interrupt control registers (icr00 to icr15) are located inside the interrupt controller. the interrupt control registers correspond to all peripheral functions that have the interrupt function. these registers control interrupts and the extended intelligent i/o service (ei 2 os). n interrupt control registers table 6.3-1 lists the interrupt control registers and corresponding peripheral functions. table 6.3-1 interrupt control registers n interrupt control register functions all interrupt control registers (icr) do the following: ? set the interrupt level of the corresponding peripheral function. ? select ordinary interrupts or the extended intelligent i/o service as interrupts of the corresponding peripheral function. ? select an extended intelligent i/o service (ei 2 os) channel ? display the status of the extended intelligent i/o service (ei 2 os) some of the functions of the interrupt control registers (icr) differ during writing and reading, as shown in figures 6.3-1 and 6.3-2. do not use a read-modify-write instruction to access the interrupt control registers (icr), since operation will not be correct. address register abbreviation corresponding peripheral function 0000b0 h interrupt control register 00 icr00 a/d converter 0000b1 h interrupt control register 01 icr01 output compare 0, 8/16-bit ppg timer 0 0000b2 h interrupt control register 02 icr02 output compare 1, 8/16-bit ppg timer 1 0000b3 h interrupt control register 03 icr03 output compare 2, 8/16-bit ppg timer 2 0000b4 h interrupt control register 04 icr04 output compare 3, 8/16-bit ppg timer 3 0000b5 h interrupt control register 05 icr05 output compare 4, 8/16-bit ppg timer 4 0000b6 h interrupt control register 06 icr06 output compare 5, 8/16-bit ppg timer 5 0000b7 h interrupt control register 07 icr07 dtp/external interrupts 0, 1, 2, 3 0000b8 h interrupt control register 08 icr08 dtp/external interrupts 4, 5, 6, 7 0000b9 h interrupt control register 09 icr09 8-bit timers 0, 1, 2, 16-bit reload timer 0 0000ba h interrupt control register 10 icr10 16-bit free-run timer overflow, 16-bit reload timer 1 0000bb h interrupt control register 11 icr11 input capture 0, 1, 16-bit free-run timer clear 0000bc h interrupt control register 12 icr12 input capture 2, 3, timebase timer 0000bd h interrupt control register 13 icr13 uart1 0000be h interrupt control register 14 icr14 uart0 0000bf h interrupt control register 15 icr15 flash memory, delayed interrupt generator module
MB90560 series chapter 6 interrupts 125 memo
126 chapter 6 interrupts MB90560 series 6.3 interrupt control registers and peripheral functions 6.3.1 interrupt control registers (icr00 to icr15) interrupt control registers correspond to all peripheral functions that have the interrupt function. the interrupt control registers control the processing when an interrupt request occurs. the functions of these registers partially differ at writing and reading. n interrupt control registers (icr00 to icr15) figure 6.3-1 interrupt control registers (icr00 to icr15) during writing address 0000b0 h to 0000bf h initial value 00000111 b ics3 ics0 ise il2 il1 il0 il2 00 0 0 0 0 1 0 0 11 1 00 1 01 1 10 1 11 1 il1 il0 interrupt level setting bit interrupt level 0 (highest) interrupt level 7 (no interrupt) ise 0 1 ei 2 os enable bit activates the interrupt sequence when an interrupt occurs activates ei 2 os when an interrupt occurs ics3 ics2 ics1 ics0 channel 0 0 0 0 0 000100 h 1 000108 h 2 000110 h 3 000118 h 4 000120 h 5 000128 h 6 000130 h 7 000138 h 8 000140 h 9 000148 h 10 000150 h 11 000158 h 12 000160 h 13 000168 h 14 000170 h 15 000178 h 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 descriptor address ei 2 os channel selection bit ics2 ics1 bit7 w w w w r/w r/w r/w r/w bit6 bit5 bit4 bit3 bit2 bit1 bit0 during writing icr r/w: read/write w: write-only : initial value
MB90560 series chapter 6 interrupts 127 figure 6.3-2 interrupt control registers (icr00 to icr15) during reading address 0000b0 h to 0000bf h initial value xx000111 b - s0 ise il2 il1 il0 il2 00 0 0 0 0 1 0 0 11 1 00 1 01 1 10 1 11 1 il1 il0 interrupt level setting bit interrupt level 0 (highest) interrupt level 7 (no interrupt) ise 0 1 ei 2 os enable bit activates the interrupt sequence when an interrupt occurs activates ei 2 os when an interrupt occurs s1 s0 00 01 10 11 ei 2 os status ei 2 os operation in progress or ei2os not activated stopped status due to count termination reserved stopped status due to a request from the peripheral function -s1 bit7 during reading icr r r r/w r/w r/w r/w bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w: read/write r: write-only - : not used x: undefined : initial value
128 chapter 6 interrupts MB90560 series 6.3 interrupt control registers and peripheral functions 6.3.2 interrupt control register functions the interrupt control registers (icr00 to icr15) consist of the following four functional bits: ? interrupt level setting bits (il2 to il0) ? extended intelligent i/o service (ei 2 os) enable bit (ise) ? extended intelligent i/o service (ei 2 os) channel selection bits (ics3 to ics0) ? extended intelligent i/o service (ei 2 os) status (s1 to s0) n configuration of interrupt control registers (icr) figure 6.3-3 shows the configuration of the interrupt control register (icr) bits. figure 6.3-3 configuration of interrupt control registers (icr) reference ? the ics3 to ics0 bits are valid only when the extended intelligent i/o service (ei 2 os) has been activated. to activate ei 2 os, set the ise bit to 1. to not activate ei 2 os, set the ise bit to 0. when ei 2 os is not activated, setting ics3 to ics0 is optional. ? ics1 and ics0 are valid only for writing. s1 and s0 are valid only for reading. n interrupt control register functions l interrupt level setting bits (il2 to il0) these bits set the interrupt level of the corresponding peripheral function. these bits are initialized to level 7 (no interrupts) by a reset. table 6.3-2 shows the correspondence between the interrupt level setting bits and interrupt levels. writing to interrupt control register (icr) address 0000b0 h to 0000bf h address 0000b0 h to 0000bf h reading of interrupt control register (icr) initial value initial value r: w: - : read-only write-only not used
MB90560 series chapter 6 interrupts 129 table 6.3-2 correspondence between the interrupt level setting bits and interrupt levels l extended intelligent i/o service (ei 2 os) enable bit (ise) if this bit is 1 when an interrupt request is generated, ei 2 os is activated. if this bit is 0 when an interrupt request is generated, the interrupt sequence is activated. when the ei 2 os termination condition is met (when the s1 and s0 bits are not 00 b ), the ise bit is cleared. if the corresponding peripheral function does not have the ei 2 os function, the ise bit must be set to 0 by software. the ise bit is initialized to 0 by a reset. l extended intelligent i/o service (ei 2 os) channel selection bits (ics3 to ics0) these write-only bits specify the ei 2 os channel. the ei 2 os descriptor address is determined based on the value set here. the ics bit is initialized to 0000 b by a reset. table 6.3-3 shows the correspondence between the ei 2 os channel selection bits and descriptor addresses. table 6.3-3 correspondence between the ei 2 os channel selection bits and descriptor addresses il2 il1 il0 interrupt level 000 0 (highest priority) 001 010 011 100 101 110 6 (lowest priority) 111 7 (no interrupts) ics3 ics2 ics1 ics0 selected channel descriptor address 0 0 0 0 0 000100 h 0 0 0 1 1 000108 h 0010 2 000110 h 0011 3 000118 h 0 1 0 0 4 000120 h 0 1 0 1 5 000128 h 0 1 1 0 6 000130 h 0 1 1 1 7 000138 h 1 0 0 0 8 000140 h 1 0 0 1 9 000148 h 1 0 1 0 10 000150 h 1 0 1 1 11 000158 h 1 1 0 0 12 000160 h 1 1 0 1 13 000168 h 1 1 1 0 14 000170 h 1 1 1 1 15 000178 h
130 chapter 6 interrupts MB90560 series l extended intelligent i/o service (ei 2 os) status bits (s1, s0) these are read-only bits. when this value is checked at ei 2 os termination, the operating status and termination status can be distinguished. these bits are initialized to 00 b by a reset. table 6.3-4 shows the relationship between the s0 and s1 bits and the ei 2 os status table 6.3-4 relationship between ei 2 os status bits and the ei 2 os status s1 s0 ei 2 os status 00 ei 2 os operation in progress or ei 2 os not activated 0 1 stopped status due to count termination 10reserved 1 1 stopped status due to a request from the peripheral function
MB90560 series chapter 6 interrupts 131 memo
132 chapter 6 interrupts MB90560 series 6.4 hardware interrupts the hardware interrupt function temporarily interrupts the program being executed by the cpu and transfers control to a user-defined interrupt processing program in response to an interrupt signal from a peripheral function. the extended intelligent i/o service (ei 2 os) and external interrupts are executed as a type of hardware interrupt. n hardware interrupts l hardware interrupt function the hardware interrupt function compares the interrupt level of the interrupt request signal output by a peripheral function with the interrupt level mask register (ilm) in the cpu processor status (ps). the function then references the contents of the i flag in the processor status (ps) through the hardware and decides if the interrupt can be accepted. when the hardware interrupt is accepted, the cpu internal registers are automatically saved on the system stack. the currently requested interrupt level is stored in the interrupt level mask register (ilm), and the function branches to the corresponding interrupt vector. l multiple interrupts multiple hardware interrupts can be activated. l extended intelligent i/o service (ei 2 os) ei 2 os is an automatic transfer function between memory and i/o. when the specified transfer count has been completed, a hardware interrupt is activated. multiple ei 2 os activation is not possible to occur. during ei 2 os processing, all other interrupt requests and ei 2 os requests are held. l external interrupt an external interrupt (including wake-up interrupts) is accepted from a peripheral function (interrupt request detection circuit) as a hardware interrupt. l interrupt vector interrupt vector tables referenced during interrupt processing are allocated to memory at fffc00 h to ffffff h . these tables are shared by software interrupts. see section 6.2, "interrupt causes and interrupt vectors," for more information about the allocation of interrupt numbers and interrupt vectors.
MB90560 series chapter 6 interrupts 133 n hardware interrupt structure table 6.4-1 lists four mechanisms used for hardware interrupts. these four mechanisms must be included in the program before hardware interrupts can be used. table 6.4-1 mechanisms used for hardware interrupts mechanism function peripheral function interrupt enable bit, interrupt request bit controls interrupt requests from a peripheral function interrupt controller interrupt control register (icr) sets the interrupt level and controls ei 2 os cpu interrupt enable flag (i) identifies the interrupt enable status interrupt level mask register (ilm) compares the request interrupt level and cur- rent interrupt level microcode executes the interrupt processing routine fffc00 h to ffffff h in memory interrupt vector table stores the branch destination address for interrupt processing
134 chapter 6 interrupts MB90560 series n hardware interrupt suppression acceptance of hardware interrupt requests is suppressed under the following conditions. l hardware interrupt suppression during writing to the peripheral function control register area when data is being written to the peripheral function control register area, hardware interrupt requests are not accepted. this prevents the cpu from making operational mistakes. the mistakes may be caused if an interrupt request is generated during data is being written to the interrupt control registers for a resource. the peripheral function control register area is not the i/ o addressing area at 000000 h to 0000ff h , but the area allocated to the control register of the peripheral function control register and data register. figure 6.4-1 shows hardware interrupt operation during writing to the built-in peripheral area figure 6.4-1 hardware interrupt request while writing to the peripheral function control register area l hardware interrupt suppression by interrupt suppression instruction the ten types of hardware interrupt suppression instructions listed in table 6.4-2 ignore interrupt requests without detecting whether a hardware interrupt request exists. table 6.4-2 hardware interrupt suppression instruction even if a valid hardware interrupt request is generated during execution of one of these instructions, the interrupt is not processed until the first time an instruction of a different type is executed. l hardware interrupt suppression during execution of software interrupt when a software interrupt is activated, the i flag is cleared to 0. in this state, other interrupt requests cannot be accepted. prefix code interrupts/hold suppression instructions (instructions that delay the effect of the prefix code) instructions that do not accept interrupts and hold requests pcb dtb adb spb cmr ncc mov ilm, #imm8 or ccr, #imm8 and ccr, #imm8 popw ps mov a, #08 mov io,a mov a,2000h interrupt processing . . . . . instruction that writes to the peripheral function control register area an interrupt request is generated here does not branch to the interrupt branches to the interrupt
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136 chapter 6 interrupts MB90560 series 6.4 hardware interrupts 6.4.1 operation of hardware interrupts this section explains hardware interrupt operation from generation of a hardware interrupt request to the completion of interrupt processing. n hardware interrupt activation l peripheral function operation (generation of an interrupt request) a peripheral function that has a hardware interrupt request function also has an interrupt request flag that indicates the presence of interrupt requests and an interrupt enable flag that determines whether cpu interrupt requests are enabled or disabled. the interrupt request flag is set when an event specified by the peripheral function occurs. l interrupt controller operation (interrupt request control) when two or more interrupt requests are received at the same time, the interrupt controller compares their interrupt levels (il) in their interrupt requests register. the interrupt controller selects the request with the highest level (with the smallest il value) and posts it to the cpu. when multiple requests have the same level, the request with the smallest interrupt number has the highest priority. l cpu operation (interrupt request acceptance and interrupt processing) the cpu compares the received interrupt level (icr: il2 to il0) and the interrupt level mask register (ilm). if il < ilm and interrupts are enabled (ps: ccr: i = 1), the cpu activates the interrupt processing microcode after the instruction currently being executed terminates. at the beginning of the interrupt processing microcode, the cpu checks the ise bit in the interrupt control register (icr). if ise = 0, the cpu continues the execution of interrupt processing. (if ise = 1, ei 2 os is activated.) interrupt processing saves the contents of the dedicated registers (12 bytes including a, dpr, adb, dtb, pcb, pc, and ps) on the system stack (the system stack space indicated by the ssb and ssp). the cpu then loads data into the interrupt vector program counters (pcb and pc), updates the ilm, and sets the stack flag (s) (sets ccr: s = 1 and activates the system stack). n returning from a hardware interrupt in an interrupt processing program, when the interrupt request flag of the peripheral function that generated the interrupt cause is cleared and the reti instruction is executed, 12-byte data saved on the system stack is restored to the dedicated registers and the processing that was being executed before branching for the interrupt is resumed. when the interrupt request flag is cleared, interrupt requests output by the peripheral function to the interrupt controller are automatically canceled.
MB90560 series chapter 6 interrupts 137 n hardware interrupt operation figure 6.4-2 shows hardware interrupt operation from generation of a hardware interrupt to the completion of interrupt processing. figure 6.4-2 hardware interrupt operation (1) an interrupt cause is generated by the peripheral function. (2) the interrupt enable bit of the peripheral function is checked. if the interrupt is enabled, the interrupt request is sent from the peripheral function to the interrupt controller. (3) the interrupt controller determines the priority of simultaneous interrupt requests, then transfers the interrupt level (il) that matches the corresponding interrupt request to the cpu. (4) the cpu compares the interrupt level (il) requested by the interrupt controller with the interrupt level mask register (ilm). (5) if the comparison indicates a higher priority than the current interrupt processing level, the cpu checks the contents of the i flag in the condition code register (ccr). (6) if in the check in (5) shows that the i flag is interrupt enabled (i = 1), the cpu waits until the execution of the instruction currently being executed terminates. at termination, the cpu sets the requested level (il) in the ilm. (7) registers are saved, and processing branches to the interrupt processing routine. (8) the interrupt cause that was generated in (1) is cleared by software in the interrupt processing routine. execution of the reti instruction terminates the interrupt processing. internal bus microcode check comparator other peripheral peripheral function that generated enable ff factor ff level interrupt interrupt controller the interrupt request functions comparator level il il: ps: i: ilm: ir: ff: interrupt level setting bit in the interrupt control register (icr) processor status interrupt enable flag interrupt level mask register instruction register flip-flop
138 chapter 6 interrupts MB90560 series 6.4 hardware interrupts 6.4.2 processing for interrupt operation when an interrupt request is generated by the peripheral function, the interrupt controller transmits the interrupt level to the cpu. if the cpu is able to accept interrupts, the interrupt controller temporarily interrupts the instruction currently being executed. the interrupt controller then executes the interrupt processing routine or activates the extended intelligent i/o service (ei 2 os). if a software interrupt is generated by the int instruction, the interrupt processing routine is executed regardless of the cpu status. in this case, hardware interrupts are not allowed. n processing for interrupt operation figure 6.4-3 shows the flow of processing for interrupt operation. figure 6.4-3 flow of interrupt processing start main program yes yes yes yes interrupt activation/return processing yes yes no no no no no ei 2 os software inter- rupt/exception processing hardware instruction ei 2 os processing return processing i&if&if=1 and lm>il int instruction? ise = 1 reti instruction? specified count terminated? alter- natively, is there a termination request from the peripheral function? fetch the next instruction and deode execute ordinary instruction (including interrupt processing) repetition of string type (*1) instruction completed? move the pointer to the next instruction by pc update return the dedicated registers from the system stack, call the interrupt routine, and return to the previous routine i <- 0 (disable hardware interrupts) pcb, pc <- interrupt vector (branch to the interrupt processing routine) s <- 1 (activates the system stack) ilm <- il (transfer the interrupt level of the accepted interrupt request to the ilm) save the dedicated registers to the system stack save the dedicated registers to the system stack string type (*1) instruction in progress *1 when a string type instruction is being executed, the interrupt is evaluated in each step. i: interrupt enable flag of the condition code register (ccr) if: interrupt request flag of the peripheral function ie: interrupt enable flag of the peripheral function ilm: interrupt level mask register (in the ps) ise: ei2os enbale flag ofthe interruptor control register (icr) il: interrupt level setting bit of the interrupt control register (icr) s: stack flag of the condition code register (ccr) pcb: program bank register pc: program counter:
6.4 hardware interrupts MB90560 series chapter 6 interrupts 139 6.4.3 procedure for using hardware interrupts before hardware interrupts can be used, the system stack area, peripheral function, and interrupt control register (icr) must be set. n procedure for using hardware interrupts figure 6.4-4 shows an example of the procedure for using hardware interrupts. figure 6.4-4 procedure for using hardware interrupts (1) set the system stack area. (2) initialize a peripheral function that can generate interrupt requests. (3 set the interrupt control register (icr) in the interrupt controller. (4) set the peripheral function to the operation start status, and set the interrupt enable bit to enable. (5) set the interrupt level mask register (ilm) and interrupt enable flag (i) to interrupt acceptable. (6) an interrupt generated in the peripheral function causes a hardware interrupt request. (7) the interrupt processing hardware saves the registers and branches to the interrupt processing program. (8) the interrupt processing program processes the peripheral function in response to the generated interrupt. (9) clear the peripheral function interrupt request. (10) execute the interrupt return instruction, and return to the program location before branching. (1) (2) (3) (4) (5) (6) (7) (8) (9) (10) start set operation start for the peripheral function. set the interrupt enable bit to enable set the icr in the interrupt controller initialize the peripheral function set the system stack area set the ilm and i in the ps main program interrupt request generated hardware processing main program stack processing branches to the interrupt vector processing for interrupt to the peripheral function (execute the interrupt processing routine) interrupt processing program clear the interrupt cause interrupt return instruction (reti)
140 chapter 6 interrupts MB90560 series 6.4 hardware interrupts 6.4.4 multiple interrupts multiple hardware interrupts can be implemented by setting different interrupt levels in the interrupt level setting bits (il0, il1, il2) of the interrupt control register (icr) in response to multiple interrupt requests from peripheral functions. use of multiple interrupts, however, is not possible with the extended intelligent i/o service. n multiple interrupts l operation of multiple interrupts during execution of an interrupt processing routine, if an interrupt request with a higher-priority interrupt level is generated, the current interrupt processing is interrupted and the interrupt request with the higher-priority interrupt level is accepted. when the interrupt request with the higher-priority interrupt level terminates, the cpu returns to the previous interrupt processing. 0 to 7 can be set as the interrupt level. if level 7 is set, the cpu does not accept interrupt requests. during execution of interrupt processing, if an interrupt request with the same or lower-priority interrupt level is generated, the new interrupt request is held until the current interrupt terminates unless the i flag or ilm is changed. other multiple interrupts to be activated during an interrupt can be temporarily disabled by setting the i flag in the condition code register (ccr) in the interrupt processing routine to interrupts not allowed (ccr: i = 0) or the interrupt level mask register (ilm) to interrupts not allowed (ilm = 000). the extended intelligent i/o service (ei 2 os) cannot be used for the activation of multiple interrupts. during processing of the extended intelligent i/o service (ei 2 os), all other interrupt requests and extended intelligent i/o service requests are held. l example of multiple interrupts this example of multiple interrupt processing assumes that a timer interrupt is given a higher priority than an a/d converter interrupt. in this example, the a/d converter interrupt level is set to 2, and the timer interrupt level is set to 1. if a timer interrupt is generated during processing of the a/d converter interrupt, the processing shown in figure 6.4-5 is performed.
MB90560 series chapter 6 interrupts 141 figure 6.4-5 example of multiple interrupts m a/d interrupt generated when the a/d converter interrupt processing starts, the interrupt level mask register (ilm) automatically has the same value (2 in the example) as the a/d converter interrupt level (icr: il2 to il0). if a level-1 or level-0 interrupt request is generated, this interrupt processing has priority. m interrupt processing terminated when the interrupt processing terminates and the return instruction (reti) is executed, the values of the dedicated registers (a, dpr, adb, dtb, pcb, pc, and ps) are returned from the stack, and the interrupt level mask register (ilm) has the value that it had before the interrupt. main program a/d interrupt processing timer interrupt processing peripheral initialization a/d interrupt generated main processing restarts interrupt level 2 interrupted restart timer interrupt interrupt level 1 timer interrupt processing timer interrupt return a/d interrupt a/d interrupt return (ilm = 010) generated processing (ilm = 001)
142 chapter 6 interrupts MB90560 series 6.4 hardware interrupts 6.4.5 hardware interrupt processing time from the occurrence of a hardware interrupt request to the execution of an interrupt processing routine, the time for the instruction currently being executed to terminate and the time required to handle an interrupt are necessary. n hardware interrupt processing time from the occurrence of a hardware interrupt request to the acceptance of the interrupt and to the execution of an interrupt processing routine, the time to wait for sampling for an interrupt request and the time required to handle an interrupt (time to prepare for interrupt processing) are necessary. figure 6.4-6 shows the interrupt processing time. figure 6.4-6 interrupt processing time l interrupt request sampling wait time the interrupt request sampling wait time is the time from the occurrence of and interrupt request to the termination of the instruction currently being executed. whether an interrupt request has been occurred is determined by sampling the instruction for an interrupt request in the final cycle of the instruction. consequently, the cpu cannot identify an interrupt request during execution of each instruction creating a delay. the interrupt request sampling wait time is the maximum when an interrupt request is generated as soon as the popw rw0, ... rw7 instruction (45 machine cycles), which takes the longest to execute, starts. cpu operation interrupt wait time interrupt request generation ordinary instruction interrupt request interrupt handling execution interrupt processing routine sampling wait time interrupt handling time ( q machine cycle) (*1) : the final instruction cycle samples the interrupt request here. : one machine cycle corresponds to one machine clock ( f ).
MB90560 series chapter 6 interrupts 143 l interrupt handling time ( q machine cycle) the cpu saves dedicated registers to the system stack and fetches interrupt vectors after it receives an interrupt request. the required handling time for this processing is q machine cycles. the interrupt handling time is calculated with the following formula: when an interrupt is activated: q = 24 + 6 + z machine cycles when returning from an interrupt: q = 11 + 6 + z machine cycles (reti instruction) the interrupt handling time is different depending on each address pointed to by the stack pointer. table 6.4-3 shows the compensation values (z) for the interrupt handling time. table 6.4-3 compensation values (z) for the interrupt handling time one machine cycle corresponds to one clock cycle of the machine clock ( f ). address pointed to by the stack pointer compensation value (z) external 8-bit +4 external even-numbered address +1 external odd-numbered address +4 internal even-numbered address 0 internal odd-numbered address +2
144 chapter 6 interrupts MB90560 series 6.5 software interrupts when the software interrupt instruction (int instruction) is executed, the software interrupt function transfers control from the program being executed by the cpu to the user-defined interrupt processing program. hardware interrupts are disabled during execution of a software interrupt. n software interrupt activation l software interrupt activation the int instruction is used to activate a software interrupt. there is no interrupt request flag or enable flag for software interrupt requests. when the int instruction is executed, an interrupt request is always generated. l hardware interrupt suppression since the int instruction does not have interrupt levels, the interrupt level mask register (ilm) is not updated. during the execution of the int instruction, the i flag of the condition code register (ccr) is set to 0, and hardware interrupts are masked. to enable hardware interrupts during software interrupt processing, set the i flag to 1 in the software interrupt processing routine. l software interrupt operation when the cpu fetches the int instruction, the software interrupt processing microcode is activated. this microcode saves the internal cpu registers on the system stack, masks hardware interrupts (ccr: i = 0), and branches to the corresponding interrupt vector. see section 6.2, "interrupt causes and interrupt vectors," in chapter 6 for more information about the allocation of interrupt numbers and interrupt vectors. n returning from a software interrupt in the interrupt processing program, when the interrupt return instruction (reti instruction) is executed, the 12-byte data saved into the system stack is restored to the dedicated registers and the processing that was being executed before branching for the interrupt is resumed.
MB90560 series chapter 6 interrupts 145 n software interrupt operation figure 6.5-1 shows software interrupt operation from the occurrence of a software interrupt to the completion of interrupt processing. figure 6.5-1 software interrupt operation (1)a software interrupt instruction is executed. (2)the dedicated registers are saved according to the microcode that corresponds to the software interrupt instruction, and other necessary processing is performed. branch processing is then executed. (3)the reti instruction in the user interrupt processing routine terminates the interrupt processing. when the program bank register (pcb) is ff h , the vector area of the callv instruction overlaps the int #vct8 instruction table. when creating the software, be careful of the duplicated address of the callv instruction and int #vct8 instruction. internal bus microcode queue fetch ps: i: s: ir: processor status interrupt enable flag stack flag instruction register
146 chapter 6 interrupts MB90560 series 6.6 interrupt of extended intelligent i/o service (ei2os) the extended intelligent i/o service (ei 2 os) automatically transfers data between a peripheral function (i/o) and memory. when the data transfer terminates, a hardware interrupt is generated. n extended intelligent i/o service (ei 2 os) the extended intelligent i/o service is a type of hardware interrupt. it automatically transfers data between a peripheral function (i/o) and a memory. traditionally, data transfer with a peripheral function (i/o) has been performed by the interrupt processing program. ei 2 os performs this data transfer in the same way as direct memory access (dma). at termination, ei 2 os sets the termination condition and automatically branches to the interrupt processing routine. the user creates programs only for ei 2 os activation and termination. data transfer programs in between are not required. l advantages of extended intelligent i/o service (ei 2 os) compared to data transfer performed by the interrupt processing routine, ei 2 os has the following advantages. ? coding a transfer program is not necessary, reducing program size. ? because transfer can be stopped depending on the peripheral function (i/o) status, unnecessary data transfer can be eliminated. ? incrementing or no updating can be selected for the buffer address. ? incrementing or no updating can be selected for the i/o register address. l extended intelligent i/o service (ei 2 os) termination interrupt when data transfer by ei 2 os terminates, a termination condition is set in the s1 and s0 bits in the interrupt control register (icr). processing then automatically branches to the interrupt processing routine. the ei 2 os termination factor can be determined by checking the ei 2 os status (icr: s1, s0) with the interrupt processing program. interrupt numbers and interrupt vectors are permanently set for each peripheral. see section 6.2, "interrupt causes and interrupt vectors," in chapter 6 for more information. l interrupt control register (icr) this register, which is located in the interrupt controller, activates ei 2 os, specifies the ei 2 os channel, and displays the (ei2os) termination status. l extended intelligent i/o service (ei 2 os) descriptor (isd) this descriptor, which is located in ram at 000100 h to 00017f h , is an eight-byte data that retains the transfer mode, i/o address, transfer count, and buffer address. the descriptor handles 16 channels. the channel is specified by the interrupt control register (icr). when the extended intelligent i/o service (ei 2 os) is operating, execution of the cpu program stops.
MB90560 series chapter 6 interrupts 147 n operation of the extended intelligent i/o service (ei 2 os) figure 6.6-1 shows ei 2 os operation. figure 6.6-1 extended intelligent i/o service (ei 2 os) operation (1)i/o requests transfer. (2)the interrupt controller selects the descriptor. (3)the transfer source and transfer destination are read from the descriptor. (4)transfer is performed between i/o and memory. (5)the interrupt cause is automatically cleared. memory space i/o register peripheral functon (i/o) interrupt request interrupt control register (icr) interrupt controller buffer isd: ioa: bap: ics: dct: ei 2 os descriptor i/o address pointer buffer address pointer ei 2 os channel selection bit in the interrupt control register (icr) data counter i/o register
148 chapter 6 interrupts MB90560 series 6.6 interrupt of extended intelligent i/o service (ei2os) 6.6.1 extended intelligent i/o service (ei2os) descriptor (isd) the extended intelligent i/o service (ei 2 os) descriptor (isd) resides in internal ram at 000100 h to 00017f h . the isd consists of 8 bytes x 16 channels. n configuration of the extended intelligent i/o service (ei2os) descriptor (isd) the isd consists of 8 bytes x 16 channels. each isd has the structure shown in figure 6.6-2. table 6.6-1 shows the correspondence between channel numbers and isd addresses. figure 6.6-2 configuration of ei 2 os descriptor (isd) table 6.6-1 correspondence between channel numbers and descriptor addresses channel descriptor address 0 000100 h 1 000108 h 2000110 h 3000118 h 4 000120 h 5 000128 h 6 000130 h 7 000138 h 8 000140 h 9 000148 h 10 000150 h 11 000158 h 12 000160 h 13 000168 h 14 000170 h 15 000178 h i/o register address pointer upper 8 b its (ioah) data counter lower 8 bits (dctl) data counter upper 8 bits (dcth) i/o register address pointer lower 8 b its (ioal) ei 2 os status register (iscs) buffer address pointer upper 8 bits (baph) buffer address pointer middle 8 bits (bapm) buffer address pointer lower 8 bits (bapl) first isd address (000100 h + 8 x ics) l h
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150 chapter 6 interrupts MB90560 series 6.6 interrupt of extended intelligent i/o service (ei2os) 6.6.2 registers of the extended intelligent i/o service (ei 2 os) descriptor (isd) the extended intelligent i/o service (ei 2 os) descriptor (isd) consists of the following registers. ? data counter (dct) ? i/o register address pointer (ioa) ? ei 2 os status register (iscs) ? buffer address pointer (bap) note that the initial value of each register is undefined after a reset. n data counter (dct) the dct is a 16-bit register that serves as a counter for the data transfer count. after each data transfer, the counter is decremented by 1. when the counter reaches zero, ei 2 os terminates. figure 6.6-3 shows the configuration of the dct. figure 6.6-3 configuration of dct n i/o register address pointer (ioa) the ioa is a 16-bit register that indicates the lower address (a15 to a0) of the i/o register used to transfer data to and from the buffer. the upper address (a23 to a16) is all zeros. any i/o from 000000 h to 00ffff h can be specified by address. figure 6.6-4 shows the configuration of the ioa. figure 6.6-4 configuration of i/o register address pointer (ioa) r/w: x: read-write undefined initial value r/w: x: read-write undefined initial value
MB90560 series chapter 6 interrupts 151 n extended intelligent i/o service (ei 2 os) status register (iscs) the iscs is an 8-bit register. the iscs indicates the update/fixed for the buffer address pointer and i/o register address pointer, transfer data format (byte or word), and transfer direction. figure 6.6-5 shows the configuration of the iscs. figure 6.6-5 configuration of ei 2 os status register (iscs) n buffer address pointer (bap) the bap is a 24-bit register that retains the address used by ei 2 os for the next transfer. since one independent bap exists for each ei 2 os channel, each ei 2 os channel can transfer data between any address in the 16-megabyte space and the i/o. if the bf bit (bap update/fixed selection bit in the ei 2 os status register) in the ei 2 os status register (iscs) is set to "update yes," only the lower 16 bits (baph, bapl) of the bap change; the upper 8 bits (baph) do not change. figure 6.6-6 shows the configuration of the bap. initial value ei 2 os termination control bit not terminated by a request from the peripheral function. terminated by a request from the peripheral function data transfer direction specification bit i/o register address pointer ? buffer address pointer. buffer address pointer ? i/o register address pointer bap update/fixed selection bit after data transfer, the buffer address pointer is updated. (*1) after data transfer, the buffer address pointer is not updated. transfer data length specification bit byte word after data transfer, the buffer address pointer is not updated. ioa update/fixed selection bit after data transfer, the i/o register address pointer is updated. (*2) reserved bits 0 must be written to these bits. r/w: x: *1 *2 read-write undefined only the lower 16 bits of the buffer address pointer change. the buffer address pointer the address pointer can only be incremented. can only be incremented.
152 chapter 6 interrupts MB90560 series figure 6.6-6 configuration of buffer address pointer (bap) reference ? the area that can be specified by the i/o address pointer (ioa) extends from 000000 h to 00ffff h . ? the area that can be specified with the buffer address pointer (bap) extends from 000000 h to ffffff h . ? the maximum transfer count that can be specified by the data counter (dct) is 65,536 (64 kilobytes). to to to initial value r/w: read-write undefined x:
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154 chapter 6 interrupts MB90560 series 6.7 operation of the extended intelligent i/o service (ei2os) if an interrupt request is generated by a peripheral function, ei 2 os activation is set in the corresponding interrupt control register (icr) that the cpu uses ei 2 os to transfer data. when the specified data transfer count terminates, the hardware interrupt is automatically processed. n operation flow of the extended intelligent i/o service (ei 2 os) figure 6.7-1 shows the flow of ei 2 os operation based on the internal microcode of the cpu. figure 6.7-1 flow of extended intelligent i/o service (ei 2 os) operation interrupt request generated by peripheral function read isd/iscs termination request from peripheral function if = 0 bf = 0 dct = 00 dir = 1 ise = 1 se = 1 data indicated by ioa (data transfer) memory indicated by bap decrement dct no no no no no no no yes yes yes yes (-1) yes updage value by bw updage value by bw yes ei 2 os termination processing yes set s1 and s0 to 00 set s1 and s0 to 01 clear ise to 0 interrupt sequence clear interrupt request from the peripheral function return to cpu operation set s1 and s0 to 11 interrupt sequence data indicated by bap (data transfer) memory indicated by bap update ioa update bap isd: ei2os descriptor iscs: ei2os status register if: ioa update/fixed selection bit in the ei2os status register (iscs) bw: transfer data length specification bit in the ei2os status register (iscs) bf: bap update/fixed selection bit in the ei2os status register (iscs) dir: data transfer direction specification bit in the ei2os status register (iscs) se: ei2os termination control bit in the ei2os status register (iscs) dct: data counter ioa: i/o register address pointer bap: buffer address pointer ise: ei2os enable bit in the interrupt control register s1, s0: ei2os status in the interrupt control register (icr)
6.7 operation of the extended intelligent i/o service (ei2os) MB90560 series chapter 6 interrupts 155 6.7.1 procedure for using the extended intelligent i/o service (ei2os) before the extended intelligent i/o service (ei 2 os) can be used, the system stack area, extended intelligent i/o service (ei 2 os) descriptor, interrupt function, and interrupt control register (icr) must be set. n procedure for using the extended intelligent i/o service (ei 2 os) figure 6.7-2 shows the ei 2 os software and hardware processing. figure 6.7-1 procedure for using the extended intelligent i/o service (ei 2 os) start software processing hardware processing set the system stack area set the ei 2 os descriptor initialize the peripheral function set the interrupt control register (icr) set the built-in peripheral to start operation. set the interrupt enable bit set the ilm and i in the ps execute the user program transfer data (branch to interrupt vector) s1, s0 = "01" or s1, s0 = "11" decide whether to end counting or to branch to an interrupt requested by the resource set the extended intelligent i/o service again (switch channels) process data in the buffer reti ise: ei 2 os enable bit in the interrupt control register (icr) s1, s0: ei 2 os status of the interrupt control register (icr) yes no (interrupt request) and (ise = 1) initializa- tion s1, s0 = "00"
156 chapter 6 interrupts MB90560 series 6.7 operation of the extended intelligent i/o service (ei2os) 6.7.2 processing time of the extended intelligent i/o service (ei2os) the time required for processing the extended intelligent i/o service (ei 2 os) is varied according to the following factors: ? ei 2 os status register (iscs) setting ? address (area) pointed by the i/o register address pointer (ioa) ? address (area) pointed by the buffer address pointer (bap) ? external data bus length for external access ? transfer data length because the hardware interrupt is activated when data transfer by ei 2 os terminates, the interrupt handling time is needed to be considered. n processing time (one transfer time) of the extended intelligent i/o service (ei 2 os) l when data transfer continues the ei 2 os processing time for data transfer continuation is shown in table 6.7-1 based on the ei 2 os status register (iscs) setting. table 6.7-1 extended intelligent i/o service execution time unit:machine cycle (one machine cycle corresponds to one clock cycle of the machine clock ( f ). as shown in table 6.7-2, compensation is necessary depending on the ei 2 os execution condition. table 6.7-2 data transfer compensation value for ei 2 os execution time b:byte data transfer 8:external bus using the 8-bit word transfer even:even-numbered address word transfer odd:odd-numbered address word transfer ei 2 os termination control bit (se) setting terminates due to termination request from the peripheral ignores termination request from the peripheral ioa update/fixed selection bit (if) setting fixed update fixed update bap address update/fixed selection bit (bf) setting fixed32343335 update34363537 i/o register address pointer internal access external access b/even odd b/even 8/odd buffer address pointer internal access b/even 0 +2 +1 +4 odd+2+4+3+6 external access b/even +1 +3 +2 +5 8/odd+4+6+5+8
MB90560 series chapter 6 interrupts 157 l when the data counter (dct) count terminates (final data transfer) because the hardware interrupt is activated when data transfer by ei 2 os terminates, the interrupt handling time is added. the ei 2 os processing time when counting terminates is calculated with the following formula: ei 2 os processing time when counting terminates = ei 2 os processing time when data is transferred + (21 + 6 x z) machine cycles interrupt handling time the interrupt handling time is different for each address pointed to by the stack pointer. table 6.7-3 shows the compensation value (z) for the interrupt handling time. table 6.7-3 interpolation value (z) for the interrupt handling time l for termination by a termination request from the peripheral function (i/o) when data transfer by ei 2 os is terminated before completion due to a termination request from the peripheral function (i/o) (icr: s1, s0 = 11), the data transfer is not performed and a hardware interrupt is activated. the ei 2 os processing time is calculated with the following formula. z in the formula indicates the compensation value for the interrupt handling time (table 6.7-3). ei 2 os processing time for termination before completion = 36 + 6 x z machine cycle one machine cycle is equal to one clock cycle of the machine clock ( f ). address pointed to by the stack pointer compensation value (z) external 8-bit +4 external even-numbered address +1 external odd-numbered address +4 internal even-numbered address 0 internal odd-numbered address +2
158 chapter 6 interrupts MB90560 series 6.8 exception processing interrupt in the f 2 mc-16lx, the execution of an undefined instruction results in exception processing. exception processing is basically the same as an interrupt. when the generation of an exception processing is detected on the instruction boundary, ordinary processing is interrupted and exception processing is executed. generally, exception processing occurs as the result of an unexpected operation. exception processing should be used only to activate recovery software required for debugging or an emergency. n exception processing l exception processing operation the f 2 mc-16lx handles all codes that are not defined in the instruction map as undefined instructions. when an undefined instruction is executed, processing equivalent to the int #10 software interrupt instruction is executed. the following processing is executed before exception processing branches to the interrupt routine: ? the a, dpr, adb, dtb, pcb, pc, and ps registers are saved to the system stack. ? the i flag of the condition code register (ccr) is cleared to 0, and hardware interrupts are masked. ? the s flag of the condition code register (ccr) is set to 1, and the system stack is activated. the program counter (pc) value saved to the stack is the exact address where the undefined instruction is stored. for 2-byte or longer instruction codes, the code identified as undefined is stored at this address. when the exception factor type must be determined within the exception processing routine, use this pc value. l return from exception processing when the reti instruction returns control from exception processing, exception processing restarts because the pc is pointing to the undefined instruction. provide a solution such as resetting the software.
MB90560 series chapter 6 interrupts 159 memo
160 chapter 6 interrupts MB90560 series 6.9 stack operations for interrupt processing once an interrupt is accepted, the contents of the dedicated registers are automatically saved to the system stack before a branch to interrupt processing. when the interrupt processing terminates, the previous processing is automatically restored from the stack. n stack operations at the start of interrupt processing once an interrupt is accepted, the cpu automatically saves the contents of the current dedicated registers to the system stack in the order given below: ? accumulator (a) ? direct page register (dpr) ? additional data bank register (adb) ? data bank register (dtb) ? program bank register (pcb) ? program counter (pc) ? processor status (ps) figure 6.9-1 shows the stack operations at the start of interrupt processing. figure 6.9-1 stack operations at the start of interrupt processing n stack operations on return from interrupt processing when the interrupt return instruction (reti) is executed at the termination of interrupt processing, the ps, pc, pcb, dtb, adb, dpr, and a values are returned from the stack in reverse order from the order they were placed on the stack. the dedicated registers are restored to the status they had immediately before the start of interrupt processing. immediately before interrupt address memory immediately after interrupt address memory byte byte sp after update
MB90560 series chapter 6 interrupts 161 n stack area l stack area allocation the stack area is used for saving and restoring the program counter (pc) when the subroutine call instruction (call) and vector call instruction (callv) are executed in addition to interrupt processing. the stack area is used for temporary saving and restoring of registers by the pushw and popw instructions. the stack area is allocated together with the data area in ram. figure 6.9-2 shows the stack area. figure 6.9-2 stack area ? generally set an even-numbered address in the stack pointers (ssp and usp). ? allocate the system stack area, user stack area, and data area so that they do not overlap. l system stack and user stack the system stack area is used for interrupt processing. when an interrupt occurs, the user stack area being used is forcibly switched to the system stack. the system stack area must be set correctly even in a system that mainly uses the user stack area. if division of the stack space is not particularly necessary, use only the system stack. vector table (interrupt vector call instruction for a reset) stack area built-in ram area general-purpose register bank area built-in i/o area rom area *1 the internal rom is different for each model. *2 the internal ram is different for each model.
162 chapter 6 interrupts MB90560 series 6.10 sample programs for interrupt processing this section contains sample programs for interrupt processing. n sample programs for interrupt processing l processing specifications the following is a sample program for an interrupt that uses external interrupt 0 (int0). l sample coding ddr1 equ 000011h ; port 1 direction register enir equ 030h ; interrupt/dtp enable register enrr equ 031h ; interrupt/dtp flag elvr equ 032h ; request level setting register icr00 equ 0b0h ; interrupt control register stack sseg ; stack rw 100 stack_t rw 1 stack ends ;---------main program -------------------------------------------------------------------------------------------------------- ----- codecseg start: mov rp,#0 ; general-purpose registers use the first bank. mov ilm, #07h ; sets ilm in ps to level 7. mov a, #!stack_t ; sets system stack. mov ssb, a movw a, #stack_t ; sets stack pointer, then movw sp, a ; sets ssp because s flag = 1. mov ddr1, #00000000b ; sets p10/int0 pin to input. or ccr, #40h ; sets i flag of ccr in ps, enables interrupts. mov e:icr00, #00h ; sets interrupt level to 0 (highest priority). mov i:elvr, #00000001b ; requests that int0 be made level h. mov i:enrr, #00h ; clears int0 interrupt cause. mov i:enrr, #01h ; enables int0 input. : loop: nop ; dummy loop nop nop nop bra loop ; unconditional jump ;---------interrupt program ---------------------------------------------------------------------------------------------- ed_int1: mov i:eirr, #00h ; acceptance of new int0 not allowed nop nop nop nop nop nop reti ; return from interrupt code ends ;--------vector setting----------------------------------------------------------------------------------------------------- vect cseg abs=0ffh org 0ffd0h ; sets vector for interrupt #11 (0bh). dsl ed_int1 org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
MB90560 series chapter 6 interrupts 163 n processing specifications of sample program for extended intelligent i/o service (ei 2 os) 1)this program detects the h level signal input to the int0 pin and activates the extended intelligent i/o service (ei 2 os). 2)when the h level is input to the int0 pin, ei 2 os is activated. data is transferred from port 0 to the memory at the 3000 h address. 3)the number of transfer data bytes is 100 bytes. after 100 bytes are transferred, an interrupt is generated because ei 2 os transfer has terminated. l sample coding ddr1 equ 000011h ; port 1-direction register enir equ 000030h ; interrupt/dtp enable register enrr equ 000031h ; interrupt/dtp factor register elvr equ 000032h ; request level setting register icr00 equ 0000b0h ; interrupt control register bapl equ 000100h ; lower buffer address pointer bapm equ 000101h ; middle buffer address pointer baph equ 000102h ; upper buffer address pointer iscs equ 000103h ; ei 2 os status ioal equ 000104h ; lower i/o address pointer ioah equ 000105h ; upper i/o address pointer dctl equ 000106h ; low-order data counter dcth equ 000107h ; high-order data counter er0 equ enrr:0 ; definition of external interrupt request flag bit stack sseg ; stack rw 100 stack_t rw 1 stack ends ;-------------------main program------------------------------------------------------------------------------------------ codecseg start: and ccr, #0bfh ; clears the i flag of the ccr in the ps and ; prohibits interrupts. mov rp, #00 ; sets the register bank pointer. mov a, #stack_t ; sets the system stack. mov ssb, a movw a, #stack_t ; sets the stack pointer, then movw sp, a ; sets ssp because the s flag = 1. mov i:ddr1, #00000000b ; sets the p10/int0 pin to input. mov bapl, #00h ; sets the buffer address (003000h). mov bapm, #30h mov baph, #00h mov iscs, #00010001b ; no i/o address update, byte transfer, ; buffer address updated ; i/o ? buffer transfer, terminated by the ; peripheral function. mov ioal, #00h ; sets the transfer source address ; (port 0: 000000h). mov ioah, #00h mov dctl, #64h ; sets the number of transfer bytes (100 bytes). mov dcth, #00h mov i:icr00, #00001000b ; ei 2 os channel 0, ei 2 os enable, ; interrupt level 0 (highest priority) mov i:elvr, #00000001b ; requests that int0 be made h level. mov i:enrr, #00h ; clears the int0 interrupt cause. mov i:enir, #01h ; enables int0 interrupts. mov ilm, #07h ; sets the ilm in the ps to level 7. or ccr, #40h ; sets the i flag of the ccr in the ps ; and enables interrupts.
164 chapter 6 interrupts MB90560 series : loop bra loop ; infinite loop ;---------------interrupt program---------------------------------------------------------------------------------------------- ----- wari clrb er0 ; clears interrupt/dtp request flag. : user processing ; checks ei 2 os termination factor, : ; processes data in buffer, sets ei 2 os again. reti code ends ;---------------vector processing---------------------------------------------------------------------------------------------- --- vect cseg abs=0ffh org 0ffd0h ; sets vector for interrupt #11 (0bh). dsl wari org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
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chapter 7 setting a mode this chapter describes the operating modes and memory access modes supported by the MB90560 series. 7.1 setting a mode ............................................................................... 168 7.2 mode pins (md2 to md0)............................................................... 169 7.3 mode data...................................................................................... 170
168 chapter 7 setting a mode MB90560 series 7.1 setting a mode the f 2 mc-16lx supports the modes for access method, access areas, and tests. a mode is determined based on the settings by the mode pin at a reset as well as the mode data fetched. n mode setting the f 2 mc-16lx supports the modes for access method, access areas, and tests, classified as shown in figure 7.1-1 in this module. figure 7.1-1 mode classification n operating modes the operating modes control the operating state of the device, and are specified by the mode setting pin (mdx) and mx bit contents in mode data. selecting operating modes enables normal operation, and the activation of internal test programs and special test functions. because the MB90560 series is only used in single-chip mode, set md2, 1, 0 to 011 and set m1, 0 to 00. n bus mode the bus mode controls the operation of internal rom and external access functions, and is specified by the mode setting pin (mdx) and mx bit contents in mode data. the mode setting pin (mdx) specifies bus mode when reset vector and mode data are read. the mx bit in mode data specifies bus mode during normal operation. n run mode the run mode means cpu operating mode. the run mode includes main clock mode, pll clock mode, and various low power consumption modes. see chapter 5, "low power consumption modes," for details. because the MB90560 series is only used in single-chip mode, set md2, 1, 0 to 011 and set m1, 0 to 00. operating mode bus mode single-chip mode run eprom programming modes
MB90560 series chapter 7 setting a mode 169 7.2 mode pins (md2 to md0) three external pins, md2 to md0, are supported as the mode pins. these are used to specify how the reset vector and mode data are fetched. n mode pins (md2 to md0) the mode pins are used to select the data bus (external or internal) used for reading the reset vector and to specify the bus width when the external data bus is selected. for a prom version, the mode pins are also used to specify prom programming mode, which is used to write programs and other data to internal rom. table 7.2-1 shows the mode pin settings. table 7.2-1 mode pin settings md2 to md0: connect the pins to vss for 0 and to vcc for 1. because the MB90560 series is only used in single-chip mode, set md2, 1, 0 to 011 and set m1, 0 to 00. md2 md2 md0 mode name reset vector access area external data bus width remarks 000 setting not allowed 001 010 0 1 1 internal vector mode internal mode data the reset sequence and subsequent sequences are controlled by mode data. 100 setting not allowed 101 110 111 prom programming mode -- -
170 chapter 7 setting a mode MB90560 series 7.3 mode data the mode data is at memory location ffffdf h , and is used to specify the operation after a reset sequence. the mode data is automatically fetched to the cpu. n mode data during a reset sequence, the mode data at address ffffdf h is fetched to the mode register in the cpu core. the cpu uses the mode data to set the memory access mode. the contents of the mode register can only be changed during the reset sequence. the settings in the register take effect after the reset sequence. figure 7.3-1 shows the mode data configuration. figure 7.3-1 mode data configuration n bus mode setting bits the bus mode setting bits specify operating mode after a reset sequence. table 7.3-1 lists the relationship between the bits and functions. table 7.3-1 bus mode setting bits and functions because the MB90560 series is only used in single-chip mode, set m2, 1, 0 to 011 and set m1, 0 to 00. m1 m0 function remarks 0 0 single-chip mode 8 bits 01 (setting not allowed) (mode data) 10 11 7 6 543210 m1 m0 0 0 0 0 0 0 mode data function extension bits (reserved area) bus mode setting bits
MB90560 series chapter 7 setting a mode 171 figure 7.3-2 shows the correspondence between access areas and physical addresses in single-chip mode. figure 7.3-2 correspondence between access areas and physical addresses in single-chip mode n relationship between mode pins and mode data table 7.3-2 lists the relationship between mode pins and mode data. table 7.3-2 relationship between mode pins and mode data the MB90560 series is only used in single-chip mode. mode md2 md1 md0 m1 m0 single-chip mode 0 1 1 0 0 rom rom when mirror rom function is selected ram no access : : internal access ffffff h 0000c0 h 000000 h 000100 h model #3 00ffff h ff0000 h model #1 model #2 note: model #x becomes the model-dependent address.

chapter 8 i/o ports this chapter describes the functions and operations of the i/o ports. 8.1 overview of i/o ports ..................................................................... 174 8.2 port register .................................................................................. 175 8.3 port 0.............................................................................................. 176 8.4 port 1.............................................................................................. 182 8.5 port 2.............................................................................................. 188 8.6 port 3.............................................................................................. 194 8.7 port 4.............................................................................................. 200 8.8 port 5.............................................................................................. 206 8.9 port 6.............................................................................................. 212 8.10 sample i/o port program ............................................................... 218
174 chapter 8 i/o ports MB90560 series 8.1 overview of i/o ports an i/o port can be used as a general-purpose i/o port (parallel i/o port). the MB90560 series has six ports (50 pins). the ports are also used for peripheral function i/o pins (peripheral function i/o pins). n i/o port functions each i/o port outputs data from the cpu to the i/o pins or inputs signals from the i/o pins to the cpu as directed by the port data register (pdr). each i/o port can also be set the direction of a data flow (input or output) at the i/o pins for each bit using the port data direction register (ddr). the function of each port and the peripheral functions using it are described below: ? port 0 : general-purpose i/o port ? port 1 : general-purpose i/o port/peripheral function (external interrupt input pins) ? port 2 : general-purpose i/o port/peripheral function (16-bit reload timer/icu) ? port 3 : general-purpose i/o port/peripheral function (ocu/uart0) ? port 4 : general-purpose i/o port/peripheral function (uart0, 8-bit/16-bit ppg timer) ? port 5 : general-purpose i/o port/peripheral function (analog input pins) ? port 6 : general-purpose i/o port/peripheral function (uart1) table 8.1-1 summarizes the functions of individual ports. table 8.1-1 functions of individual ports port 5 is also used as analog input pins. to use the port as a general-purpose port, be sure to reset the corresponding bit of the analog data input enable register (ader) to 0. resetting the cpu sets the ader register bits to 1. port pin input form output form function bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 port 0 p00~p07 cmos (hysteresis) cmos pull- up resistor selectable general i/o port CCCCCCCC p07p06p05p04p03p02p01p00 peripheral function CCCCCCCCCCCCCCCC port 1 p10/int0 ~p17/frck general i/o port p17 p16 p15 p14 p13 p12 p11 p10 CCCCCCCC peripheral function frck int6 int5 int4 int3 int2 int1 int0 CCCCCCCC port 2 p20/tin0 ~p27/in3 cmos general i/o port CCCCCCCC p27p26p25p24p23p22p21p20 peripheral function CCCCCCCC in3 in2 in1 in0 to1 tin1 to0 tin0 port 3 p30/rto0 ~p37/sot0 general i/o port p37 p36 p35 p34 p33 p32 p31 p30 CCCCCCCC peripheral function sot0 sin0 rto5 rto4 rto3 rto2 rto1 rto0 CCCCCCCC port 4 p40/sck0 ~p46/ppg5 general i/o port CCCCCCCCC p46 p45 p44 p43 p42 p41 p40 peripheral function CCCCCCCCC ppg5 ppg4 ppg3 ppg2 ppg1 ppg0 sck0 port 5 p50/an0 ~p57/an7 analog/cmos (hysteresis) cmos general i/o port p57 p56 p55 p54 p53 p52 p51 p50 CCCCCCCC analog input an7 an6 an5 an4 an3 an2 an1 an0 CCCCCCCC port 6 p60/sin1 ~p63/int7/ dtti analog input cmos general i/o port CCCCCCCCCCCC p63 p62 p61 p60 peripheral function CCCCCCCCCCCC int7/ dtti sck1 sot1 sin1
MB90560 series chapter 8 i/o ports 175 8.2 port register this section provides a list of the registers related to the i/o port settings and shows how each port is assigned to the external pins. n registers for i/o ports table 8.2-1 is a list of the registers corresponding to individual ports. table 8.2-1 registers and corresponding ports r/w:read/write enabled r:read only x:undefined C:not used register read/write address initial value port 0 data register (pdr0) r/w 000000h xxxxxxxxb port 1 data register (pdr1) r/w 000001h xxxxxxxxb port 2 data register (pdr2) r/w 000002h xxxxxxxxb port 3 data register (pdr3) r/w 000003h xxxxxxxxb port 4 data register (pdr4) r/w 000004h Cxxxxxxxb port 5 data register (pdr5) r/w 000005h xxxxxxxxb port 6 data register (pdr6) r/w 000006h ----xxxxb port 0 data direction register (ddr0) r/w 000010h 00000000b port 1 data direction register (ddr1) r/w 000011h 00000000b port 2 data direction register (ddr2) r/w 000012h 00000000b port 3 data direction register (ddr3) r/w 000013h 00000000b port 4 data direction register (ddr4) r/w 000014h C0000000b port 5 data direction register (ddr5) r/w 000015h 00000000b port 6 data direction register (ddr6) r/w 000016h ----0000b analog data input enable register (ader) r/w 000017h 11111111b port 0 pull-up resistor setting register (rdr0) r/w 00008ch 00000000b port 1 pull-up resistor setting register (rdr1) r/w 00008dh 00000000b
176 chapter 8 i/o ports MB90560 series 8.3 port 0 port 0 is a general-purpose i/o port. this section provides the configuration of port 0, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 0 configuration port 0 consists of the following: ? general-purpose i/o pins ? port 0 data register (pdr0) ? port 0 data direction register (ddr0) ? port 0 pull-up resistor setting register (rdr0) n port 0 pins table 8.3-1 lists the port 0 pins. table 8.3-1 port 0 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function i/o form circuit type input output port 0 p00 p00 general- purpose i/o cmos (hysteresis) cmos c p01 p01 p02 p02 p03 p03 p04 p04 p05 p05 p06 p06 p07 p07
MB90560 series chapter 8 i/o ports 177 n block diagram of port 0 pins figure 8.3-1 is a block diagram of the port 0 pins. figure 8.3-1 block diagram of port 0 pins n port 0 registers port 0 registers are pdr0, ddr0, and rdr0. the bits making up each register correspond to the port 0 pins on a one-to-one basis. table 8.3-2 lists the port 0 pins and their corresponding register bits. table 8.3-2 port 0 pins and their corresponding register bits see section 1.7,"i/o circuit types,"for information on the circuit types. port register bits and corresponding port pins port 0 pdr0,ddr0,rdr0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin p07 p06 p05 p04 p03 p02 p01 p00 internal data bus rdr port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) pull-up resistor about 50k w
178 chapter 8 i/o ports MB90560 series 8.3 port 0 8.3.1 port 0 registers (pdr0, ddr0, and rdr0) this section describes the port 0 registers. n functions of port 0 registers l port 0 data register (pdr0) the pdr0 register indicates the state of each pin of port 0. l port 0 data direction register (ddr0) the ddr0 register specifies the direction of a data flow (input or output) at each pin (bit) of port 0. when a ddr0 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. l port 0 pull-up resistor setting register (rdr0) the rdr0 register specifies the selection of a pull-up resistor at each pin (bit) of port 0. when a rdr0 register bit is 1, a pull-up resistor is selected for the corresponding port (pin). when the bit is 0, the pull-up resistor is deselected. table 8.3-3 lists the functions of the port 0 registers. table 8.3-3 port 0 register functions r/w : read/write enabled x : undefined register dat a during reading during writing read/ write address initial value port 0 data register (pdr0) 0 the pin is at the low level. the output latch is loaded with 0. when the pin functions as an output port, the pin is set to the low level. r/w 000000h xxxxxxxxb 1 the pin is at the high level. the output latch is loaded with 1. when the pin functions as an output port, the pin is set to the high level. port 0 data direction register (ddr0) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000010h 00000000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode. port 0 pull-up resistor setting register (rdr0) 0 the setting latch is 0. the pull-up resistor is cut and the port is placed in the hi-z state in input mode. r/w 00008ch 00000000b 1 the setting latch is 1. the pull-up resistor is selected and the port is held at the high level in input mode.
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180 chapter 8 i/o ports MB90560 series 8.3 port 0 8.3.2 operation of port 0 this section describes the operation of port 0. n operation of port 0 l port operation in output mode ? setting a bit of the ddr0 register to 1 places the corresponding port pin in output mode. ? data written to the pdr0 register in output mode is held in the output latch of the pdr and output to the port pins. ? the pdr0 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write the output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? writing a bit of the ddr0 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? however, when the rdr0 register is set to 1 to select a pull-up resistor, the pins are held at the high level. ? data written to the pdr0 register in input mode is stored in the output latch of the pdr but is not output to the port pins. ? the pdr0 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation after a reset ? when the cpu is reset, the ddr0 and pdr registers are initialized to 0. as a result, the output buffer is turned off (i/o mode changes to input), the pull-up resistor is cut, and the pins are placed in a high impedance state. ? the pdr0 register is not initialized when the cpu is reset. to use the port in output mode, therefore, output mode must be specified in the ddr0 register after the output data is set in the pdr0 register.
MB90560 series chapter 8 i/o ports 181 l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power consumption mode control register (lpmcr) is already 1 when the cpu is shifted to stop or time-base timer mode, the port pins are placed in a high-impedance state. this is because the output buffer is turned off forcibly regardless of the value in the ddr0 register. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a high-impedance state even when the spl bit is set to 1. table 8.3-4 lists the states of the port 0 pins. table 8.3-4 states of port 0 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time-base timer mode (spl = 0) stop mode or time-base timer mode (spl = 1, rdr = 0) stop mode or time-base timer mode (spl = 1, rdr = 1) p00~p07 general-purpose i/o port general-purpose i/o port general-purpose i/o port input shut down/ output in hi-z input shut down/held at h level
182 chapter 8 i/o ports MB90560 series 8.4 port 1 port 1 is a general-purpose i/o port. it can also be used for peripheral function input. the port pins can be switched individually between the i/o port and peripheral function. this section focuses on the general i/o port function. the section provides the configuration of port 1, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 1 configuration port 1 consists of the following: ? general-purpose i/o pins/external interrupt input pins (p10/int0 to p17/frck) ? port 1 data register (pdr1) ? port 1 data direction register (ddr1) ? port 1 pull-up resistor setting register (rdr1) n port 1 pins the port 1 pins are also used as peripheral function input pins. the pins cannot be used as output port pins when they are used as peripheral function input pins. table 8.4-1 lists the port 1 pins. table 8.4-1 port 1 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function peripheral function i/o form circuit type input output port 1 p10/int0 p10 general- purpose i/o int0 external interrupt input cmos (hystere sis) cmos c p11/int1 p11 int1 p12/int2 p12 int2 p13/int3 p13 int3 p14/int4 p14 int4 p15/int5 p15 int5 p16/int6 p16 int6 p17/frck p17 frck
MB90560 series chapter 8 i/o ports 183 n block diagram of port 1 pins figure 8.4-1 is a block diagram of port 1 pins. figure 8.4-1 block diagram of port 1 pins n port 1 registers port 1 registers are pdr1, ddr1, and rdr1. the bits making up each register correspond to the port 1 pins on a one-to-one basis. table 8.4-2 lists the port 1 pins and their corresponding register bits. table 8.4-2 port 1 pins and their corresponding register bits port register bits and corresponding port pins port 1 pdr1,ddr1,rdr1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 corresponding pin p17 p16 p15 p14 p13 p12 p11 p10 internal data bus rdr port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) pull-up resistor about 50k w peripheral input (int) frck
184 chapter 8 i/o ports MB90560 series 8.4 port 1 8.4.1 port 1 registers (pdr1, ddr1, and rdr1) this section describes the port 1 registers. n functions of port 1 registers l port 1 data register (pdr1) the pdr1 register indicates the state of each pin of port 1. l port 1 data direction register (ddr1) the ddr1 register specifies the direction of a data flow (input or output) at each pin (bit) of port 1. when a ddr1 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. l port 1 pull-up resistor setting register (rdr1) the rdr1 register specifies the selection of a pull-up resistor at each pin (bit) of port 1. when a rdr1 register bit is 1, a pull-up resistor is selected for the corresponding port (pin). when the bit is 0, the pull-up resistor is deselected. to use a peripheral function having input pins, reset the port direction register bit corresponding to each peripheral function input pin to 0 to place the port in input mode. table 8.4-3 lists the functions of the port 1 registers. table 8.4-3 port 1 register functions r/w : read/write enabled x : undefined register data during reading during writing read/ write address initial value port 1 data register (pdr1) 0 the pin is at the low level. the output latch is loaded with 0. when the pin functions as an output port, the pin is set to the low level. r/w 000001h xxxxxxxxb 1 the pin is at the high level. the output latch is loaded with 1. when the pin functions as an output port, the pin is set to the high level. port 1 data direction register (ddr1) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000011h 00000000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode. port 1 pull-up resistor setting register (rdr1) 0 the setting latch is 0. the pull-up resistor is cut and the port is placed in the hi-z state in input mode. r/w 00008dh 00000000b 1 the setting latch is 1. the pull-up resistor is selected and the port is held at the high level in input mode.
MB90560 series chapter 8 i/o ports 185 memo
186 chapter 8 i/o ports MB90560 series 8.4 port 1 8.4.2 operation of port 1 this section describes the operation of port 1. n operation of port 1 l port operation in output mode ? setting a bit of the ddr1 register to 1 places the corresponding port pin in output mode. ? data written to the pdr1 register in output mode is stored in the output latch of the pdr and output to the port pins as is. ? the pdr1 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write the output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? writing a bit of the ddr1 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? however, when the rdr1 register is set to 1 to select a pull-up resistor, the pins are held at the high level. ? data written to the pdr1 register in input mode is stored in the output latch of the pdr but not output to the port pins. ? the pdr1 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation for peripheral function input when the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. to use an external signal for the peripheral function, reset the ddr1 register to 0 to place the port in input mode. l port operation after a reset ? when the cpu is reset, the ddr1 and pdr registers are initialized to 0. as a result, the output buffer is turned off (i/o mode changes to input), the pull-up resistor is cut, and the pins are placed in a high impedance state. ? the pdr1 register is not initialized when the cpu is reset. to use the port in output mode, therefore, output mode must be specified in the ddr1 register after the output data is set in the pdr1 register.
MB90560 series chapter 8 i/o ports 187 l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power mode control register (lpmcr) is already 1 when the cpu is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state. this is because the output buffer is turned off forcibly regardless of the value in the ddr1 register. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. note also that when a pull-up resistor is selected, the port pins are held at the high level and not placed in a high-impedance state even when the spl bit is set to 1. table 8.4-4 lists the states of the port 1 pins. table 8.4-4 states of port 1 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time-base timer mode (spl = 0) stop mode or time-base timer mode (spl = 1, rdr = 0) stop mode or time- base timer mode (spl = 1, rdr = 1) p10/ int0~p17 /frck general-purpose i/o port general-purpose i/o port general-purpose i/o port input enabled/ output in hi-z input shut down/ held at h level
188 chapter 8 i/o ports MB90560 series 8.5 port 2 port 2 is a general-purpose i/o port. it can also be used for peripheral function input and output. the port pins can be switched in units of bits between the i/o port and the peripheral function. this section focuses on the general i/o port function. this section also provides the configuration of port 2, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 2 configuration port 2 consists of the following: ? general-purpose i/o pins/peripheral function i/o pins (p20/tin0 to p27/in3) ? port 2 data register (pdr2) ? port 2 data direction register (ddr2) n port 2 pins the port 2 i/o pins are also used as peripheral function i/o pins. the pins cannot be used as general-purpose i/o port pins when they are used as peripheral function i/o pins. table 8.5-1 lists the port 2 pins. table 8.5-1 port 2 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function peripheral function i/o form circuit type input output port 2 p20/tin0 p20 general- purpose i/o tin0 16-bit reload timer 0 event input cmos (hysteresis) cmos d p21/to0 p21 to0 16-bit reload timer 0 timer output p22/tin1 p22 tin1 16-bit reload timer 1 event input p23/to1 p23 to1 16-bit reload timer 1 timer output p24/in0 p24 in0 input capture channel 0 input p25/in1 p25 in1 input capture channel 1 input p26/in2 p26 in2 input capture channel 2 input p27/in3 p27 in3 input capture channel 3 input
MB90560 series chapter 8 i/o ports 189 n block diagram of port 2 pins figure 8.5-1 is a block diagram of port 2 pins. figure 8.5-1 block diagram of port 2 pins when the peripheral function output enable bit is set, the port is forcibly caused to function as peripheral function output pins regardless of the value in the ddr2 register. n port 2 registers port 2 registers are pdr2 and ddr2. the bits making up each register correspond to the port 2 pins on a one-to-one basis. table 8.5-2 lists the port 2 pins and their corresponding register bits. table 8.5-2 port 2 pins and their corresponding register bits port register bits and corresponding port pins port 2 pdr2,ddr2 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin p27 p26 p25 p24 p23 p22 p21 p20 internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) peripheral input peripheral output peripheral output enable
190 chapter 8 i/o ports MB90560 series 8.5 port 2 8.5.1 port 2 registers (pdr2 and ddr2) this section describes the port 2 registers. n functions of port 2 registers l port 2 data register (pdr2) the pdr2 register indicates the state of each pin of port 2. l port 2 data direction register (ddr2) the ddr2 register specifies the direction of a data flow (input or output) at each pin (bit) of port 2. when a ddr2 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. ? when a peripheral function having output pins is used, the port functions as peripheral function output pins regardless of the value in the ddr2 register as long as the peripheral function output enable bit corresponding to the pins is set. ? to use a peripheral function having input pins, reset the ddr2 register bit corresponding to each peripheral function input pin to 0 to place the port in input mode. table 8.5-3 lists the functions of the port 2 registers. table 8.5-3 port 2 register functions r/w : read/write enabled x : undefined register data during reading during writing read/ write address initial value port 2 data register (pdr2) 0 the pin is at the low level. the output latch is loaded with 0. when the pin functions as an output port, the pin is set to the low level. r/w 000002h xxxxxxxxb 1 the pin is at the high level. the output latch is loaded with 1. when the pin functions as an output port, the pin is set to the high level. port 2 data direction register (ddr2)) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000012h 00000000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode.
MB90560 series chapter 8 i/o ports 191 memo
192 chapter 8 i/o ports MB90560 series 8.5 port 2 8.5.2 operation of port 2 this section describes the operation of port 2. n operation of port 2 l port operation in output mode ? setting a bit of the ddr2 register to 1 places the corresponding port pin in output mode. ? data written to the pdr2 register in output mode is stored in the output latch of the pdr and output to the port pins as is. ? the pdr2 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? writing a bit of the ddr2 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? data written to the pdr2 register in input mode is store in the output latch of the pdr but not output to the port pins. ? the pdr2 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation for peripheral function output the peripheral function output enable bit is set to enable the port to be used for peripheral function output. the state of the peripheral function enable bit takes precedence when specifying a switch between input and output. even if a ddr2 register bit is 0, the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. l port operation for peripheral function input when the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. to use an external signal for the peripheral function, reset the ddr2 register to 0 to place the port in input mode.
MB90560 series chapter 8 i/o ports 193 l port operation after a reset ? when the cpu is reset, the ddr2 register is initialized to 0. as a result, the output buffer is turned off (i/o mode changes to input), the pins are placed in a high impedance state. ? the pdr2 register is not initialized when the cpu is reset. to use the port in output mode, therefore, output mode must be specified in the ddr2 register after the output data is set in the pdr2 register. l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power mode control register (lpmcr) is already 1 when the cpu is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state. this is because the output buffer is turned off forcibly regardless of the value in the ddr2 register. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. table 8.5-4 lists the states of the port 2 pins. table 8.5-4 states of port 2 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time-base timer mode (spl = 0) stop mode or time-base timer mode (spl = 0) stop mode or time- base timer mode (spl = 1) p20/int0~ p27/in3 general-purpose i/o port general-purpose i/o port general-purpose i/o port input enabled/ output in hi-z input shut down/output in hi-z
194 chapter 8 i/o ports MB90560 series 8.6 port 3 port 3 is a general-purpose i/o port. it can also be used for peripheral function input and output. the port pins can be switched in units of bits between the i/o port and peripheral function. this section focuses on the general i/o port function. it provides the configuration of port 3, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 3 configuration port 3 consists of the following: ? general-purpose i/o pins/peripheral function i/o pins (p30/ppg0 to p37/sot0) ? port 3 data register (pdr3) ? port 3 data direction register (ddr3) n port 3 pins the port 3 i/o pins are also used as peripheral function i/o pins. therefore, the pins cannot be used as general-purpose i/o port pins when they are used as peripheral function i/o pins. table 8.6-1 lists the port 3 pins. table 8.6-1 port 3 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function (single-chip mode) peripheral function i/o form circuit type input output port 3 p30/rto0 p30 general- purpose i/o rto0 ocu channel 0 output cmos (hysteresis) cmos d p31/rto1 p31 rto1 ocu channel 1 output p32/rto2 p32 rto2 ocu channel 2 output p33/rto3 p33 rto3 ocu channel 3 output p34/rto4 p34 rto4 ocu channel 4 output p35/rto5 p35 rto5 ocu channel 5 output p36/sin0 p36 sin0 uart0 data input p37/sot0 p37 sot0 uart0 data output
MB90560 series chapter 8 i/o ports 195 n block diagram of port 3 pins figure 8.6-1 is a block diagram of port 3 pins. figure 8.6-1 block diagram of port 3 pins n port 3 registers port 3 registers are pdr3 and ddr3. the bits making up each register correspond to the port 3 pins on a one-to-one basis. table 8.6-2 lists the port 3 pins and their corresponding register bits. table 8.6-2 port 3 pins and their corresponding register bits port register bits and corresponding port pins port 3 pdr3, ddr3 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 corresponding pin p37 p36 p35 p34 p33 p32 p31 p30 internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) peripheral input peripheral output peripheral output enable
196 chapter 8 i/o ports MB90560 series 8.6 port 3 8.6.1 port 3 registers (pdr3 and ddr3) this section describes the port 3 registers. n functions of port 3 registers l port 3 data register (pdr3) the pdr3 register indicates the state of each pin of port 3. l port 3 data direction register (ddr3) the ddr3 register specifies the direction of a data flow (input or output) at each pin (bit) of port 3. when a ddr3 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. ? when a peripheral function having output pins is used, the port functions as peripheral function output pins regardless of the value in the ddr3 register as long as the peripheral function output enable bit corresponding to the pins is set. ? to use a peripheral function having input pins, reset the ddr3 register bit corresponding to each peripheral function input pin to 0 to place the port in input mode. table 8.6-3 lists the functions of the port 3 registers. table 8.6-3 port 3 register functions r/w : read/write enabled x : undefined register data during reading during writing read/ write address initial value port 3 data register (pdr3) 0 the pin is at the low level. the output latch is loaded with 0. when the pin functions as an output port, the pin is set to the low level. r/w 000003h xxxxxxxxb 1 the pin is at the high level. the output latch is loaded with 1. when the pin functions as an output port, the pin is set to the high level. port 3 data direction register (ddr3) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000013h 00000000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode.
MB90560 series chapter 8 i/o ports 197 memo
198 chapter 8 i/o ports MB90560 series 8.6 port 3 8.6.2 operation of port 3 this section describes the operation of port 3. n operation of port 3 l port operation in output mode ? setting a bit of the ddr3 register to 1 places the corresponding port pin in output mode. ? data written to the pdr3 register in output mode is stored in the output latch of the pdr and output to the port pins as is. ? the pdr3 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? writing a bit of the ddr3 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? data written to the pdr3 register in input mode is stored in the output latch of the pdr but not output to the port pins. ? the pdr3 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation for peripheral function output the peripheral function output enable bit is set to enable the port to be used for peripheral function output. the state of the peripheral function enable bit takes precedence when specifying a switch between input and output. even if a ddr3 register bit is 0, the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. l port operation for peripheral function input when the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. to use an external signal for the peripheral function, reset the ddr3 register to 0 to place the port in input mode.
MB90560 series chapter 8 i/o ports 199 l port operation after a reset ? when the cpu is reset, the ddr3 register is initialized to 0. as a result, the output buffer is turned off (i/o mode changes to input), the pins are placed in a high impedance state. ? the pdr3 register is not initialized when the cpu is reset. to use the port in output mode, therefore, output mode must be specified in the ddr3 register after the output data is set in the pdr3 register. l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power mode control register (lpmcr) is already 1 when the cpu is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state. this is because the output buffer is turned off forcibly regardless of the value in the ddr3 register. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. table 8.6-4 lists the states of the port 3 pins. table 8.6-4 states of port 3 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time-base timer mode (spl = 0) stop mode or time- base timer mode (spl = 1) p30/rt00~ p37/sot0 general-purpose i/o port general-purpose i/o port general-purpose i/o port input shut down/output in hi-z
200 chapter 8 i/o ports MB90560 series 8.7 port 4 port 4 is a general-purpose i/o port. it can also be used for peripheral function input and output. the port pins can be switched in units of bits between the i/o port and peripheral function. this section focuses on the general i/o port function. it provides the configuration of port 4, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 4 configuration port 4 consists of the following: ? general-purpose i/o pins/peripheral function i/o pins (p40/sck0 to p45/ppg5) ? port 4 data register (pdr4) ? port 4 data direction register (ddr4) n port 4 pins the port 4 i/o pins are also used as peripheral function i/o pins. the pins cannot be used as general-purpose i/o port pins when they are used as peripheral function i/o pins. table 8.7-1 lists the port 4 pins. table 8.7-1 port 4 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function (single-chip mode) peripheral function i/o form circuit type input output port 4 p40/sck0 p40 general- purpose i/o sck0 uart0 serial clock i/o cmos (hysteresis) cmos d p41/ppg0 p41 ppg0 ppg0 output p42/ppg1 p42 ppg1 ppg1 output f p43/ppg2 p43 ppg2 ppg2 output p44/ppg3 p44 ppg3 ppg3 output p45/ppg4 p45 ppg4 ppg4 output p46/ppg5 p46 ppg5 ppg5 output CC C C
MB90560 series chapter 8 i/o ports 201 n block diagram of port 4 pins figure 8.7-1 is a block diagram of port 4 pins. figure 8.7-1 block diagram of port 4 pins when the peripheral function output enable bit is set, the port is forcibly caused to function as peripheral function output pins regardless of the value in the ddr4 register.if valid dtti is input when the rto0 to rto5 outputs and dtti input are enabled, the value set in pdr4 is forcibly output. n port 4 registers port 4 registers are pdr4 and ddr4. the bits making up each register correspond to the port 4 pins on a one-to-one basis. table 8.7-2 lists the port 4 pins and their corresponding register bits. table 8.7-2 port 4 pins and their corresponding register bits port register bits and corresponding port pins port 4 pdr4,ddr4 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin C p46 p45 p44 p43 p42 p41 p40 port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) peripheral input peripheral output peripheral output enable internal data bus
202 chapter 8 i/o ports MB90560 series 8.7 port 4 8.7.1 port 4 registers (pdr4 and ddr4) this section describes the port 4 registers. n functions of port 4 registers l port 4 data register (pdr4) the pdr4 register indicates the state of each pin of port 4. l port 4 data direction register (ddr4) the ddr4 register specifies the direction of a data flow (input or output) at each pin (bit) of port 4. when a ddr4 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. ? when a peripheral function having output pins is used, the port functions as peripheral function output pins regardless of the value in the ddr4 register as long as the peripheral function output enable bit corresponding to the pins is set. ? to use a peripheral function having input pins, reset the ddr4 register bit corresponding to each peripheral function input pin to 0 to place the port in input mode. table 8.7-3 lists the functions of the port 4 registers. table 8.7-3 port 4 register functions r/w : read/write enabled x : undefined C : empty bit register data during reading during writing read/ write address initial value port 4 data register (pdr4) 0 the pin is at the low level. the output latch is loaded with 0. when the pin functions as an output port, the pin is set to the low level. r/w 000004h Cxxxxxxxb 1 the pin is at the high level. the output latch is loaded with 1. when the pin functions as an output port, the pin is set to the high level. port 4 data direction register (ddr4) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000014h C0000000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode.
MB90560 series chapter 8 i/o ports 203 memo
204 chapter 8 i/o ports MB90560 series 8.7 port 4 8.7.2 operation of port 4 this section describes the operation of port 4. n operation of port 4 l port operation in output mode ? setting a bit of the ddr4 register to 1 places the corresponding port pin in output mode. ? data written to the pdr4 register in output mode is stored in the output latch of the pdr and output to the port pins as is. ? the pdr4 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? writing a bit of the ddr4 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? data written to the pdr4 register in input mode is stored in the output latch of the pdr but not output to the port pins. ? the pdr4 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation for peripheral function output the peripheral function output enable bit is set to enable the port to be used for peripheral function output. the state of the peripheral function enable bit takes precedence when specifying a switch between input and output. even if a ddr4 register bit is 0, the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. l port operation for peripheral function input when the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. to use an external signal for the peripheral function, reset the ddr4 register to 0 to place the port in input mode.
MB90560 series chapter 8 i/o ports 205 l port operation after a reset ? when the cpu is reset, the ddr4 register is initialized to 0. as a result, the output buffer is turned off (i/o mode changes to input), the pins are placed in a high impedance state. ? the pdr4 register is not initialized when the cpu is reset. to use the port in output mode, therefore, output mode must be specified in the ddr4 register after the output data is set in the pdr4 register. l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power mode control register (lpmcr) is already 1 when the port is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state. this is because the output buffer is turned off forcibly regardless of the value in the ddr4 register. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. table 8.7-4 lists the states of the port 4 pins. table 8.7-4 states of port 4 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time- base timer mode (spl = 0) stop mode or time- base timer mode (spl = 1) hardware standby mode p40/sin0~p47/ atg general-purpose i/o port general-purpose i/ o port general-purpose i/o port input shut down/ output in hi-z input shut down/output in hi-z
206 chapter 8 i/o ports MB90560 series 8.8 port 5 port 5 is a general-purpose i/o port. it can also be used for a/d converter analog input. the port pins can be switched in units of bits between the i/o port and analog input. this section focuses on the general i/o port function. it provides the configuration of port 5, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 5 configuration port 5 consists of the following: ? general-purpose i/o pins/analog input pins (p50/an0 to p57/an7) ? port 5 data register (pdr5) ? port 5 data direction register (ddr5) ? analog input enable register (ader) n port 5 pins the port 5 i/o pins are also used as analog input pins. the pins cannot be used as general- purpose i/o port pins when they are used for analog input. similarly, the port 5 i/o pins cannot be used for analog input when they are used as a general-purpose i/o port. table 8.8-1 lists the port 5 pins. table 8.8-1 port 5 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function (single-chip mode) peripheral function i/o form circuit type input output port 5 p50/an0 p50 general- purpose i/o an0 analog input 0 cmos (hysteresis) cmos e p51/an1 p51 an1 analog input 1 p52/an2 p52 an2 analog input 2 p53/an3 p53 an3 analog input 3 p54/an4 p54 an4 analog input 4 p55/an5 p55 an5 analog input 5 p56/an6 p56 an6 analog input 6 p57/an7 p57 an7 analog input 7
MB90560 series chapter 8 i/o ports 207 n block diagram of port 5 pins figure 8.8-1 block diagram of port 5 pins for a pin used as an input port, reset the corresponding pdr5 register bit to 0, and also reset the corresponding ader register bit to 0. for an pin used as an analog input pin, reset the corresponding ddr5 register bit to 0 and set the corresponding ader register bit to 1. in this case, the value read from the pdr5 register is 0. n port 5 registers port 5 registers are pdr5, ddr5, and ader. the bits making up each register correspond to the port 5 pins on a one-to-one basis. table 8.8-2 lists the port 5 pins and their corresponding register bits. table 8.8-2 port 5 pins and their corresponding register bits port register bits and corresponding port pins port 5 pdr5,ddr5,ader bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 corresponding pin p57 p56 p55 p54 p53 p52 p51 p50 internal data bus ader pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) analog input
208 chapter 8 i/o ports MB90560 series 8.8 port 5 8.8.1 port 5 registers (pdr5, ddr5, and ader) this section describes the port 5 registers. n functions of port 5 registers l port 5 data register (pdr5) the pdr5 register indicates the state of each pin of port 5. l port 5 data direction register (ddr5) the ddr5 register specifies the direction of a data flow (input or output) at each pin (bit) of port 5. when a ddr5 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. l analog input enable register (ader) each bit of the ader register specifies whether the corresponding port 5 pin is to be used as a general-purpose i/o port or an analog input pin. setting an ader bit to 1 enables the corresponding pin for analog input. setting the bit to 0 enables the pin for general-purpose i/o. if a signal at an intermediate level is input in port i/o mode, input leak current flows. therefore, for a pin used for analog input, be sure to set the corresponding ader bit to 1 for analog input. when the cpu is reset, the ddr5 register is reset to 0 and the ader register is set to 1 for analog input. table 8.8-3 lists the functions of the port 5 registers. table 8.8-3 port 5 register functions r/w : read/write enabled x : undefined register data during reading during writing read/ write address initial value port 5 data register (pdr5) 0 the pin is at the low level. low level is output to the pin. (the output latch is loaded with 0: to turn on the output transistor.) r/w 000005h xxxxxxxb 1 the pin is at the high level. the pin is placed in a high-impedance state. (the output latch is loaded with 1 to turn off the output transistor.) port 5 data direction register (ddr5) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000015h 00000000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode. analog input enable register (ader) 0 port i/o mode r/w 000017h 111 11111b 1 analog input mode
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210 chapter 8 i/o ports MB90560 series 8.8 port 5 8.8.2 operation of port 5 this section describes the operation of port 5. n operation of port 5 l port operation in output mode ? setting a bit of the ddr5 register to 1 places the corresponding port pin in output mode.- data written to the pdr5 register in output mode is held in the output latch of the pdr and output to the port pins. ? the pdr5 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write the output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? writing a bit of the ddr5 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? data written to the pdr5 register in input mode is stored in the output latch of the pdr but not output to the port pins. ? the pdr5 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation for analog input to use a port pin for analog input, write 1 to the corresponding ader bit. doing so disables the port from operating as a general-purpose port pin and enables it to function as an analog input pin. when pdr5 is accessed in read mode in this situation, a value of 0 is read. l port operation after a reset when the cpu is reset, the ddr5 register is initialized to 0 and the ader register is initialized to 1 to place the port in analog input mode. to use the port as a general-purpose port, write 0 to the ader register in advance to place the port in port i/o mode. l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power mode control register (lpmcr) is already 1 when the cpu is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state. this is because the output buffer is turned off forcibly. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. table 8.8-4 lists the states of the port 5 pins.
MB90560 series chapter 8 i/o ports 211 table 8.8-4 states of port 5 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time-base timer mode (spl = 0) stop mode or time- base timer mode (spl = 1) p50/an0~p57/an7 general-purpose i/o port general-purpose i/o port general-purpose i/o port input shut down/output in hi-z
212 chapter 8 i/o ports MB90560 series 8.9 port 6 port 6 is a general-purpose i/o port. it can also be used for peripheral function input and output. the port pins can be switched in units of bits between the i/o port and peripheral function. this section focuses on the general i/o port function. it provides the configuration of port 6, lists its pins, shows a block diagram of the pins, and describes the corresponding registers. n port 6 configuration port 6 consists of the following: ? general-purpose i/o pins/peripheral function i/o pins (p60/sin1 to p62/sck1) ? port 6 data register (pdr6) ? port 6 data direction register (ddr6) n port 6 pins the port 6 i/o pins are also used as peripheral function i/o pins. the pins cannot be used as general-purpose i/o port pins when they are used as peripheral function i/o pins. table 8.9-1 lists the port 6 pins. table 8.9-1 port 6 pins see section 1.7, "i/o circuit types," for information on the circuit types. port pin port function (single-chip mode) peripheral function i/o form circuit type input output port 6 p60/sin1 p60 general- purpose i/o sin1 uart1 data input cmos (hysteresis) cmos d p61/sot1 p61 sot1 uart1 data output p62/sck1 p62 sck1 uart1 serial clock i/o p63/int7/ dtti p63 int7 external interrupt input/ dtti input CC C C CC C C CC C C CC C C
MB90560 series chapter 8 i/o ports 213 n block diagram of port 6 pins figure 8.9-1 is a block diagram of port 6 pins. figure 8.9-1 block diagram of port 6 pins n port 6 registers port 6 registers are pdr6 and ddr6. the bits making up each register correspond to the port 6 pins on a one-to-one basis. table 8.9-2 lists the port 6 pins and their corresponding register bits. table 8.9-2 port 6 pins and their corresponding register bits port register bits and corresponding port pins port 6 pdr6,ddr6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 corresponding pin C C C C p63 p62 p61 p60 internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) peripheral input peripheral output peripheral output enable
214 chapter 8 i/o ports MB90560 series 8.9 port 6 8.9.1 port 6 registers (pdr6 and ddr6) this section describes the port 6 registers. n functions of port 6 registers l port 6 data register (pdr6) the pdr6 register indicates the state of each pin of port 6. l port 6 data direction register (ddr6) the ddr6 register specifies the direction of a data flow (input or output) at each pin (bit) of port 6. when a ddr6 register bit is 1, the corresponding port (pin) is set as an output port. when the bit is 0, the port (pin) is set as an input port. check: to use a peripheral function having input pins, reset the ddr6 register bit corresponding to each peripheral function input pin to 0 to place the port in input mode. table 8.9-3 lists the functions of the port 6 registers. table 8.9-3 port 6 register functions r/w : read/write enabled x : undefined C : empty bit register data during reading during writing read/ write address initial value port 6 data register (pdr6) 0 the pin is at the low level. the output latch is loaded with 0. when the pin functions as an output port, the pin is set to the low level. r/w 000006h ----xxxxb 1 the pin is at the high level. the output latch is loaded with 1. when the pin functions as an output port, the pin is set to the high level. port 6 data direction register (ddr6) 0 the direction latch is 0. the output buffer is turned off to place the port in input mode. r/w 000016h ----0000b 1 the direction latch is 1. the output buffer is turned on to place the port in output mode.
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216 chapter 8 i/o ports MB90560 series 8.9 port 6 8.9.2 operation of port 6 this section describes the operation of port 6. n operation of port 6 l port operation in output mode ? setting a bit of the ddr6 register to 1 places the corresponding port pin in output mode. ? data written to the pdr6 register in output mode is stored in the output latch of the pdr and output to the port pins as is. ? the pdr6 register can be accessed in read mode to read the value at the port pins (the same value as in the output latch of the pdr). if a read-modify-write instruction (such as an instruction that sets bits) is used with the port data register, the target bits of the register are set to the specified value. the bits that have been specified for output using the ddr register are not affected, but for the bits that have been specified for input, a value input from the pins is written to the output latch and output as it is. before switching the mode for the bits from input to output, therefore, write the output data to the pdr register, then specify output mode in the ddr register. l port operation in input mode ? resetting a bit of the ddr6 register to 0 places the corresponding port pin in input mode. ? in input mode, the output buffer is turned off, and the pins are placed in a high impedance state. ? data written to the pdr6 register in input mode is held in the output latch of the pdr but not output to the port pins. ? the pdr6 register can be accessed in read mode to read the level value (0 or 1) at the port pins. l port operation for peripheral function output the peripheral function output enable bit is set to enable the port to be used for peripheral function output. the state of the peripheral function enable bit takes precedence when specifying a switch between input and output. even if a ddr6 register bit is 0, the corresponding port pin is used for peripheral function output if the peripheral function has been enabled for output. because the value at the pins can be read even if peripheral function output is enabled, the peripheral function output value can be read. l port operation for peripheral function input when the port is also used for peripheral function input, the value at the pins is always supplied as peripheral function inputs. to use an external signal for the peripheral function, reset the ddr6 register to 0 to place the port in input mode.
MB90560 series chapter 8 i/o ports 217 l port operation after a reset ? when the cpu is reset, the ddr6 register is initialized to 0. as a result, the output buffer is turned off (i/o mode changes to input), the pins are placed in a high impedance state. ? the pdr6 register is not initialized when the cpu is reset. to use the port in output mode, therefore, output mode must be specified in the ddr6 register after output data is set in the pdr6 register. l port operation in stop or time-base timer mode if the pin state setting bit (spl) in the low-power mode control register (lpmcr) is already 1 when the port is shifted to stop or time-base timer mode, the port pins are placed in a high- impedance state. this is because the output buffer is turned off forcibly regardless of the value in the ddr6 register. note that the inputs are fixed at a certain level to prevent leakage due to an open circuit. table 8.9-4 lists the states of the port 6 pins. table 8.9-4 states of port 6 pins spl : pin state setting bit of low-power mode control register (lpmcr) hi-z : high impedance pin normal operation sleep mode stop mode or time- base timer mode (spl = 0) stop mode or time- base timer mode (spl = 1) p60/sin1~ p63/int7/dtti general-purpose i/o port general-purpose i/o port general-purpose i/o port input shut down/output in hi-z
218 chapter 8 i/o ports MB90560 series 8.10 sample i/o port program this section provides a sample program using i/o port pins. n sample i/o port program l processing specifications ? ports 0 and 1 are used to turn on all segments of a seven-segment (eight-segment if the decimal point is included) led. ? pin p00 corresponds to the anode common pin of the led, and pins p10 to p17 correspond to the segment pins. figure 8.10-1 is an example of connecting the eight-segment led to the MB90560 ports. figure 8.10-1 example of eight-segment led connection l coding example pdr0 equ 000000h pdr1 equ 000001h ddr0 equ 000010h ddr1 equ 000011h ;-----------------------------main program------------------------------------------------------------------------------------- ----------- -------------- code cseg start: ; initialization mov i:pdr0, #00000000b ; puts p00 at a low level (#xxxxxxx0b). mov i:ddr0, #11111111b ; puts all port 0 bits in output m ode. mov i:pdr1, # 11111111b ; sets all port 1 bits to 1. mov i:ddr1, #11111111b ; puts all port 1 bits in output m ode. code ends ; ----------------------------------------------------------------------------------------------------------------------------- -------------------- -------------- end start MB90560 p00 p17 p16 p15 p14 p13 p12 p11 p10
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chapter 9 timebase timer this chapter describes the functions and operation of the timebase timer. 9.1 overview of the timebase timer ................................................... 222 9.2 configuration of the timebase timer ............................................. 224 9.3 timebase timer control register (tbtc)...................................... 226 9.4 timebase timer interrupts ............................................................. 228 9.5 operation of the timebase timer................................................... 230 9.6 usage notes on the timebase timer............................................. 232 9.7 sample program for the timebase timer program ....................... 234
222 chapter 9 timebase timer MB90560 series 9.1 overview of the timebase timer the timebase timer is an 18-bit free-run counter (timebase counter) that counts up in synchronization with the internal count clock (one-half of the source oscillation). the timer has an interval timer function that can select four intervals. the timebase timer also has functions for timer output of the oscillation stabilization wait interval and for supplying the clocks for the watchdog timer. n interval timer function the interval timer function repeatedly generates an interrupt request at a given interval. ? an interrupt request is generated when the interval timer bit for the timebase counter overflows. ? four types of the interval timer (interval) can be selected. table 9.1-1 lists the intervals for the timebase timer. table 9.1-1 intervals for the timebase timer hclk: oscillation clock values in parentheses are for a 4 mhz oscillation clock. internal count clock cycle interval cycle 2/hclk (0.5 s) 2 12 /hclk (approx. 1.0 ms) 2 14 /hclk (approx. 4.1 ms) 2 16 /hclk (approx. 16.4 ms) 2 19 /hclk (approx. 131.1 ms)
MB90560 series chapter 9 timebase timer 223 n clock supply function the clock supply function supplies clocks to the oscillation stabilization wait interval timer and to some peripheral functions. table 9.1-2 lists the cycle times of clocks supplied from the timebase timer to each peripheral. table 9.1-2 clock cycle time supplied from the timebase timer hclk: oscillation clock values in parentheses occurs during operation of the 4 mhz oscillation clock. the oscillation stabilization wait interval is the yardstick because the oscillation cycle time is unstable as soon as oscillation starts. clock destination clock cycle time remarks oscillation stabilization wait interval 2 13 /hclk (approx. 2.0 ms) oscillation settling time for ceramic vibrator 2 15 /hclk (approx. 8.2 ms) oscillation settling time for crystal vibrator 2 17 /hclk (approx. 32.8 ms) watchdog timer 2 12 /hclk (approx. 1.0 ms) count-up clock for watchdog timer 2 14 /hclk (approx. 4.1 ms) 2 16 /hclk (approx. 16.4 ms) 2 19 /hclk (approx. 131.1 ms) ppg timer 2 9 /hclk (approx. 128 m s) -
224 chapter 9 timebase timer MB90560 series 9.2 configuration of the timebase timer the timebase timer consists of the following four blocks: ? timebase timer counter ? counter clear circuit ? interval timer selector ? timebase timer control register (tbtc) n block diagram of the timebase timer figure 9.2-1 shows the block diagram of the timebase timer. figure 9.2-1 block diagram of the timebase timer t o the ppg timer to the watchdog timebase timer counter to the oscillation stabilization power-on reset stop mode start counter clear interval timer tbof set tbof clear timebase timer control register timebase timer interrupt signal timer wait interval selector in the clock control section ckscr: mcs = 1 ? 0 (*1) circuit selector (tbtc) #34 (22 h ) (*2) of: overflow hclk: oscillation clock *1 switching of the machine clock from the oscillation clock to the pll clock hclk/2
MB90560 series chapter 9 timebase timer 225 l timebase timer counter this 18-bit up counter uses the divide-by-two clock of the oscillation clock (hclk) as the count clock. l counter clear circuit used to clear the counter by writing 0 to the tbtc tbr bit, by a power-on reset, or by transition to stop mode (lpmcr:stp = 1). l interval timer selector selects one of four outputs of the timebase timer counter. an overflow of the selected bit becomes an interrupt cause. l timebase timer control register (tbtc) selects the interval, clears the counter, controls an interrupt request, and checks the status.
226 chapter 9 timebase timer MB90560 series 9.3 timebase timer control register (tbtc) the timebase timer control register (tbtc) selects the interval, clears the counter, controls interrupts, and checks the status. n timebase timer control register (tbtc) figure 9.3-1 timebase timer control register (tbtc) address 0000a9 h initial value 1- - 00100 b resv tbie tbof tbr tbc1 tbc0 tbc1 tbr tbof tbie resv timebase timer initialization bit reserved bit interrupt request enable bit interrupt request flag bit during reading during writing during reading during writing 0 0- 02 12 /hclk (approx. 1.0 ms) 2 14 /hclk (approx. 4.1 ms) clearing of the timebase timer counter and tbof bit no change, no effect on other bits. the read value is always "1". interrupt request output disabled interrupt request output enabled clearing of this bit no overflow from the specified bit no change, no effect on other bits. overflow from the specified bit be sure to write "1" to this bit. values in parentheses are for a 4 mhz oscillation clock. 2 16 /hclk (approx. 16.4 ms) 2 19 /hclk (approx. 131 ms) 01 1 1 0 0 1 1 0 11 tbc0 interval selection bit (wdtc) -- bit15 r/w r/w r/w w r/w r/w bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 r/w : read/write w : write only - : not used x : undefined : initial value
MB90560 series chapter 9 timebase timer 227 table 9.3-1 function description of each bit in the timebase timer control register (tbtc) bit name function bit15 resv: reserved bit be sure to write 1 to this bit. bit14 bit13 not used when read, the value is undefined. writing has no effect on operation. bit12 tbie: interrupt request enable bit used to enable or disable the output of an interrupt request to the cpu. when this bit and the interrupt request flag bit (tbof) are 1, an interrupt request is output. bit11 tbof: interrupt request flag bit this bit is set to 1 when the bit specifying the timebase timer counter overflows. when this bit and the interrupt request enable bit (tbie) are 1, an interrupt request is output. during writing, this bit is cleared with 0. if 1 is written, the bit does not change and there is no effect. to clear the tbof bit, disable the timebase timer interrupt by specifying the tbie bit or processor status (ps) ilm bit. the tbof bit is cleared by writing 0, by a transition to stop mode, by clearing of the timebase timer with the tbr bit, or by a reset. bit10 tbr: timebase timer initial- ization bit used to clear the timebase timer counter. when 0 is written to this bit, the counter is cleared and the tbof bit is cleared. if 1 is written, the bit does not change and there is no effect. the read value is always 1. bit9 bit8 tbc1, tbc0: interval selection bit used to select an interval timer cycle. the bit for the interval timer of the timebase timer counter is specified. four types of interval can be selected.
228 chapter 9 timebase timer MB90560 series 9.4 timebase timer interrupts the timebase timer can generate an interrupt request when the bit specifying the timebase timer counter overflows. (interval timer function) n timebase timer interrupts the interrupt request flag bit (tbtc:tbof) is set to 1 when the timebase timer counter counts up with the internal count clock and when the bit for the selected interval timer bit overflows. if the interrupt request enable bit has been enabled (tbtc:tbie = 1), an interrupt request (#36) is generated in the cpu. writing 0 to the tbof bit in the interrupt handling routine clears the interrupt request. when the specified bit overflows, the tbof bit is set regardless of the tbie bit value. clear the interrupt request flag bit (tbtc:tbof) while a timebase timer interrupt is disabled by setting the tbie bit or the processor status (ps) ilm bit. reference ? when the tbof bit is 1, if the tbie bit status is switched from disable to enable (0 ? 1), an interrupt request occurs immediately. ? the timebase timer cannot use the extended intelligent i/o service (ei 2 os). n timebase timer interrupts and ei 2 os table 9.4-1 lists the timebase timer interrupt and ei2os. table 9.4-1 timebase interrupts and ei 2 os x: not available icr12 is common to the timebase timer interrupt and input capture ch 2/3 wake-up interrupt. interrupts can be used for two applications, but the interrupt level is the same. interrupt number interrupt level setting register vector table address ei 2 os register name address lower upper bank #36 (24 h ) icr12 0000bc h ffff6c h ffff6d h ffff6e h x
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230 chapter 9 timebase timer MB90560 series 9.5 operation of the timebase timer the timebase timer provides the interval timer function and the clock supply function that supplies clocks to some peripheral functions. n operation of the interval timer function (timebase timer) the interval timer function generates an interrupt request for each interval the setting in figure 9.5-1 is required for timebase timer to operate as an interval timer. figure 9.5-1 setting of the timebase timer ? the timebase timer counter continues counting up in synchronization with the internal count clock (one-half of the oscillation clock) as long as the clock is being oscillated. ? when the counter is cleared (tbr = 0), it counts up from 0. when the interval timer bit overflows, the interrupt request flag bit (tbof) is set to 1. if interrupt request output has been enabled (tbie = 1), an interrupt is generated for each selected interval based on the cleared time. ? the interval may become longer than the time set because of timebase timer clearing. n oscillation stabilization wait interval timer function the timebase timer is also used as the oscillation stabilization wait interval timer for oscillation and the pll clocks. the oscillation settling time is set for the interval from the time the counter counts up from 0 (count clear) until the oscillation stabilization wait interval bit overflows. when control returns from timebase timer mode to pll clock mode, the oscillation stabilization wait interval starts from the middle of counting because the timebase timer counter has been not cleared. table 9.5-1 shows the clearing of the timebase counter and the oscillation settling times. : used : set "0" : set "1"
MB90560 series chapter 9 timebase timer 231 table 9.5-1 timebase timer counter clearing and oscillation stabilization wait intervals o: available x: not available n clock supply function the timebase timer supplies clocks to the watchdog timer. clearing of the timebase counter affects operation of the watchdog timer. operation counter clear tbof clear oscillation stabilization wait interval tbtc: writing of 0 to tbr o o power-on reset oo oscillation clock oscillation stabilization wait interval watchdog reset releasing of stop mode o o oscillation clock oscillation stabilization wait interval (at return to main clock mode) transition from oscillation clock mode to pll clock mode (mcs = 1 ? 0) o o pll clock oscillation stabilization wait interval releasing of timebase timer mode xx pll clock oscillation stabilization wait interval (at return to pll clock mode) releasing of sleep mode x x -
232 chapter 9 timebase timer MB90560 series 9.6 usage notes on the timebase timer notes about the effects on peripheral functions of clearing interrupt requests and the timebase timer are given below. n timebase timer usage notes l clearing interrupt requests the tbof bit of the timebase timer control register must be cleared while a timebase timer interrupt is masked by the tbie bit or the interrupt level mask register (ilm) of the processor status (ps). l effects of timebase timer clearing clearing of the timebase timer counter affects the following operations: ? when the timebase timer is using the interval timer function (interval interrupt) ? when the watchdog timer is being used l use of the timebase timer as the oscillation settling time timer at power-on, the source oscillation of the main clock stops in main stop mode. after oscillator operation starts, the operating clock supplied by the timebase timer is used to take the oscillation stabilization wait time of the main clock. an appropriate oscillation stabilization wait time must be selected based on the type of oscillating element connected to the main clock oscillator (clock generation section). see section 4.5, "oscillation stabilization wait time," for details. l notes on peripheral functions to which clocks are supplied from the timebase timer in the mode in which the main clock source oscillation stops, the counter is cleared and timebase timer operation stops. when the timebase timer counter is cleared, the clock supplied from the timebase timer is supplied from its initial state. as a result, the h level is shortened and the l level lengthened 1/2 cycle. although the clock for the watchdog timer is also supplied from its initial state; the watchdog timer operates in normal cycles because the watchdog timer counter is cleared at the same time. figure 9.6-1 effect on ppg when clearing timebase timer counter value 00fff h 00800 h 00000 h clock supplied to ppg ppg can be operated by supplying count clock from the timebase timer (divide-by-512 source oscillation) clearing the counter by the program (tbtc: tbr = 0)
MB90560 series chapter 9 timebase timer 233 n operation of the timebase timer the following operations are shown in figure 9.6-2: ? a power-on reset occurs. ? sleep mode is entered during operation of the interval timer function. ? a counter clear request is issued. when stop mode is entered, the timebase timer is cleared and its operation stops. on return from stop mode, the timebase timer counts the oscillation settling time. figure 9.6-2 timebase timer operations counter value clearing by transition oscillation settling start of cpu to stop mode overflow operation interval cycle (tbtc: tbc1, tbc0 = 11 h ) counter clearing (tbtc: tbr = 0) power-on reset (option) clearing by the interrupt handling routine sleep stop tbof bit tbie bit slp bit (lpmc register) releasing of interval stp bit (lpmcr register) interrupt sleep releasing of stop by an external interrupt when 11 b has been set in the interval selection bit (tbtc:tbc1,tbc0) of the timebase timer control register : indicates the oscillation settling time.
234 chapter 9 timebase timer MB90560 series 9.7 sample program for the timebase timer program this section contains a sample program for the timebase timer. n sample program for the timebase timer l processing an interval interrupt of 2 12 /hclk (hclk: oscillation clock) is repeatedly generated. the interval becomes approx. 1.0 ms (during 4 mhz operation). l coding example icr12 equ 0000bch ; timebase timer interrupt control register tbtc equ 0000a9h ; timebase timer control register tbof equ tbtc:3 ; interrupt request flag bit ;-------main program------------------------------------------------------------------------------------------------ codecseg start: ; : ; assumes that stack pointer (sp) has already been ; initialized. and ccr,#0bfh ; disables interrupts. mov i:icr12 #00h ; interrupt level 0 (highest) mov i:tbtc,#10010000b ; fixes upper 3 bits. ; enables interrupts and clears tbof. ; clears counter. ; selects interval 2 12 /hclk mov ilm,#07h ; sets ps ilm to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h bra loop ;-------interrupt program--------------------------------------------------------------------------------------------- wari: clrb i:tbof ; clears interrupt request flag. ; : ; user handling ; : reti ; ; returns from interrupt. code ends ;-------vector setting--------------------------------------------------------------------------------------------- vect cseg abs=0ffh org 0ff6ch ; sets vector for interrupt #36 (24 h ). dsl wari org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
MB90560 series chapter 9 timebase timer 235 memo

chapter 10 watchdog timer this chapter describes the functions and operation of the watchdog timer. 10.1 overview of the watchdog timer ................................................. 238 10.2 configuration of the watchdog timer ........................................... 239 10.3 watchdog timer control register (wdtc) .................................. 240 10.4 operation of the watchdog timer................................................. 242 10.5 usage notes on the watchdog timer........................................... 244 10.6 sample program for the watchdog timer .................................... 245
238 chapter 10 watchdog timer MB90560 series 10.1 overview of the watchdog timer the watchdog timer is a 2-bit counter that uses the timebase timer supply clock as the count clock. after activation, if the watchdog timer is not cleared within a given time, the cpu is reset. n watchdog timer function the watchdog timer is a counter for handling program crashes. once the watchdog timer is activated, it must be regularly cleared within a given time. if the program results in an endless loop and the watchdog timer is not cleared over a given time, a watchdog reset is generated for the cpu. table 10.1-1 lists the watchdog timer intervals. if the watchdog timer is not cleared, a watchdog reset is generated between the minimum time and maximum time. clear the counter within the minimum time listed in this table. table 10.1-1 intervals for the watchdog timer *1 value during operation of the 4 mhz oscillation clock the maximum and minimum watchdog timer intervals and the oscillation clock cycle count depend on the clear timing. the interval is 3.5 to 4.5 times longer than the cycle of the count clock (timebase timer supply clock). see section 11.4, "operation of the watchdog timer." the watchdog counter consists of a 2-bit counter that uses the carry signals of the timebase timer as count clocks. therefore, if the timebase timer is cleared, the watchdog reset generation time may become longer than the time set. at activation, the watchdog timer is initialized by a power-on or watchdog reset, and is placed in stopped status. the watchdog timer is cleared by an external pin reset, software reset, writing to the wte bit (watchdog timer control register), sleep mode, transition to stop mode, or the hold acknowledge signal. it is not stopped, however. interval minimum (*1) maximum (*1) oscillation clock cycle count approx. 3.58 ms approx. 4.61 ms 2 14 2 11 cycle approx. 14.33 ms approx. 18.3 ms 2 16 2 13 cycle approx. 57.23 ms approx. 73.73 ms 2 18 2 15 cycle approx. 458.75 ms approx. 589.82 ms 2 21 2 18 cycle
MB90560 series chapter 10 watchdog timer 239 10.2 configuration of the watchdog timer the watchdog timer consists of the following five blocks: ? count clock selector ? watchdog counter (2-bit counter) ? watchdog reset generator ? counter clear control circuit ? watchdog timer control register (wdtc) n block diagram of the watchdog timer figure 10.2-1 shows the block diagram of the watchdog timer. figure 10.2-1 block diagram of the watchdog timer l count clock selector this circuit is used to select the count clock of the watchdog timer from four types of timebase timer outputs. this determines the watchdog reset generation time. l watchdog counter (2-bit counter) this 2-bit up counter uses the timebase timer output as the count clock. l watchdog reset generator used to generate the reset signal by an overflow of the watchdog counter. l counter clear circuit used to clear the watchdog counter and to control the operation or stopping of the counter. l watchdog timer control register (wdtc) used to activate or clear the watchdog timer; holds the reset generation cause. watchdog timer control register (wdtc) watchdog timer start of sleep mode start of hold status mode start of stop mode counter clear control circuit count clock selector activation 2-bit over- watchdog to the internal with clr counter reset generator reset generator flow clear (timebase timer counter) one-half of hclk hclk: oscillation clock
240 chapter 10 watchdog timer MB90560 series 10.3 watchdog timer control register (wdtc) the watchdog timer control register (wdtc) activates and clears the watchdog timer, and displays the reset cause. n watchdog timer control register (wdtc) figure 10.3-1 shows the watchdog timer control register (wdtc); table 11.3-1 describes the function of each bit of the watchdog timer control register (wdtc). figure 10.3-1 watchdog timer control register (wdtc) the interval becomes 3.5 to 4.5 times longer than the count clock (timebase timer output value) cycle. for details, see section 11.4, "operation of the watchdog timer." address 0000a8 h initial value xxxxx111 b ponr wrst erst srst wte wt1 wt0 (tbtc) wt1 wt0 interval selection bit (for 4 mhz hclk) interval minimum maximum oscillation clock cycle count 0 0 0 approx. 3.58 ms approx. 4.61 ms power-on watchdog timer external pin (rstx input) rst bit (software reset) 2 14 2 11 cycle 2 16 2 13 cycle 2 18 2 15 cycle 2 21 2 18 cycle approx. 14.33 ms hclk: oscillation clock approx. 18.3 ms approx. 57.23 ms approx. 73.73 ms approx. 458.75 ms approx. 589.82 ms 1 1 0 1 1 wte 0 - activation of the watchdog timer (at first write after reset) - clearing of the watchdog timer (at second or subsequent write after reset) no operation 1 watchdog control bit bit15 r r r r w w w bit8 bit6 bit7 bit5 bit4 bit3 bit2 bit1 bit0 ponr ** 1* *1 1--- * * * 1 * * wrst erst srst reset cause bit reset cause r: read only w: write only x: undefined - : the contents of the bit are not guaranteed. *: retains the previous status. : initial value
MB90560 series chapter 10 watchdog timer 241 table 10.3-1 function description of each bit of the watchdog timer control register (wdtc) bit name function bit7 bit5 bit4 bit3 ponr, wrst, erst, srst: reset cause bits read-only bits for indicating the reset cause. if more than one reset cause occurs, the bit for each reset cause occurring is set to 1. these bits are all cleared to 0 after the watchdog timer control register (wdtc) is read. at power-on, the contents of the bits other than the ponr bit are not guaranteed. therefore, when the ponr bit is 1, ignore the contents of the bits other than the ponr bit. bit2 wte: watchdog timer con- trol bit when 0 is written to this bit, the watchdog timer is activated (first write after reset) or the 2-bit counter is cleared (second or subsequent write after reset). writing 1 does not affect operation. bit1 bit0 wt1, wt0: interval selection bit used to select the watchdog timer interval. only data at watchdog timer activation is valid. data written after watchdog timer activation is ignored. these bits are write-only.
242 chapter 10 watchdog timer MB90560 series 10.4 operation of the watchdog timer the watchdog timer generates a watchdog reset by an overflow of the watchdog counter. n watchdog timer operation operation of the watchdog timer requires the setting in figure 11.4-1. figure 10.4-1 setting of the watchdog timer l activating the watchdog timer ? the watchdog timer is activated when the first 0 after reset is written to the wte bit of the watchdog timer control register (wdtc). specify the interval by specifying the wt1 and wt0 bits of the watchdog timer control register at the same time. ? when watchdog timer activation starts, it can be stopped only by a power-on, or its own reset. l clearing the watchdog timer ? when a second or subsequent 0 is written to the wte bit, the 2-bit counter of the watchdog timer is cleared. if the counter is not cleared within the time interval, it overflows and a watchdog reset occurs. ? the watchdog counter is cleared by reset generation, sleep mode, stop mode, transition to clock mode, or detection of the hold acknowledge signal. ? in clock mode, the watchdog timer counter is cleared and stops. l intervals for the watchdog timer figure 11.4-2 shows the relationship between the clear timing of the watchdog timer and intervals. the interval changes according to the clear timing of the watchdog timer and requires 3.5 to 4.5 times longer than the count clock cycle. l checking a reset cause a reset cause can be determined by checking the ponr, wrst, erst, and srst bits of the watchdog timer control register (wdtc) after a reset. : used : set 0.
MB90560 series chapter 10 watchdog timer 243 figure 10.4-2 clear timing and watchdog timer intervals [wdg timer block diagram] 2-bit counter clock wte bit count enable divide-by- reset reset signal selector two circuit circuit count enabling and clearing output circuit divide-by- two circuit [minimum interval] when the wte bit is cleared immediately before the count clock rises: count start counter clearing count clock a divide-by-two value b divide-by-two value c count enabling 7 x (count clock cycle/2) wte bit clearing watchdog reset generation reset signal d 9 x (count clock cycle/2) reset signal wte bit clearing watchdog reset generation [maximum interval] when the wte bit is cleared immediately after the count clock rises: count start counter clearing count clock a divide-by-two value b divide-by-two value c count enabling
244 chapter 10 watchdog timer MB90560 series 10.5 usage notes on the watchdog timer notes on using the watchdog timer are given below. n usage notes on the watchdog timer l stopping the watchdog timer once the watchdog timer is activated, it cannot stop until a power-on or watchdog reset occurs. the watchdog timer counter is cleared by software reset; however, the watchdog timer does not stop. l intervals since a carry signal of the timebase timer is used as the count clock for the interval, the watchdog timer interval may become longer than the setting time when the timebase timer is cleared. l selecting the interval the interval can be set when the watchdog timer is activated. data written during operations other than activation is ignored. l notes on program creation when a program that repeatedly clears the watchdog timer in the main loop is created, the processing time of the main loop including the interrupt processing must be equal to or less than the minimum watchdog timer interval. l watchdog timer operation in timebase timer mode the timebase timer operates while the timebase timer mode is set. the watchdog timer, however, is temporarily stopped.
MB90560 series chapter 10 watchdog timer 245 10.6 sample program for the watchdog timer this section contains a sample program for the watchdog timer. n sample program for the watchdog timer l processing ? the watchdog timer is cleared every time in the main program loop. ? the main loop must make one iteration within the minimum watchdog timer interval. l coding example wdtc equ 0000a8h ; watchdog timer control register wte equ wdtc:2 ; watchdog control bit ;-------main program------------------------------------------------------------------------------------------------------ code cseg start: ; : ; assumes that stack pointer (sp) has already been wdg_start: mov wdtc,#00000011b ; activates watchdog timer. ; selects the interval 2 21 2 18 cycle. ;--------main loop---------------------------------------------------------------------------------------------------------- main: clrb i:wte ; clears watchdog timer. ; : clears two bits regularly. ; user processing ; : jmp main ; loops in less time than the watchdog timer interval. code ends ;--------vector setting----------------------------------------------------------------------------------------------------- vect cseg abs=0ffh org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start

chapter 11 16-bit reload timer the chapter describes the functions and operation of the 16-bit reload timer. 11.1 overview of the 16-bit reload timer............................................ 248 11.2 configuration of the 16-bit reload timer ..................................... 252 11.3 16-bit reload timer pins.............................................................. 254 11.4 16-bit reload timer registers...................................................... 255 11.5 16-bit reload timer interrupts...................................................... 262 11.6 operation of the 16-bit reload timer ........................................... 264 11.7 usage notes on the 16-bit reload timer ..................................... 272 11.8 sample programs for the 16-bit reload timer............................. 273
248 chapter 11 16-bit reload timer MB90560 series 11.1 overview of the 16-bit reload timer the 16-bit reload timer is synchronized with three types of internal clocks for counting down in internal clock mode, and it counts down by detecting an optional edge input to the external pin in event counter mode. this timer defines that an underflow condition results when the counter value changes from 0000 h to ffff h . thus, an underflow will occur after an interval of [reload register setting value + 1] counts. either of two modes can be selected for counting. in reload mode, the value set for the count is reloaded to repeat counting for an underflow. in single-shot mode, the counting is stopped with an underflow. the counter underflow allows the occurrence of an interrupt and coordination with the extended intelligent i/o service (ei 2 os). the MB90560 series 16-bit reload timer has two built-in channels. n 16-bit reload timer operating modes table 11.1-1 lists the operating modes of the 16-bit reload timer. table 11.1-1 16-bit reload timer operating modes n internal clock mode internal clock mode allows selection of one of three types of internal clock for the following operations: l software trigger operation when 1 is written to the trg bit of the timer control status register (tmcsr), counting starts. trigger input by the trg bit is always valid for external trigger input as well as for external gate input. l external trigger operation when selected edges (rising, falling, and both edges) are input to the tin0 and tin1 pins, counting starts. l external gate input operation while the selected signal level (l or h) is being input to tin0 and tin1 pins, counting continues. clock mode counter operation operation of 16-bit reload timer internal clock mode reload mode software trigger operation external trigger operation external gate input operation one-shot mode event count mode (external clock mode) reload mode software trigger operation one-shot mode
MB90560 series chapter 11 16-bit reload timer 249 n event count mode (external clock mode) when selected valid edges (rising, falling, and both edges) are input to tin0 and tin1 pins, the timer counts down at these edges. when an external clock with a constant period is used, this timer can also be used as an interval timer. n counter operation l reload mode when an underflow (from 0000 h to ffff h ) occurs during counting down, the count setting value is reloaded to continue counting. since the 16-bit reload timer causes an interrupt request to occur for an underflow condition, it can be used as an interval timer. a toggle waveform inverted at each underflow can also be output from to0 and to1 pins. table 11.1-2 lists the intervals for the 16-bit reload timer. table 11.1-2 intervals for the 16-bit reload timer f : machine clock values in parentheses are for a 16 mhz machine clock. l single-shot mode when an underflow (from 0000 h to ffff h ) occurs during counting down, counting stops, causing an interrupt to occur for the underflow condition. during counter operation, a rectangular waveform that indicates when the count is in progress can be output from the to0 and to1 pins. reference ? 16-bit reload timer 0 can be used to create the baud rate of uart0/uart1. ? 16-bit reload timer 1 can be used as the start trigger of the a/d converter. count clock count clock period interval internal clock 2 1 / f (0.125 s) 0.125 s to 8.192 ms 2 3 / f (0.5 s) 0.5 s to 32.768 ms 2 5 / f (2.0 s) 2.0 s to 131.1 ms external clock 2 3 / f or more (0.5 s) 0.5 s or more
250 chapter 11 16-bit reload timer MB90560 series n 16-bit reload timer interrupts and ei 2 os table 11.1-3 lists 16-bit reload timer interrupts and ei2os. table 11.1-3 16-bit reload timer interrupts and ei 2 os d : available when icr09/icr10 or the interrupt causes sharing the interrupt vector are not used. *1 the same interrupt number is used for 8-bit timer counter underflow and 16-bit reload timer 0. *2 the same interrupt number is used for 16-bit free-running timer underflow and 16-bit reload timer 1. channel interrupt number interrupt control register vector table address ei 2 os register name address lower upper bank 16-bit reload timer 0 (*1) #30 (1e h ) icr09 0000b9 h ffff84 h ffff85 h ffff86 h d 16-bit reload timer 1 (*2) #32 (20 h ) icr10 0000ba h ffff7c h ffff7d h fff7e h
MB90560 series chapter 11 16-bit reload timer 251 memo
252 chapter 11 16-bit reload timer MB90560 series 11.2 configuration of the 16-bit reload timer 16-bit reload timers 0 and 1 each consist of the following seven blocks: ? count clock generation circuit ? reload control circuit ? output control circuit ? operation control circuit ? 16-bit timer register (tmr) ? 16-bit reload register (tmrlr) ? timer control status register (tmcsr) n block diagram of the 16-bit reload timer figure 11.2-1 shows the block diagram of the 16-bit reload timer. figure 11.2-1 block diagram of the 16-bit reload timer internal data bus 16-bit reload register reload signal reload con- trol circuit 16-bit timer register (down counter) count clock generation circuit machine clock pre- scaler clear gate input valid clock judgment circuit wait signal internal clock pin input control circuit external clock clock selector select signal invert output control circuit output signal generation circuit to uart0 and uart1 (*1) pin function selection operation control circuit timer control status register (tmcsr0)(*1) interrupt request signal #30 (1eh)(*2) <#32 (20h)> *1 this register includes channel 0 and channel 1. the register enclosed in < and > indicates the channel 1 register. *2 interrupt number p20/to0(*1)
MB90560 series chapter 11 16-bit reload timer 253 l count clock generation circuit this circuit generates the count clock for the 16-bit reload timer from the machine clock or external input clock. l reload control circuit this circuit controls the reload operation when the timer is started and when an underflow occurs. l output control circuit this circuit controls the inversion of the to pin output by an underflow of the 16-bit timer register and enabling and disabling of to pin output. l operation control circuit this circuit controls starting and stopping of the 16-bit reload timer. l 16-bit timer register (tmr) this register is a 16-bit down counter. the current counter value is read from this register during a read operation. l 16-bit reload register (tmrlr) the interval for the 16-bit reload timer is set in this register. the setting value of this register is loaded into the 16-bit timer register and decremented. l timer control status register (tmcsr) this register selects the count clock of the 16-bit reload timer and the operating mode, sets operating conditions, starts a trigger with software, enables or disables counting, selects reload or single-shot mode and the pin output level, enables or disables timer output, controls interrupts, and controls the status.
254 chapter 11 16-bit reload timer MB90560 series 11.3 16-bit reload timer pins this section describes the pins of the 16-bit reload timer and provides a pin block diagram. n 16-bit reload timer pins the pins of the 16-bit reload timer are shared with the general-purpose ports. table 11.3-1 lists the functions of the pins, i/o format, and settings required to use the 16-bit reload timer. table 11.3-1 16-bit reload timer pins n block diagram of the 16-bit reload timer pins figure 11.3-1 shows the block diagram of the16-bit reload timer pins. figure 11.3-1 block diagram of the 16-bit reload timer pins pin name pin function i/o format pull-up option standby control settings required for pins p20/tin0 port 2 i/o pin/ timer input cmos output/ cmos hysteresis input not available available setting for the input port (ddr2: bit 0 = 0) p21/to0 port 2 i/o pin/ timer output setting for timer output enable (tmcsr0: oute = 1) p22/tin1 port 2 i/o pin/ timer input setting for the input port (ddr2: bit 2 = 0) p23/to1 port 2 i/o pin/ timer output setting for timer output enable (tmcsr1: oute = 1) internal data bus port data register (pdr) pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) peripheral input* peripheral output* peripheral output enable* 1 11 1 * only pins with peripheral functions are used for peripheral i/o standby control: stop, clock mode with spl=1 p20/tin0 p21/to0 p22/tin1 p23/to1
MB90560 series chapter 11 16-bit reload timer 255 11.4 16-bit reload timer registers the 16-bit reload timer registers are as follows. n 16-bit reload timer registers figure 11.4-1 shows 16-bit reload timer registers. figure 11.4-1 16-bit reload timer registers address 16-bit reload timer 0 16-bit reload timer 1 tmcsr0 (timer control status register) tmr0/tmrlr0 (16-bit timer register/16-bit reload register) (*1) tmcsr1 (timer control status register) tmr1/tmrlr1 (16-bit timer register/16-bit reload register) (*1) *1 this register functions as a 16-bit timer register (tmr) during reading, and functions as a 16-bit reload register (tmrlr) during writing. 000083h,82 h 000085h,84 h 000087h,86 h 000089h,88 h
256 chapter 11 16-bit reload timer MB90560 series 11.4 16-bit reload timer registers 11.4.1 timer control status register, upper part (tmcsr0, tmcsr1: h) bits 11 to bit 7 of the timer control status registers (tmcsr0 and tmcsr1) are used to select the operating mode of the 16-bit reload timer and set the operating conditions. this section describes bit 7: the mod0 bit. n timer control status register, upper part (tmcsr0, tmcsr1: h) figure 11.4-2 timer control status register, upper part (tmcsr0, tmcsr1: h) csl1 mod2 mod1 mod0 csl0 r/w r/w r/w r/w r/w mod2 mod1 mod0 0 0 0 0 1 1 0 0 1 1 x x 0 1 0 1 0 1 mod2 mod1 mod0 x x x x 0 0 1 1 0 1 0 1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit0 tmscr l tmcsr0 000083 h tmcsr1 000087 h csl1 csl0 0 0 1 1 0 1 0 1 xxxx00000 b r/w x address initial value read/write initial value undefined not used machine cycle. value in parentheres are for 16mhz machine clock operating mode selection bit input pin function valid edge and level trigger disabled trigger input gate input (internal clock mode) rising edge falling edge both edges "l" level "h" level operating mode selection bit (event clock mode) input pin function valid edge rising edge falling edge both edges event input count clock selection bit function count clock 1 2 / (0.125 m s) 2 / (2.0 m s) 2 / (0.5 m s) 5 3 internal clock mode event clock mode external event input
MB90560 series chapter 11 16-bit reload timer 257 table 11.4-1 function description of each bit of the upper part of the timer control status register (tmcsr0, tmcsr1: h) bit name function bit15 bit14 bit13 bit12 not used when these bits are read, their values are undefined. writing to these bits has no effect on operation. bit11 bit10 csl1, csl0: count clock selection bits selects the count clock. when these bits are not set to 11 b , internal clock mode is set. the internal clock is counted in this mode. when these bits are set to 11 b , event count mode is set. the external clock edges are counted in this mode. bit9 bit8 bit7 mod2, mod1, mod0: operating mode selection bits the mod2 bit is used to select input pin functions. when the mod2 bit is 0, the input pin is used as a trigger input pin, so that whenever a valid edge is input, the contents of the reload register are loaded into the counter and counting continues. the mod1 and mod0 bits are used to select the type of valid edge. when the mod2 bit is 1, the input pin becomes a gate, meaning that counting will continue only as long as a valid level signal is input. the mod1 bit is an unused bit, and the mod0 bit is used to select the valid level. the mod2 bit is not used. set any value (0 or 1). the input pin is used as a trigger input pin for event input, and the valid edge is selected with mod1 and mod0 bits.
258 chapter 11 16-bit reload timer MB90560 series 11.4 16-bit reload timer registers 11.4.2 timer control status register, lower part (tmcsr0, tmcsr1: l) the lower seven bits of the timer control status registers (tmcsr0 and tmcsr1) are used to set operating conditions for the 16-bit reload timer, enable and disable operation, control interrupts, and check the status. n timer control status register, low part (tmcsr0, tmcsr1: l) figure 11.4-3 timer control status register, low part (tmcsr0, tmcsr1: l) address tmcsr0 000082 h tmcsr1 000086 h initial value 00000000 b mod0* oute outl reld inte uf cnte trg (tmcsr:h bit15 r/w r/w r/w r/w r/w r/w r/w r/w bit8 bit6 bit7 bit5 bit4 bit3 bit2 bit1 bit0 trg 0 no change, no effect on other bits after reloading, counting starts. 1 software trigger bit inte 0 interrupt request output disabled interrupt request output enabled 1 interrupt request enable bit reld 0 one-shot mode reload mode 1 reload selection bit cnte 0 counting stopped counting enabled (wait for the start trigger) 1 count enable bit uf during reading during writing underflow interrupt request flag bit 0 without counter underflow with counter underflow this bit is cleared. no change, no effect on other bits 1 outl in single-shot mode (reld = 0) in reload mode (reld = 1) pin output level selection bit 0 square wave of h during counting square wave of l during count toggle output of l when counting is started. toggle output of h when counting is started. 1 oute pin functions registers and pins corresponding to each channel tmcsr0 p21 to0 p23 to1 tmcsr1 timer output enable bit 0 general-purpose port timer output 1 r/w: read/write : initial value * : see section 10.4.1, "timer control status register, high part," for mod0 (bit 7)
MB90560 series chapter 11 16-bit reload timer 259 table 11.4-2 function description of each bit of the low part of the timer control status register (tmcsr0, tmcsr1: l) bit name function bit6 oute: timer output enable bit this bit enables or disables output from the timer output pin. when this bit is 0, the pin functions as a general-purpose port. when this bit is 1, the pin functions as a timer output pin. in reload mode, the output waveform of this timer output pin toggles. in single-shot mode, the timer outputs a rectangular waveform that indicates that counting is in progress is output. bit5 outl: pin output level selection bit this register is used to select the output level of the timer output pin. the output level of the pin is inverted depending on whether this bit is 0 or 1. bit4 reld: reload selection bit this bit enables reloading. when this bit is 1, the timer is in reload mode. at the same time an underflow occurs, the contents of the reload register are loaded into the counter, and counting continues. when this bit is 0, the timer is in single-shot mode. counting stops when an underflow occurs. bit3 inte: interrupt request enable bit this bit enables or disables output of an interrupt request to the cpu. when this bit and the interrupt request flag (uf) bit are 1, the timer outputs an interrupt request. bit2 uf: underflow interrupt request flag bit this bit is set to 1 when a counter underflow occurs. writing 0 to this bit clears it. writing 1 to this bit does not change the bit value and has no effect on other bits. this bit is also cleared when ei 2 os is activated. bit1 cnte: count enable bit the bit enables or disables counting. when this bit is set to 1, the counter is placed in trigger standby mode. when a trigger occurs, actual counting starts. bit0 trg: software trigger bit this bit starts the interval timer function or counter function with software. writing 1 to this bit applies a software trigger, causing the contents of the reload register to be loaded into the counter and starting counter operation. writing 0 to this bit has no effect. trigger input from this trigger is always valid when the cnte bit is set to 1 regardless of the operating mode.
260 chapter 11 16-bit reload timer MB90560 series 11.4 16-bit reload timer registers 11.4.3 16-bit timer register (tmr0, tmr1) the 16-bit timer register (tmr0, tmr1) is used to read the count value from the 16-bit down counter. n 16-bit timer register (tmr0, tmr1) figure 10.4-4 shows the 16-bit timer registers (tmr0, tmr1). figure 11.4-4 16-bit timer register (tmr0, tmr1) the 16-bit timer register is used to read the counter value from the 16-bit down counter. when counting is enabled (tmcsr: cnte = 1) to start counting, the value written to the 16-bit reload register is loaded into this register, and counting down starts. this register value is stored when the counter is in stop status (tmcsr: cnte = 0). ? this register is able to read the count value even during counting. it should always be read with a word transfer instruction (movw a, 0084h, etc.). ? although the 16-bit timer register (tmr) is functionally a read-only register, it is allocated to the same address as the address of the write-only 16-bit reload register (tmrlr). accordingly, writing to this register has no effect on the tmr value, although writing to tmrlr is done. address address initial value initial value r: read only x: undefined tmr0: 000085 h tmr1: 000089 h tmr0: 000084 h tmr1: 000088 h
11.4 16-bit reload timer registers MB90560 series chapter 11 16-bit reload timer 261 11.4.4 16-bit reload register (tmrlr0, tmrlr1) the 16-bit reload register (tmrlr0, tmrlr1) sets a reload value in the 16-bit down counter. the value written to this register is loaded into the down counter, and the down counter starts with this value. n 16-bit reload register (tmrlr0, tmrlr1) figure 11.4-5 shows the 16-bit reload registers (tmrlr0, tmrlr1). figure 11.4-5 16-bit reload register (tmrlr0, tmrlr1) the initial value of the counter is set in this register when counting is disabled (tmcsr: cnte = 0), regardless of the operating mode of the 16-bit reload timer. when counting is enabled (tmcsr: cnte = 1) and the counter is started, counting down starts from the value written to this register. in reload mode, the value set in the 16-bit reload register (tmrlr) is reloaded into the counter when an underflow occurs, and counting down continues. in single-shot mode, the counter stops at ffff h when an underflow occurs. ? write a value to this register in the counter stop (tmcsr: cnte = 0) state. also, always use a word transfer instruction (movw 0084h,a etc.) to write a value to this register. ? although the 16-bit reload register (tmrlr) is functionally a write-only register, it is allocated to the same address as one of the read-only 16-bit timer registers (tmr). accordingly, since the read value is used as the tmr value, the inc/dec instruction and other instructions for read-modify-write (rmw) operations cannot be used. address initial value initial value address w: write only x: undefined 000085 h 000089 h 000084 h 000088 h
262 chapter 11 16-bit reload timer MB90560 series 11.5 16-bit reload timer interrupts the 16-bit reload timer is able to generate an interrupt request when an underflow of the counter is occurred. it is also coordinated with the extended intelligent i/o service (ei 2 os). n 16-bit reload timer interrupts table 11.5-1 lists the interrupt control bits and interrupt causes of the 16-bit reload timer. table 11.5-1 interrupt control bits and interrupt causes of the 16-bit reload timer in the 16-bit reload timer, the uf bit of the timer control status register (tmcsr) is set to 1 by an underflow (from 0000 h to ffff h ) of the down counter. if an interrupt request is enabled (tmcsr: inte = 1) in this operation, the interrupt request is output to the interrupt controller. n 16-bit reload timer interrupts and ei 2 os table 11.5-2 lists the 16-bit reload timer interrupts and ei2os. table 11.5-2 16-bit reload timer interrupts and ei 2 os d : available when icr09 or the interrupt causes sharing the interrupt vector are not used. *1 the same interrupt number as that for 8-bit timer counter underflow and 16-bit reload timer 0 underflow. *2 the same interrupt number as that for 16-bit free-run timer overflow and 16-bit reload timer 1 underflow. 16-bit reload timer 0 16-bit reload timer 1 interrupt request flag bit tmcsr0: uf tmcsr1: uf interrupt request enable bit tmcsr0: inte tmcsr: inte interrupt cause underflow of the 16-bit down counter (tmr0 ) underflow of the 16-bit down counter (tmr1) channel interrupt number interrupt control register vector table address ei 2 os register name address lower upper bank 16-bit reload timer 0 (*1) #30 (1e h ) icr09 0000b9 h ffff84 h ffff85 h ffff86 h d 16-bit reload timer 1 (*2) #32 (20 h ) icr10 0000ba h ffff7c h ffff7d h ffff7e h
MB90560 series chapter 11 16-bit reload timer 263 n ei 2 os function of the 16-bit reload timer since the 16-bit reload timer has a circuit that coordinates with ei 2 os, the counter can start ei 2 os when an underflow occurs. however, ei 2 os is available only when other peripheral functions sharing the interrupt control register (icr) do not use interrupts. for example, when 16-bit reload timer 1 uses ei2os, interrupts of the 16-bit free-run timer must be disabled.
MB90560 series chapter 11 16-bit reload timer 264 11.6 operation of the 16-bit reload timer this section describes the 16-bit reload timer settings and counter operating status. n 16-bit reload timer settings l internal clock mode setting the setting shown in figure 11.6-1 is required to operate this timer as an interval timer. figure 11.6-1 internal clock mode setting l event counter mode setting the setting shown in figure 11.6-2 is required to operate this timer as an event counter. figure 11.6-2 event counter mode setting other than 11 set the initial value (reload value) of the counter. : used : set 1. set the initial value (reload value) of the counter. : used : set 1. : set the bit corresponding to the pin used to 0. d d
MB90560 series chapter 11 16-bit reload timer 265 n counter operating status the counter status is determined by the cnte bit of the timer control status register (tmcsr) and the internal wait signal. possible settings include the stop status (stop status), trigger wait status (wait status), and running status (run status). figure 11.6-3 shows the transitions of these counter statuses. figure 11.6-3 counter status transition reset cnte = 0 cnte = 0 loading ends. uf = 1 & reld = 0 (single-shot mode) trg = 1 (software trigger) external trigger from tin trg = 1 (software trigger) uf = 1 & reld = 1 (reload mode) cnte = 1 trg = 0 cnte = 1 trg = 1 stop cnte = 0, wait = 1 tot: general-purpose port counter: the counter value is retained when the counter stops. immediately after a reset, it is undefined. tin: input disabled wait : state transition by hardware : state transition by register access : wait signal (internal signal) : software trigger bit of timer control status register (tmcsr) : count enable bit of timer control status register (tmcsr) : underflow interrupt request flag bit of timer control status register (tmcsr) : reload selection bit of timer control status register (tmcsr) load cnte = 1, wait = 1 cnte = 1, wait = 0 to: output initial value counter: the counter value is retained when the counter stops. immediately after a reset, it is undefined until a value is loaded. tin: only trigger input enabled the contents of the reload register are loaded into the counter run cnte = 1, wait = 0 to: functions as to counter: run tin: functions as tin wait trg cnte uf reld
266 chapter 11 16-bit reload timer MB90560 series 11.6 operation of the 16-bit reload timer 11.6.1 reload mode (internal clock mode) synchronized with the internal count clock, the 16-bit reload timer is used for counting down of the 16-bit counter and generating an interrupt request to the cpu when the counter is underflow. it can also output a toggle waveform to the timer output pin. n operation in reload mode (internal clock mode) when counting is enabled (tmcsr: cnte = 1) and the timer is started by the software trigger bit (tmcsr: trg) or external trigger, the value of the reload register (tmrlr) is loaded into the counter, and counting starts. if the count enable bit and software trigger bit are set to 1 simultaneously, counting starts simultaneously with the enabling of counting. when an underflow of the counter value (from 0000 h to ffff h ) occurs, the value of the 16-bit reload register (tmrlr) is loaded into the counter, and counting continues. if the underflow interrupt request flag (uf) bit is set to 1 and the interrupt request enable (inte) bit is 1, an interrupt request is generated. the timer can also output to the to pin a toggle waveform, which is inverted for each underflow. l software trigger operation when 1 is written to the trg bit of the timer control status register (tmcsr), the counter is started. figure 11.6-4 shows software trigger operation in reload mode. figure 11.6-4 count operation in reload mode (software trigger operation) count clock counter data load signal uf bit cnte bit trg bit to pin reload data reload data reload data reload data t: machine cycle * it takes 1t time from trigger input to loading of the reload data.
MB90560 series chapter 11 16-bit reload timer 267 l external trigger operation when a valid edge (rising, falling, and both edges can be selected) is input to the tin pin, the counter is started. figure 11.6-5 shows external trigger operation in reload mode. figure 11.6-5 counting in reload mode (external trigger operation) specify 2/ f (machine clock) or more for the width of the trigger pulse input to the tin pin. l gate input operation while a valid level (h and l levels can be selected) is input to the tin pin, counting is done. figure 11.6-6 shows gate input in reload mode. figure 11.6-6 count operation in reload mode (software trigger and gate input operation) specify 2/ f (machine clock) or more for the width of the trigger pulse input to the tin pin. count clock counter data load signal uf bit cnte bit tin pin to pin reload data reload data reload data reload data t: machine cycle * it takes 2t to 2.5t time from trigger input to loading of the reload data. count clock counter data load signal cnte bit trg bit tin pin t: machine cycle * it takes 1t time from trigger input to loading of the reload data. reload data reload data to pin
268 chapter 11 16-bit reload timer MB90560 series 11.6 operation of the 16-bit reload timer 11.6.2 single-shot mode (internal clock mode) synchronized with the internal count clock, the 16-bit reload timer is used for counting down of the 16-bit counter and generating an interrupt request to the cpu when the counter is underflow. it can also output to the to pin a rectangular waveform indicating that counting is in progress. n single-shot mode (internal clock mode) when counting is enabled (tmcsr: cnte = 1) and the timer is started with the software trigger bit (tmcsr: trg) or external trigger, counting starts. if the count enable bit and software trigger bit are set to 1 simultaneously, counting starts simultaneously with the enabling of counting. when an underflow of the counter value (from 0000 h to ffff h ) occurs, the counter stops in the ffff h state. if the underflow interrupt request flag (uf) bit is set to 1 and the interrupt request enable (inte) bit is 1, an interrupt request is generated. the timer can also output to the to pin a rectangular waveform indicating that counting is in progress. l software trigger operation when 1 is written to the trg bit of the timer control status register (tmcsr), the counter is started. figure 11.6-7 shows the software trigger operation in single-shot mode. figure 11.6-7 count operation in single-shot mode (software trigger operation) count clock counter data load signal uf bit cnte bit trg bit to pin wait for trigger input reload data reload data t: machine cycle * it takes 1t time from trigger input to loading of the reload data.
MB90560 series chapter 11 16-bit reload timer 269 l external trigger operation when a valid edge (rising, falling, and both edges can be selected) is input to the tin pin, the counter is started. figure 11.6-8 shows external trigger operation in single-shot mode. figure 11.6-8 count operation in single-shot mode (external trigger operation) specify 2/ f (machine clock) or more for the width of the trigger pulse input to the tin pin. l gate input operation while a valid level (h and l levels can be selected) is input to the tin pin, counting is done. figure 11.6-9 shows gate input operation in single-shot mode. figure 11.6-9 count operation in single-shot mode (software trigger and gate input operation) specify 2/ f (machine clock) or more for the width of the trigger pulse input to the tin pin. count clock counter reload data data load signal uf bit cnte bit tin bit to pin wait for trigger input reload data t: machine cycle * it takes 2t to 2.5t time from external trigger input to loading of the reload data. count clock counter reload data data load signal uf bit cnte bit trg bit to pin wait for trigger input reload data t: machine cycle * it takes 1t time from trigger input to loading of the reload data. t*
270 chapter 11 16-bit reload timer MB90560 series 11.6 operation of the 16-bit reload timer 11.6.3 event count mode in the 16-bit reload timer, an input edge from the tin pin is used to count down the 16- bit counter and an interrupt request to the cpu is generated when the counter is underflow. it can also output a toggle waveform or rectangular waveform to the to pin. n event count mode when counting is enabled (tmcsr: cnte = 1) and the counter is started (tmcsr: trg = 1), the value of the reload register is loaded into the counter. counting down is then done every time a valid edge (rising, falling, and both edges can be selected) of the pulse input to the tin pin (external count clock) is detected. when the count enable bit and software trigger bit are set to 1 simultaneously, counting is started simultaneously with the enabling of counting. l operation in reload mode when an underflow of the counter value (from 0000 h to ffff h ) occurs, the value of the reload register (tmrlr) is loaded into the counter, and counting continues. if the underflow interrupt request flag (uf) bit is set to 1 and the interrupt request enable bit (tmcsr: inte) is 1, an interrupt request is generated. the timer can also output to the to pin a toggle waveform, which is inverted for each underflow. figure 11.6-10 shows counting in reload mode. figure 11.6-10 count operation in reload mode (event count mode) specify 4/ f (machine clock) or more for the h and l widths of the clock input to the tin pin. reload data tin pin counter data load signal uf bit cnte bit trg bit to pin reload data reload data reload data t: machine cycle * it takes 1t time from trigger input to loading of the reload data.
MB90560 series chapter 11 16-bit reload timer 271 l operation in single-shot mode when an underflow of the counter value (from 0000 h to ffff h ) occurs, the counter stops in the ffff h state. if the underflow interrupt request flag (uf) bit is set to 1 and the interrupt request enable (inte) bit is 1, an interrupt request is generated. the timer can also output to the to pin a rectangular waveform indicating that counting is in progress. figure 11.6-11 shows counting in single-shot mode. figure 11.6-11 counter operation in single-shot mode (event count mode) specify 4/ f (machine clock) or more for the h and l widths of the clock input to the tin pin. tin pin counter reload data data load signal uf bit cnte bit trg bit to pin wait for trigger input reload data t: machine cycle * it takes 1t time from trigger input to loading of the reload data.
272 chapter 11 16-bit reload timer MB90560 series 11.7 usage notes on the 16-bit reload timer notes on using the 16-bit reload timer are given below. n usage notes on the16-bit reload timer l notes on using a program for setting ? write a value to the 16-bit reload register (tmrlr) when counting stops (tmcsr: cnte = 0). also, a value can be read from the 16-bit timer register (tmr) even during counting, but always be sure to use a word transfer instruction (movw a, dir, etc.). ? change the csl1 and csl0 bits of the timer control status register (tmcsr) when the counter has stopped (tmcsr: cnte = 0). l notes about interrupts ? when the uf bit of the timer control status register (tmcsr) is set to 1 and an interrupt request is enabled (tmcsr: inte = 1), control cannot be returned from interrupt processing. always clear the uf bit. ? since the 16-bit reload timer 0 shares an interrupt vector with 8-bit timer 0/1/2, interrupt causes must be checked carefully by the interrupt processing routine when interrupts are used. furthermore, when ei 2 os is used by the 16-bit reload timer 0, 8-bit timer 0/1/2 interrupts must be disabled ? since the 16-bit reload timer 1 shares an interrupt vector with 16-bit free-run timer, interrupt causes must be checked carefully by the interrupt processing routine when interrupts are used. furthermore, when ei 2 os is used by the 16-bit reload timer 0, 16-bit free-run timer interrupts must be disabled
MB90560 series chapter 11 16-bit reload timer 273 11.8 sample programs for the 16-bit reload timer this section contains sample programs for the 16-bit reload timer in internal clock mode and event count mode. n sample program in internal clock mode l processing ? a 25-ms interval timer interrupt is generated with 16-bit reload timer 0. ? the timer is used in reload mode to repeatedly generate an interrupt. ? the timer is started with a software trigger. external trigger input is not used. ? ei 2 os is not used. ? 16 mhz is used for the machine clock, and 2s is used for the count clock. l coding example icr09 equ 0000b9h ; interrupt control register for the 16-bit reload timer tmcsr equ 000082h ; timer control status register tmr equ 000084h ; 16-bit timer register tmrlr equ 000084h ; 16-bit reload register uf equ tmcsr0:2 ; interrupt request flag bit cnte equ tmcsr0:1 ; counter operation enable bit trg equ tmcsr0:0 ; software trigger bit ;-------main program------------------------------------------------------------------------------------------------ code cseg start: ; : ; assumes that stack pointer (sp) has already been ; initialized. and ccr,#0bfh ; interrupt disable mov i:icr09,#00h ; interrupt level 0 (strongest) clrb i:cnte ; temporary stopping of counter movw i:tmrlr0,#30d4h ; sets data for 25-ms timer. movw i:tmcsr0,#00001000000011011b ; interval timer operation, 2 s clock ; disables external trigger and external output. ; selects reload mode, and enables interrupts. ; clears interrupt flag, and starts counter. mov ilm,#07h ; sets ilm in ps to level 7 or ccr,#40h ; interrupt enable loop: mov a,#00h ; endless loop mov a,#01h ; bra loop ; ;-------interrupt program-------------------------------------------------------------------------------------------- wari: clrb i:uf ; clears interrupt request flag. ; : ; user processing ; : reti ; returns from interrupt
274 chapter 11 16-bit reload timer MB90560 series codeends ;-------vector setting------------------------------------------------------------------------------------------------ vect cseg abs=0ffh org 0ff84h ; sets vector for interrupt #29 (1dh). dsl wari org 0ffdch ; sets reset vector dsl start db 00h ; sets single-chip mode. vect ends end start n sample program in event count mode l processing ? when the rising edge of the pulse input to the external event input pin is counted 10,000 times with 16-bit reload timer/counter 0, an interrupt is generated. ? the timer operates in single-shot mode. ? external trigger input selects the rising edge. ? ei 2 os is not used. l coding example icr09 equ 0000b9h ; interrupt control register for the 16-bit reload timer tmcsr equ 000082h ; timer control status register tmr equ 000084h ; 16-bit timer register tmrlr equ 000084h ; 16-bit reload register ddr2 equ 000012h ; port data register uf equ tmcsr0:2 ; interrupt request flag bit cnte equ tmcsr0:1 ; counter operation enable bit trg equ tmcsr0:0 ; software trigger bit ;-------main program------------------------------------------------------------------------------------------------ code cseg start: ; : ; assumes that stack pointer (sp) has already been ; initialized. and ccr,#0bfh ; interrupt disable mov i:icr09,#00h ; interrupt level 0 (strongest) mov i:ddr2,#00h ; sets p20/tin0 pin to input. clrb i:cnte ; temporary stopping of counter movw i:tmrlr0,#2710h ; sets reload value to 10,000. movw i:tmcsr0,#0000110010001011b ; counter operation, external trigger, rising ; disables edge and external output. ; selects single-shot mode and enables interrupts. ; clears interrupt flag, starts counter. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; interrupt enable loop: mov a,#00h ; endless loop mov a,#01h ; bra loop ;
MB90560 series chapter 11 16-bit reload timer 275 ;-------interrupt program-------------------------------------------------------------------------------------------- wari: clrb i:uf ; clears interrupt request flag. ; : ; user processing ; : reti ; returns from interrupt. code ends ;-------vector setting------------------------------------------------------------------------------------------------- vectc seg abs=0ffh org 0ff84h ; sets vector for interrupt #30 (1eh). dsl wari org 0ffdch ; sets reset vector dsl start db 00h ; sets single-chip mode. vect ends end start

chapter 12 multi-function timer this chapter describes the functions and operation of the multi-function timer in MB90560 series. 12.1 overview of multi-function timer .................................................. 278 12.2 block diagram of multi-function timer.......................................... 280 12.3 register of multi-function timer................................................... 284 12.4 operation of multi-function timer ................................................ 324
278 chapter 12 multi-function timer MB90560 series 12.1 overview of multi-function timer the multi-function timer consists of a 16-bit free-run timer, six 16-bit output compare, four 16-bit input capture, 6 channels of 8-bit ppg timer (3 channels of 16-bit ppg timer) and a waveform generator. by using this waveform generator, 12 independent waveform can be outputted through 16-bit free-run timer. furthermore input pulse width measurement and external clock cycle measurement can be done. n 16-bit free-run timer (x1) the 16-bit free-run timer consists of a 16-bit up-counter, control register, 16-bit compare clear register and a prescaler. the output value of this counter will be used as the count clock of the output compares and input captures ? 6 types of counter operation clock ( f , f /2, f /4, f /8, f /16, f /32, f /64 f /128) can be selected. f : internal clock ? an interrupt is generated when there is an overflow in the counter value or comparing match with compare clear register (mode setting is necessary for compare match) ? reset, software clear, compare match with compare clear register will reset the counter value to 0000 h n output compare (x6) the output compare consists of six 16-bit compare registers, compare output latch and compare control registers. an interrupt is generated and output level is inverted when the value of 16-bit free run timer and compare register are matched. ? 6 compare registers can be operated independently. output pins and interrupt flag are corresponding to each compare register. ? 2 compare register can be paired to control the output pins. inverts output pins by using 2 compare register together. ? setting the initial value for each output pin is possible. ? an interrupt is generated when compare register is matched. n input capture (x4) input capture consists of 4 independent external input pins, the corresponding capture register and capture control register. by detecting any edge of the input signal from the external pin, the value of the 16-bit free-run timer can be stored in the capture register and an interrupt is generated simultaneously. ? 3 types of trigger edge (rising edge, falling edge, both edge) of the external input signal can be selected. ? 4 input captures can operated independently. ? an interrupt is generated by detecting a valid edge from external input.
MB90560 series chapter 12 multi-function timer 279 n 8/16-bit ppg timer (8-bit ppg x 6, 16-bit ppg x 3) 8/16-bit ppg timer consists of six 8-bit down-counter, twelve 8-bit re-load register and three 8-bit control register. by using it as 8/16-bit re-load timer, it is possible to operate as an event counter. by setting of 8/16-bit l width and h width, it is possible to output a pulse with any cycle duty ratio. ? 8-bit ppg output operation mode 6 channels of 8-bit ppg output can be operated independently. ? 16-bit ppg output operation mode 3 channels of 16-bit ppg output can be operated independently. ? 8+8-bit ppg output operation mode in this mode, ch/0/ch2/ch4 can be operated as an 8-bit prescaler, in which an underflow output of ch/0/ch2/ch4 is used as a count clock for ch1/ch3/ch5. it is possible to output any cycle from any 8-bit ppg output. ? ppg output operation the 8/16-bit ppg timer can output pulse waveforms with variable period and duty ratio. also, it can be used as d/a converter in conjunction with an external circuit. n waveform generator the waveform generator consists of three 8-bit re-load registers, three timer control registers and 8-bit waveform control register. with waveform generator, it is possible to generate realtime output, 8/16-bit ppg waveform output, non-overlap 3-phase waveform output for inverter control and dc chopper waveform output. ? it is possible to generate a non-overlap waveform output based on dead-time of 8-bit timer. (dead-time timer function) ? it is possible to generate a non-overlap waveform output when realtime output is operated in 2-channel mode.(dead-time timer function) ? by detecting realtime output compare match, gate signal of the ppg timer operation will be generated to start or stop ppg timer operation. (gate function) ? when a match is detected by real-time output compare, the 8-bit timer is activated. the ppg timer can be started or stopped easily by generating a gate signal for ppg operation until the 8-bit timer stops. (gate function) ? forced stop control using dtti pin input external pin control can be performed through clockless dtti pin input even when oscillation is stopped. (the pin level can be set by each pin or software.)
280 chapter 12 multi-function timer MB90560 series 12.2 block diagram of multi-function timer block diagram of multi-function timer is shown in the section. n realtime i/o block diagram figure 12.2-1 block diagram of realtime i/o f 2 m c - 1 6 l x b u s 16-bit free-run timer pre-scaler ivf ivfe stop mode sclr clk2 clk1 clk0 f interrupt #31 (1fh) 16-bit compare clear register compare circuit msi3~0 iclr icre compare register 0/2/4 compare circuit t q compare register 1/3/5 compare circuit t q a/d rt0/2/4 interrupt #34 (22h) cmod rt1/3/5 iop1 iop0 ioe1 ioe0 eg11 eg10 eg01 eg00 icp0 icp1 ice0 ice1 capture register 0/2 in0/2 edge detect capture register 1/3 in1/3 edge detect interrupt #33, #35 #33, #35 interrupt #13, #17, #21 #15, #19, #23 (waveform generator) (waveform generator) clock
MB90560 series chapter 12 multi-function timer 281 n 8/16-bit ppg timer block diagram figure 12.2-2 block diagram of 8/16-bit ppg timer f 2 m c - 1 6 l x b u s pcnt0 (down counter) pre-scaler pc02 pc01 pc00 pos0 pen0 sst0 poe0 puf0 pie0 f interrupt selector control circuit prll0/2/4* prlh0/2/4* prlbh0/2/4 selector ch1/3/5 port gate0/1 ppg0/2/4 pcnt0 (down counter) pre-scaler pc102 pc11 pc10 pos1 pen1 sst1 poe1 puf1 pie1 f interrupt selector control circuit prll1/3/5* prlh1/3/5* prlbh1/3/5 selector gate1 ppg1/3/5 ch0/2/4 reload reload #14, #18, #22 #16, #20, #24 * : prll0/2/4, prlh0/2/4. prll1/3/5 and prlh1/3/5 are ppg reload registers.
282 chapter 12 multi-function timer MB90560 series n waveform generator block diagram figure 12.2-3 block diagram of waveform generator f 2 m c - 1 6 l x b u s pre-scaler dck2 dck1 dck0 tmd1 tmd0 nrsl dtil dtie f dtti control circuit dtti waveform selector generator selector dead-time generator 8-bit reload register 0 8-bit timer compare circuit to0 to1 u x gate0/1 (ppg timer) rt0 rt1 rto0/u rto1/x clock waveform selector generator selector dead-time generator 8-bit reload register 1 8-bit timer compare circuit to0 to1 v y gate2/3 (ppg timer) rt2 rt3 rto2/v rto3/y waveform selector generator selector dead-time generator 8-bit reload register 2 8-bit timer compare circuit to4 to5 w z gate4/5 (ppg timer) rt4 rt5 rto4/w rto5/z ppg selection circuit ppg5 ppg4 ppg3 ppg2 ppg1 ppg0 pgs1, pgs0
MB90560 series chapter 12 multi-function timer 283 memo
284 chapter 12 multi-function timer MB90560 series 12.3 register of multi-function timer this section describes registers of multi-function timer. n 16-bit free-run timer registers figure 12.3-1 registers of 16-bit free-run timer 15 14 13 12 11 10 9 8 r/w x address: 000059 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x cl15 cl14 cl13 cl12 cl11 cl10 cl09 cl08 address: 000058 h 76543 2 10 compare clear register (upper) compare clear register (lower) cpclr cpclr initial value read/write bit number r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write bit number cl07 cl06 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 r/w 0 address: 00005b h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 t15 t14 t13 t12 t11 t10 t09 t08 address: 00005a h 76543 2 10 timer data register (upper) timer data register (lower) tcdt tcdt initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number t07 t06 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 r/w 0 address: 00005d h r/w x r/w x r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 ecke msi2 msi1 msi0 iclr icre address: 00005c h 76543 2 10 timer control status register (upper) timer control status register (lower) tccs tccs initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number ivf ivfe stop mode sclr clk2 clk1 clk0
MB90560 series chapter 12 multi-function timer 285 n output compare registers figure 12.3-2 registers of output compare 15 14 13 12 11 10 9 8 bit number compare register (upper) 7 6 5 4 3 2 1 0 bit number compare register (lower) address: ch0 000071 h ch1 000073 h ch2 000075 h ch3 000077 h ch4 000079 h ch5 00007b h occp0~5 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write op15 op14 op13 op12 op11 op10 op09 op08 address: ch0 000070 h ch1 000072 h ch2 000074 h ch3 000076 h ch4 000078 h ch5 00007a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write occp0~5 op07 op06 op05 op04 op03 op02 op01 op00 15 14 13 12 11 10 9 8 bit number compare control register (upper) 7 6 5 4 3 2 1 0 bit number compare control register (lower) address: ch1 00007d h ch3 00007f h ch5 000081 h ocs1/3/5 r/w x r/w x r/w x r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write cmod ote1 ote0 otd1 otd0 r/w 0 r/w 0 r/w 0 r/w 0 r/w x r/w x r/w 0 r/w 0 initial value read/write ocs0/2/4 iop1 iop0 ioe1 ioe0 cst1 cst0 address: ch0 00007c h ch2 00007e h ch4 000080 h
286 chapter 12 multi-function timer MB90560 series n input capture registers figure 12.3-3 registers of 16-bit input capture 15 14 13 12 11 10 9 8 bit number input capture register (upper) 7 6 5 4 3 2 1 0 bit number input capture register (lower) address: ch0 000061 h ch1 000063 h ch2 000065 h ch3 000067 h ipcp0~3 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 address: ch0 000060 h ch1 000062 h ch2 000064 h ch3 000066 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write ipcp0~3 cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 15 14 13 12 11 10 9 8 r/w 0 address: 000069 h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 icp3 icp2 ice3 ice2 eg31 eg30 eg21 eg20 address: 000068 h 76543 2 10 capture control register (upper) capture control register (lower) ics23 ics01 initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00
MB90560 series chapter 12 multi-function timer 287 n 8/16-bit ppg timer registers figure 12.3-4 registers of 8/16-bit ppg timers 15 14 13 12 11 10 9 8 bit number ppg reload register (upper) 7 6 5 4 3 2 1 0 bit number ppg reload register (lower) address: ch0 000039 h ch1 00003b h ch2 000041 h ch3 000043 h ch4 000049 h ch5 00004b h prlh0~5 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write address: ch0 000038 h ch1 00003a h ch2 000040 h ch3 000042 h ch4 000048 h ch5 00004a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write prll0~5 15 14 13 12 11 10 9 8 bit number ppg1/3/5 control register 7 6 5 4 3 2 1 0 bit number ppg0/2/4 control register address: ch1 00003d h ch3 000045 h ch5 00004d h ppgc1/3/5 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 1 r/w 0 initial value read/write r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 1 r/w 0 initial value read/write ppgc0/2/4 address: ch0 00003c h ch2 000044 h ch4 00004c h pen1 sst1 poe1 pie1 puf1 md01 md00 pen0 sst0 poe0 pie0 puf0 7 6 5 4 3 2 1 0 bit number ppg clock control register r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w x initial value read/write pcs01/23/45 address: ch0,1 00003e h ch2,3 000046 h ch4,5 00004e h pc12 pc11 pc10 pc02 pc01 pc00 pos1 pos0 reserved reserved r/w x
288 chapter 12 multi-function timer MB90560 series n waveform generator registers figure 12.3-5 registers of waveform generator 15 14 13 12 11 10 9 8 bit number 8-bit timer control register 7 6 5 4 3 2 1 0 bit number 8-bit reload register address: ch0 000051 h ch1 000053 h ch2 000055 h dtcr0/1/2 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write tmrr0/1/2 address: ch0 000050 h ch1 000052 h ch2 000054 h dmod gten pgen tmif tmie tmd2 tmd1 tmd0 address: 000056 h 76543 2 10 waveform control register sigcr bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write dtie dtil nrsl dck2 dck1 dck0 pgs1 pgs0
MB90560 series chapter 12 multi-function timer 289 memo
290 chapter 12 multi-function timer MB90560 series 12.3 registers of multi-function timer 12.3.1 registers of 16-bit free-run timer this section describe registers of 16-bit free-run timer and register details. those register are compare clear registers, timer data register and timer control status register. n 16-bit free-run timer registers figure 12.3.1-1 registers of 16-bit free-run timer 15 14 13 12 11 10 9 8 r/w x address: 000059 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x cl15 cl14 cl13 cl12 cl11 cl10 cl09 cl08 address: 000058 h 76543 2 10 compare clear register (upper) compare clear register (lower) cpclr cpclr initial value read/write bit number r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write bit number cl07 cl06 cl05 cl04 cl03 cl02 cl01 cl00 15 14 13 12 11 10 9 8 r/w 0 address: 00005b h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 t15 t14 t13 t12 t11 t10 t09 t08 address: 00005a h 76543 2 10 timer data register (upper) timer data register (lower) tcdt tcdt initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number t07 t06 t05 t04 t03 t02 t01 t00 15 14 13 12 11 10 9 8 r/w 0 address: 00005d h r/w x r/w x r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 ecke msi2 msi1 msi0 iclr icre address: 00005c h 76543 2 10 timer control status register (upper) timer control status register (lower) tccs tccs initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number ivf ivfe stop mode sclr clk2 clk1 clk0
MB90560 series chapter 12 multi-function timer 291 12.3.1 registers of 16-bit free-run timer 12.3.1.1 compare clear register (cpclr) compare clear register (cpclr) is 16-bit register. when this register is matched with the count value of 16-bit free-run timer, the 16-bit free-run timer will be reset to 0000 h . n compare clear register (cpcr) figure 12.3.1.1-1 compare clear register (cpcr) compare clear register is 16-bit register and is used to compare the count value of the 16-bit free-run timer. the initial value of this register is undetermined, so that the register must be set a value before starting an operation. word access instruction to this register is recommended. when this register is matched with the count value of 16-bit free-run timer, 16-bit free-run timer will be reset to 0000 h and the compare clear interrupt flag will be set. furthermore, when the interrupt operation is enabled, interrupt request will be sent to the cpu. 15 14 13 12 11 10 9 8 r/w x address: 000059 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x cl15 cl14 cl13 cl12 cl11 cl10 cl09 cl08 address: 000058 h 76543 2 10 compare clear register (upper) compare clear register (lower) cpclr cpclr initial value read/write bit number r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write bit number cl07 cl06 cl05 cl04 cl03 cl02 cl01 cl00
292 chapter 12 multi-function timer MB90560 series 12.3.1 registers of 16-bit free-run timer 12.3.1.2 timer data register (tcdt) the timer data register (tcdt) is used to read the count value of 16-bit free-run timer. n timer data register (tcdt) figure 12.3.1.2-1 timer data register the timer data register is used to read the count value of the 16-bit free-run timer. the counter value is cleared to '0000' upon a reset. the timer value can be set by writing a value to this register. however, ensure that the value is written while the operation is stopped (stop=1). word access instruction to the timer data register is recommended. the 16-bit free-run timer is initialized upon the following factors: ? reset ? clear bit (clr) of control status register ? a match between compare clear register and the timer counter value (this can be performed only in an appropriate mode.) 15 14 13 12 11 10 9 8 r/w 0 address: 00005b h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 t15 t14 t13 t12 t11 t10 t09 t08 address: 00005a h 76543 2 10 timer data register (upper) timer data register (lower) tcdt tcdt initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number t07 t06 t05 t04 t03 t02 t01 t00
MB90560 series chapter 12 multi-function timer 293 memo
294 chapter 12 multi-function timer MB90560 series 12.3.1 registers of 16-bit free-run timer 12.3.1.3 timer control status register (tccs) the timer control status register (tccs) is 16-bit register and used to control the operation of 16-bit free-run timer n timer control status register (upper) figure 12.3.1.3-1 timer control status register (upper) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 00005d h ecke msi2 msi1 msi0 iclr icre 0xx00000 b r/w r/w r/w r/w r/w r/w icre compare interrupt request enable bit 0 enable interrupt request 1 disable interrupt request sc11 compare interrupt request flag bit read write 0 count value and set value is not matched clear this bit 1 count value and set value is match no effect msi2 msi1 msi0 masking interrupt bits 0 0 0 interrupt is generated when 1st match 001 interrupt is generated when 2nd match 010 interrupt is generated when 3rd match 011 interrupt is generated when 4th match 100 interrupt is generated when 5th match 101 interrupt is generated when 6th match 110 interrupt is generated when 7th match 111 interrupt is generated when 8th match ecke clock selection bit 0 select internal clock 1 select external clock from frck pin x : indeterminate r/w : read and write : initial value : not used
MB90560 series chapter 12 multi-function timer 295 table 12.3.1.3-1 timer control status register (upper) bit bit function bit 15 ecke: clock selection bit ? this bit is used to select either external or internal count clock source for the 16-bit free-run timer. change this bit when the output compare and input capture are in stop status because the clock will be changed as soon as this bit is changed. note: when selecting internal clock, set the count clock to bit 2~0 (clk2~0). this count clock will become the base clock. when inputting clock from frck pin, set ddr1:bit7=0 bit 14 bit 13 unused bit ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 12 bit 11 bit 10 mis2~0: masking interrupt bit ? these bits are used to set the number of times of masking the compare clear interrupt. 16-bit free-run timer will reload the count value every time when these 3 bits is not 000 b and the 3 bits will be decrement by 1 until these 3 bits becomes 000 b . the number of masking interrupt = the value of these 3 bits. (i.e. when masking two times and interrupt is generated in the 3rd time of the match, set the value = 010 b . however, there is no masking interrupt when the value is 000 b . bit 9 iclr: compare interrupt request flag bit ? this bit is an interrupt request flag for compare clear. ? when the compare clear register and 16-bit free-run timer value are matched and the counter is cleared, this bit will become 1. ? interrupt is generated when the interrupt request enable bit (bit8: icre) is set to 1. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 8 icre: compare interrupt request enable bit ? this is the interrupt request enable bit for the compare clear. ? when this bit is 1 and the interrupt flag (bit9: iclr) is set to 1, an interrupt will be generated.
296 chapter 12 multi-function timer MB90560 series n timer control status register (lower) figure 12.3.1.3-2 timer control status register (lower) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 00005c h ivf ivfe stop mode sclr clk2 clk1 clk0 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w clk2 clk1 clk0 clock frequency selection bit count clock f = 16mhz f = 8mhz f = 4mhz f = 1mhz 00 0 f 62.5 ns 125 ns 0.25 m s1 m s 00 1 f /2 125 ns 0.25 m s0.5 m s2 m s 01 0 f /4 0.25 m s0.5 m s1 m s4 m s 01 1 f /8 0.5 m s1 m s2 m s8 m s 10 0 f /16 1 m s2 m s4 m s 16 m s 10 1 f /32 2 m s4 m s8 m s 32 m s 11 0 f /64 4 m s8 m s 16 m s 64 m s 11 1 f /128 8 m s 16 m s 32 m s 128 m s f : machine cycle sclr clear bit write read 0 no effect always read 0 1 initialize counter to 0000 h mode initialization condition bit 0 initialize counter by reset and clear bit (bit3: sclr) 1 initialize counter by reset, clear bit (bit3: sclr) and match values with compare register 5 of output compare. stop counter enable bit 0 counting is enabled (operation) 1 counting is disabled (stop) ivfe timer interrupt request enable bit 0 interrupt is disabled 1 interrupt is enabled ivf timer interrupt request flag bit read write 0 no interrupt request clear this bit 1 has interrupt request no effect r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 297 table 12.3.1.3-2 timer control status register (lower) bit function bit 7 ivf: timer interrupt request flag bit ? this bit is an interrupt request flag for 16-bit free-run timer. ? this bit will be set to 1 when the 16-bit free-run timer is overflow. ? interrupt will be generated when the timer interrupt request enable bit (bit6: ivfe) is set to 1. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 6 ivfe: timer interrupt request enable bit ? this is the interrupt request enable bit for 16-bit free-run timer clear. ? when this bit is 1 and the timer interrupt request flag bit (bit7: iclr) is set to 1, an interrupt will be generated. bit 5 stop: counter enable bit ? this bit is used to stop/start the counting of the 16-bit free-run timer. ? writing 1 to this bit will stop the counting of the 16-bit free-run timer ? writing 0 to this bit will start the counting of the 16-bit free-run timer. note: when the 16-bit free-run timer is stopped, the output compare operation will be also stopped bit 4 mode: initialization condition bit ? this bit is used to set the initializing condition for the 16-bit free- run timer. ? when it is 0, 16-bit free-run counter will be initialized by the reset and the clear bit reset (bit 3:sclr). ? when it is 1, 16-bit free-run timer will be initialized by not only the reset and the clear bit reset (bit 3:sclr), but also when the count value is matched with the compare clear register. note: initialization of the counter value will be at the changing point of the count value. bit 3 sclr: clear bit ? this bit is used to initialize the 16-bit free-run time to the value of 0000 h . ? writing 1 will initialize 16-bit free-run counter to 0000 h ? writing 0 has no meaning. ? read value is always 0 note: initialization of the counter value will be at the changing point of the count value. note: if the initialization when the counter is stopped, write 0000 h to the data register. bit 2 bit 1 bit 0 clk2~0: clock frequency section bit ? this bit is used to select count clock for the 16-bit free-run timer. change this bit when the output compare and input capture are in stop status because the clock will be changed as soon as this bit is changed.
298 chapter 12 multi-function timer MB90560 series 12.3 registers of multi-function timer 12.3.2 registers of 16-bit output compare this section describe registers of 16-bit output compare and register details. n output compare registers figure 12.3.2-1 registers of output compare 15 14 13 12 11 10 9 8 bit number compare register (upper) 7 6 5 4 3 2 1 0 bit number compare register (lower) address: ch0 000071 h ch1 000073 h ch2 000075 h ch3 000077 h ch4 000079 h ch5 00007b h occp0~5 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write op15 op14 op13 op12 op11 op10 op09 op08 address: ch0 000070 h ch1 000072 h ch2 000074 h ch3 000076 h ch4 000078 h ch5 00007a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write occp0~5 op07 op06 op05 op04 op03 op02 op01 op00 15 14 13 12 11 10 9 8 bit number compare control register (upper) 7 6 5 4 3 2 1 0 bit number compare control register (lower) address: ch1 00007d h ch3 00007f h ch5 000081 h ocs1/3/5 r/w x r/w x r/w x r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write cmod ote1 ote0 otd1 otd0 r/w 0 r/w 0 r/w 0 r/w 0 r/w x r/w x r/w 0 r/w 0 initial value read/write ocs0/2/4 iop1 iop0 ioe1 ioe0 cst1 cst0 address: ch0 00007c h ch2 00007e h ch4 000080 h
MB90560 series chapter 12 multi-function timer 299 12.3.2 registers of 16-bit output compare 12.3.2.1 compare registers (occp0~5) compare registers (occp0~5) are used to set the compare value for the 16-bit free-run timer. n compare registers (occp0~5) figure 12.3.2.1-1 compare registers (occp0~5) the compare registers (occp0~5) are 16-bit registers which are used to compare the count value of 16-bit free run timer. the initial values of the compare registers (occp0~5) are undetermined, so that the value must be set before enabling the operation. word access instruction to this register is recommended. when the value of this register matches that of the 16-bit free-run timer, a compare signal is generated to set the output compare interrupt flag. if output is enabled, the output level (rt0~5) corresponding to the compare register (occp0~5) is reversed. 15 14 13 12 11 10 9 8 bit number compare register (upper) 7 6 5 4 3 2 1 0 bit number compare register (lower) address: ch0 000071 h ch1 000073 h ch2 000075 h ch3 000077 h ch4 000079 h ch5 00007b h occp0~5 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write op15 op14 op13 op12 op11 op10 op09 op08 address: ch0 000070 h ch1 000072 h ch2 000074 h ch3 000076 h ch4 000078 h ch5 00007a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write occp0~5 op07 op06 op05 op04 op03 op02 op01 op00
300 chapter 12 multi-function timer MB90560 series 12.3.2 registers of 16-bit output compare 12.3.2.2 compare control registers (osc0/1/2/3/4/5) compare control register is used to control the output level, output enable, output reverse mode, compare operation enable, compare match interrupt enable and compare match interrupt flag for rto0~5. n compare control register (upper, osc1/3/5) figure 12.3.2.2-1 compare control register (upper, osc1/3/5) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value ch1: 00007d h ch3: 00007f h ch5: 000081 h cmod ote1 ote0 otd1 otd0 xxx00000 b r/w r/w r/w r/w r/w otd0 output level bit 0 output 0 for rt0/rt2/rt4 1 output 1 for rt0/rt2/rt4 otd1 output level bit 0 output 0 for rt1/rt3/rt5 1 output 1 for rt1/rt3/rt5 ote0 output enable bit 0 general-purpose port (port 30/32/34) 1 output compare output pin (rt0/rt2/rt4) ote1 output enable bit 0 general-purpose port (port 31/33/35) 1 output compare output pin (rt1/rt3/rt5) cmod output level reverse mode bit 0 rt0/2/4: the level is reversed upon a match with compare register 0/ 2/ 4. rt1/3/5: the level is reversed upon a match with compare register 1/3/5 respectively 1 rt0/2/4: the level is reversed upon a match with compare register 0/2/4. rt1/3/5: the level is reversed upon a match with compare register 0 or 1, 2 or 3, 4 or 5. x : indeterminate r/w : read and write : initial value : not used
MB90560 series chapter 12 multi-function timer 301 table 12.3.2.2-1 compare control register (upper, osc1/3/5) bit bit function bit 15 bit 14 bit 13 unused bit ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 12 cmod: output level reverse mode bit ? cmod is used to switch the pin output level reverse mode upon a match while pin output is enabled (ote1=1 or ote0=1). ? when cmod=0 (default), the output level of the pin is reversed upon a match with corresponding compare register. rt0/2/4: the level is reversed upon a match between the 16-bit free-run timer and compare register 0/2/4. rt1/3/5: the level is reversed upon a match between the 16-bit free-run timer and compare register 1/3/5. ? when cmod=1, the output level of the pin corresponding to compare register is reversed as same as when cmod=0. however, the output level of the pin (rt1) corresponding to compare register 1 is reversed only when a match is detected in both compare register 0 and 1. if compare registers 0 and 1 have the same value, the same operation as when only one compare register is used. rt0/2/4: the level is reversed upon a match between the 16-bit free-run timer and compare register 0/2/4. rt1/3/5: the level is reversed upon a match between the 16-bit free-run timer and compare register 0 or 1, 2 or 3, 4 or 5. bit 11 ote1: output enable bit ? this bit is used to enable output compare pin output for output compare 1/3/5. ? the initial value for these bits is '0'. note: the output enable bit of the waveform generator must be set when dead-time timer is used in the waveform generator. bit 10 ote0: output enable bit ? this bit is used to enable output compare pin output for output compare 0/2/4. ? the initial value for these bits is '0.' note: the output enable bit of the waveform generator must be set when dead-time timer is used in the waveform generator. bit 9 otd1: output level bit ? this bit is used to change the pin output level for output compare 1/3/5 when the output compare pin output is enabled. ? the initial value of the compare pin output is '0.' ? ensure that the compare operation is stopped before a value is written. when reading this bit, this bit indicate the output compare pin output value bit 8 otd0: output level bit ? this bit is used to change the pin output level for output compare 0/2/4 when the output compare pin output is enabled. ? the initial value of the compare pin output is '0.' ? ensure that the compare operation is stopped before a value is written. when reading this bit, this bit indicates the output compare pin output value.
302 chapter 12 multi-function timer MB90560 series n compare control register (lower, osc0/2/4) figure 12.3.2.2-2 compare control register (lower, osc0/2/4) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value ch0: 00007c h ch2: 00007e h ch4: 000080 h iop1 iop0 ioe1 ioe0 cst1 cst0 00000000 b r/w r/w r/w r/w r/w r/w cst0 compare operation enable bit 0 disable compare operation for compare register 0/2/4 1 enable compare operation for compare register 0/2/4 cst1 compare operation enable bit 0 disable compare operation for compare register 1/3/5 1 enable compare operation for compare register 1/3/5 ioe0 compare match interrupt enable bit 0 disable compare match interrupt for compare register 0/2/4 1 enable compare match interrupt for compare register 0/2/4 ioe1 compare match interrupt enable bit 0 disable compare match interrupt for compare register 1/3/5 1 enable compare match interrupt for compare register 1/3/5 iop0 compare match interrupt flag bit 0 no compare match interrupt for compare register 0/2/4 1 compare match interrupt for compare register 0/2/4 iop1 compare match interrupt flag bit 0 no compare match interrupt for compare register 1/3/5 1 compare match interrupt for compare register 1/3/5 r/w : read and write : initial value : not used
MB90560 series chapter 12 multi-function timer 303 table 12.3.2.2-2 compare control register (lower, osc0/2/4) bit function bit 7 iop1: compare match interrupt flag bit ? this bit is an interrupt flag for when compare register 1/3/5 is matched with the value of 16-bit free-run timer. ? '1' is written to this bit when the compare register value matches the 16-bit free-run timer value. ? while the interrupt request bits (ioe1) is enabled, an output compare interrupt occurs when the iop1 bit is set. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 6 iop0: compare match interrupt flag bit ? this bit is an interrupt flag for when compare register 0/2/4 is matched with the value of 16-bit free-run timer. ? '1' is written to this bit when the compare register value matches the 16-bit free-run timer value. ? while the interrupt request bits (ioe0) is enabled, an output compare interrupt occurs when the iop0 bit is set. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 5 ioe1: compare match interrupt enable bit ? this bit is used to enable output compare interrupt for compare register 1/3/5. ? while the '1' is written to this bit, an output compare interrupt occurs when an interrupt flag (iop1) is set. bit 4 ioe0: compare match interrupt enable bit ? this bit is used to enable output compare interrupt for compare register 0/2/4. ? while the '1' is written to this bit, an output compare interrupt occurs when an interrupt flag (iop0) is set. bit 3 bit 2 unused bit ? the read value is indeterminate. ? writing to this bit has no effect on the operation. bit 1 cst1: compare operation enable bit ? this bit is used to enable the compare operation between 16-bit free-run timer and compare register 1/3/5 ? ensure that a value is written into the compare register and timer data register before the compare operation is enabled. note: since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation. bit 0 cst0: compare operation enable bit ? this bit is used to enable the compare operation between 16-bit free-run timer and compare register 0/2/4 ? ensure that a value is written into the compare register and timer data register before the compare operation is enabled. note: since output compare is synchronized with the 16-bit free-run timer clock, stopping the 16-bit free-run timer stops compare operation.
304 chapter 12 multi-function timer MB90560 series 12.3 registers of multi-function timer 12.3.3 registers of 16-bit input capture the section describe the registers of 16-bit input capture, which are input capture registers and capture control registers. n input capture registers figure 12.3.3-1 registers of 16-bit input capture 15 14 13 12 11 10 9 8 bit number input capture register (upper) 7 6 5 4 3 2 1 0 bit number input capture register (lower) address: ch0 000061 h ch1 000063 h ch2 000065 h ch3 000067 h ipcp0~3 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 address: ch0 000060 h ch1 000062 h ch2 000064 h ch3 000066 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write ipcp0~3 cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00 15 14 13 12 11 10 9 8 r/w 0 address: 000069 h r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 icp3 icp2 ice3 ice2 eg31 eg30 eg21 eg20 address: 000068 h 76543 2 10 capture control register (upper) capture control register (lower) ics23 ics01 initial value read/write bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write bit number icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00
MB90560 series chapter 12 multi-function timer 305 12.3.3 registers of 16-bit input capture 12.3.3.1 input capture register (ipcp0~3) input capture registers are used to hold the count value of 16-bit timer when a valid edge of the input waveform is detected. n input capture register (ipcp0~3) figure 12.3.3.1-1 input capture registers (ipcp0~3) this register is used to store the value of the 16-bit timer when a valid edge of the corresponding external pin input waveform is detected. (word access instruction to this register is recommended. no data can be written to this register.) 15 14 13 12 11 10 9 8 input capture register (upper) 7 6 5 4 3 2 1 0 bit number input capture register (lower) address: ch0 000061 h ch1 000063 h ch2 000065 h ch3 000067 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write cp15 cp14 cp13 cp12 cp11 cp10 cp09 cp08 address: ch0 000060 h ch1 000062 h ch2 000064 h ch3 000066 h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write ipcp0~3 cp07 cp06 cp05 cp04 cp03 cp02 cp01 cp00
306 chapter 12 multi-function timer MB90560 series 12.3.3 registers of 16-bit input capture 12.3.3.2 capture control registers (ics23, ics01) capture control registers (ics23, ics01) are used to control edge selection, interrupt request enable and interrupt request flag for input capture 0~3. n capture control register (ics23) figure 12.3.3.2-1 capture control register (ics23) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value 000069 h icp3 icp2 ice3 ice2 eg31 eg30 eg21 eg20 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w eg21 eg20 edge selection bit (input capture 2) 0 0 no edge detection (stop) 01 rising edge detection 10 falling edge detection 11 both edges detection eg31 eg30 edge selection bit (input capture 3) 0 0 no edge detection (stop) 01 rising edge detection 10 falling edge detection 11 both edges detection ice2 interrupt request enable bit (input capture 2) 0 disable interrupt request 1 enable interrupt request ice3 interrupt request enable bit (input capture 3) 0 disable interrupt request 1 enable interrupt request icp2 interrupt request flag bit (input capture 2) read write 0 no valid detected clear this bit 1 valid detected no effect icp3 interrupt request flag bit (input capture 3) read write 0 no valid detected clear this bit 1 valid detected no effect r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 307 table 12.3.3.2-1 capture control register (ics23) bit bit function bit 15 icp3: interrupt request flag bit (input capture 3) ? this bit is used as interrupt request flag for input capture 3. ? 1 is written to this bit upon detection of a valid edge of an external input pin. ? while the interrupt enable bit (ice3) is set, an interrupt can be generated upon detection of a valid edge. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 14 icp2: interrupt request flag (input capture 2) ? this bit is used as interrupt request flag for input capture 2. ? 1 is written to this bit upon detection of a valid edge of an external input pin. ? while the interrupt enable bit (ice2) is set, an interrupt can be generated upon detection of a valid edge. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 13 ice3: interrupt request enable bit (input capture 3) ? this bit is used to enable input capture interrupt request for input capture 3. ? while 1 is written to this bit, an input capture interrupt is generated when the interrupt flag (icp3) is set. bit 12 ice2: interrupt request enable bit (input capture 2) ? this bit is used to enable input capture interrupt request for input capture 2. ? while 1 is written to this bit, an input capture interrupt is generated when the interrupt flag (icp2) is set. bit 11 bit 10 eg31, eg30: edge selection bit (input capture 3) ? these bits are used to specify the valid edge polarity of an external input for input capture 3. ? these bits are also used to enable input capture operation. bit 9 bit 8 eg21, eg20: edge selection bit (input capture 2) ? these bits are used to specify the valid edge polarity of an external input for input capture 2. ? these bits are also used to enable input capture operation.
308 chapter 12 multi-function timer MB90560 series n capture control register (ics01) figure 12.3.3.2-2 capture control register (ics01) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 000068 h icp1 icp0 ice1 ice0 eg11 eg10 eg01 eg00 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w eg01 eg00 edge selection bit (input capture 0) 0 0 no edge detection (stop) 01 rising edge detection 10 falling edge detection 11 both edges detection eg11 eg10 edge selection bit (input capture 1) 0 0 no edge detection (stop) 01 rising edge detection 10 falling edge detection 11 both edges detection ice0 interrupt request enable bit (input capture 0) 0 disable interrupt request 1 enable interrupt request ice1 interrupt request enable bit (input capture 1) 0 disable interrupt request 1 enable interrupt request icp0 interrupt request flag bit (input capture 0) read write 0 no valid detected clear this bit 1 valid detected no effect icp1 interrupt request flag bit (input capture 1) read write 0 no valid detected clear this bit 1 valid detected no effect r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 309 table 12.3.3.2-2 capture control register (ics01) bit function bit 7 icp1: interrupt request flag bit (input capture 1) ? this bit is used as interrupt request flag for input capture 1. ? 1 is written to this bit upon detection of a valid edge of an external input pin. ? while the interrupt enable bit (ice1) is set, an interrupt can be generated upon detection of a valid edge. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 6 icp0: interrupt request flag (input capture 0) ? this bit is used as interrupt request flag for input capture 0. ? 1 is written to this bit upon detection of a valid edge of an external input pin. ? while the interrupt enable bit (ice0) is set, an interrupt can be generated upon detection of a valid edge. ? writing 0 will clear this bit. ? writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 5 icp1: interrupt request enable bit (input capture 1) ? this bit is used to enable input capture interrupt request for input capture 1. ? while 1 is written to this bit, an input capture interrupt is generated when the interrupt flag (icp1) is set. bit 4 icp0: interrupt request enable bit (input capture 0) ? this bit is used to enable input capture interrupt request for input capture 0. ? while 1 is written to this bit, an input capture interrupt is generated when the interrupt flag (icp0) is set. bit 3 bit 2 eg11, eg10: edge selection bit (input capture 1) ? these bits are used to specify the valid edge polarity of an external input for input capture 1. ? these bits are also used to enable input capture operation. bit 1 bit 0 eg01, eg00: edge selection bit (input capture 0) ? these bits are used to specify the valid edge polarity of an external input for input capture 0. ? these bits are also used to enable input capture operation.
310 chapter 12 multi-function timer MB90560 series 12.3 registers of multi-function timer 12.3.4 register of 8/16-bit ppg timer this section describe registers of 8/16-bit ppg timer, that are ppg reload timer x 6, ppg control register x 6 and ppg clock control register x 3. n 8/16-bit ppg timer registers figure 12.3.4-1 registers of 8/16-bit ppg timers 15 14 13 12 11 10 9 8 bit number ppg reload register (upper) 7 6 5 4 3 2 1 0 bit number ppg reload register (lower) address: ch0 000039 h ch1 00003b h ch2 000041 h ch3 000043 h ch4 000049 h ch5 00004b h prlh0~5 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write address: ch0 000038 h ch1 00003a h ch2 000040 h ch3 000042 h ch4 000048 h ch5 00004a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write prll0~5 15 14 13 12 11 10 9 8 bit number ppg1/3/5 control register 7 6 5 4 3 2 1 0 bit number ppg0/2/4 control register address: ch1 00003d h ch3 000045 h ch5 00004d h ppgc1/3/5 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 1 r/w 0 initial value read/write r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 1 r/w 0 initial value read/write ppgc0/2/4 address: ch0 00003c h ch2 000044 h ch4 00004c h pen1 sst1 poe1 pie1 puf1 md01 md00 pen0 sst0 poe0 pie0 puf0 7 6 5 4 3 2 1 0 bit number ppg clock control register r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w x initial value read/write pcs01/23/45 address: ch0,1 00003e h ch2,3 000046 h ch4,5 00004e h pc12 pc11 pc10 pc02 pc01 pc00 pos1 pos0 reserved reserved r/w x
MB90560 series chapter 12 multi-function timer 311 12.3.4 registers of 8/16-bit ppg timer 12.3.4.1 ppg reload register (prlh0~5, prll0~5) ppg reload registers (prlh0~5, prll0~5) are 8-bit register that is used to store the reload values for the down counter. n ppg reload register (prlh0~5, prll0~5) figure 12.3.4.1-1 ppg reload register (prlh0~5, prll0~5) these are 8-bit registers that is used to store the reload values for the down counter. their function are described below. these registers are readable and writable. note: in 8+8-bit ppg mode, setting different values in prll and prlh of ch0/2/4 may cause the ppg waveform of ch1/3/5 to vary in each cycle. write the same value to prll and prlh of ch0/2/4. table 12.3.4.1-1 function of ppg reload registers register name function prll0-5 store the lower byte of reload value prlh0~5 store the upper byte of reload value 15 14 13 12 11 10 9 8 bit number ppg reload register (upper) 7 6 5 4 3 2 1 0 bit number ppg reload register (lower) address: ch0 000039 h ch1 00003b h ch2 000041 h ch3 000043 h ch4 000049 h ch5 00004b h prlh0~5 r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write address: ch0 000038 h ch1 00003a h ch2 000040 h ch3 000042 h ch4 000048 h ch5 00004a h r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write prll0~5
312 chapter 12 multi-function timer MB90560 series 12.3.4 registers of 8/16-bit ppg timer 12.3.4.2 ppg control register (ppgc0~5) ppg control registers (ppgc0~5) are used to control the operation mode, interrupt request enable, interrupt request flag, output enable, start selection, operation enable and the output level polarity for ppg0~5 timers. n ppg1/3/5 control register (ppgc1/3/5) figure 12.3.4.2-1 ppg1/3/5 control register (ppgc1/3/5) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value ch1: 00003d h ch3: 000045 h ch5: 00004d h pen1 sst1 poe1 pie1 puf1 md01 md00 reserved 00000001 b r/w r/w r/w r/w r/w r/w r/w r/w m0d1 mod0 ppg1/3/5 timer operation mode bit 0 0 8-bit ppg 2ch independent mode 01 8 + 8-bit ppg mode 10 reserved (setting inhibited) 11 16-bit ppg 1ch mode puf1 interrupt request flag bit for ppg1/3/5 read write 0 no overflow of ppg1/3/5 timer clear this bit 1 overflow of ppg1/3/5 timer no effect pie1 interrupt request enable bit for ppg1/3/5 0 disable interrupt request for ppg1/3/5 1 enable interrupt request for ppg1/3/5 poe1 output enable bit for ppg1/3/5 0 general-purpose port (p42/44/46) 1 ppg output port for ppg1/3/5 sst1 start select bit for ppg1/3/5 0 ppg1/3/5 will be operated when pen1=1. 1 ppg1/3/5 will be operated when gate=h. pen1 operation enable bit for ppg1/3/5 0 sop operation for ppg1/3/5 1 start operation for ppg1/3/5 r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 313 table 12.3.4.2-1 ppg1/3/5 control register (ppgc1/3/5) bit bit function bit 15 pen1: operation enable bit for ppg1/3/5 ? this bit is used to enable the operation of ppg1/3/5. ? when sst1=0, writing 1 will start the ppg1/3/5 operation and writing 0 will stop the operation. ? when sst1=1, setting this bit cause no effect. bit 14 sst1: start select bit for ppg1/3/5 ? this bit is used to select the start condition of ppg1/3/5. ? after writing 0 to this bit, the ppg1/3/5 will be operated depending on the pen1 bit. ? writing 1 to pen1 bit while this bit is 1, ppg1/3/5 will be operated while the gate signal is h. bit 13 poe1: output enable bit ? this bit is used to select either the pulse output of ppg1/3/5 or general-purpose port. bit 12 pie1: interrupt request enable bit for ppg1/3/5 ? this bit is used to enable an interrupt request for ppg1/3/5. ? while 1 is written to this bit, ppg1/3/5 is generated an interrupt when the interrupt flag (puf1) is set. bit 11 puf1: interrupt request flag bit for ppg1/3/5 ? this bit is used as an interrupt request flag for ppg1/3/5 underflow. ? in 8-bit ppg 2ch independent mode or 8+8-bit ppg mode, 1 is written to this bit when an underflow occurs as a result of the ch0/2/4 counter value becoming between 00h and ffh. ? in 16-bit ppg 1ch mode, 1 is written to this bit when an underflow occurs as a result of the ch1/ch0, ch2/ch3 and ch4/ ch5 counter value becoming between 0000h and ffffh. ? writing 0 will clear this bit. writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 10 bit 9 md01, md00: ppg1/3/5 timer operation mode bit ? this bit is used to select operation mode of ppg1/3/5. note: do not set 10 in this bit. note: when these bits are set to 01, do not set the ppgc0/2/4:pen0 and ppgc1/3/5:pen1 bits to 01. it is recommended that the pen0 and pen1 bits be set to 11 or 00. when mod1 and mod0 are set to 11, rewrite ppgc0/2/4 and ppgc1/3/5 by word transfer to set the pen0 and pen1 bits to 11 or 00 . note: when these bits are set to 01, be sure to set the ppgc0/2/4:pen0 bit to 1 before setting the ppgc1/ 3/5:sst1 bit to 1. when the pen0 bit is set to 0, be sure to set the sst1 bit to 0 in advance. when mod1 and mod0 are set to 11, rewrite ppgc0/2/4 and ppgc1/3/5 by word transfer to set the sst0 and sst1 bits to 11 or 00. bit 8 reserved bit ? always setting this bit to 1 when setting ppgc1/3/5
314 chapter 12 multi-function timer MB90560 series n ppg0/2/4 control register (ppgc0/2/4) figure 12.3.4.2-2 ppg0/2/4 control register (ppgc0/2/4) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value ch0: 00003c h ch2: 000044 h ch4: 00004c h pen0 sst0 poe0 pie0 puf0 pos1 pos0 reserved 00000001 b r/w r/w r/w r/w r/w r/w r/w r/w pos0 pulse polarity bit for ppg0/2/4 0 positive pulse 1 negative pulse (reverse mode) pos1 pulse polarity bit for ppg1/3/5 0 positive pulse 1 negative pulse (reverse mode) puf0 interrupt request flag bit for ppg0/2/4 read write 0 no overflow of ppg0/2/4 timer clear this bit 1 overflow of ppg0/2/4 timer no effect pie0 interrupt request enable bit for ppg0/2/4 0 disable interrupt request for ppg0/2/4 1 enable interrupt request for ppg0/2/4 poe0 output enable bit for ppg0/2/4 0 general-purpose port (p41/43/45) 1 ppg output port for ppg0/2/4 sst0 start select bit for ppg0/2/4 0 ppg0/2/4 will be operated when pen1=1. 1 ppg0/2/4 will be operated when gate=h. pen0 operation enable bit for ppg0/2/4 0 sop operation 1 start operation r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 315 table 12.3.4.2-2 ppg0/2/4 control register (ppg0/2/4) bit function bit 7 pen0: operation enable bit for ppg0/2/4 ? this bit is used to enable the operation of ppg0/2/4. ? when sst1=0, writing 1 will start the ppg0/2/4 operation and writing 0 will stop the operation. ? when sst1=1, setting this bit cause no effect. bit 6 sst0: start select bit for ppg0/2/4 ? this bit is used to select he start condition of ppg0/2/4. ? after writing 0 to this bit, the ppg0/2/4 will be operated depending on the pen1 bit. ? writing 1 writing 1 to pen0 bit while this bit is 1, ppg0/2/4 will be operated while the gate signal is h. bit 5 poe0: output enable bit ? this bit is used to select either the pulse output of ppg0/2/4 or general-purpose port. bit 4 pie0: interrupt request enable bit for ppg0/2/4 ? this bit is used to enable an interrupt request for ppg0/2/4. ? while '1' is written to this bit, ppg0/2/4 is generated an interrupt when the interrupt flag (puf0) is set. bit 3 puf0: interrupt request flag bit for ppg0/2/4 ? this bit is used as an interrupt request flag for ppg0/2/4 underflow. ? in 8-bit ppg 2ch independent mode or 8-bit prescaler + 8-bit ppg mode, '1' is written to this bit when an underflow occurs as a result of the ch0/2/4 counter value becoming between 00h and ffh. ? in 16-bit ppg 1ch mode, '1' is written to this bit when an underflow occurs as a result of the ch1/ch0, ch2/ch3 and ch4/ ch5 counter value becoming between 0000h and ffffh. ? writing 0 will clear this bit. writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 2 pos1: pulse polarity selection bit ? this bit is used to select the pulse polarity to the external pin for ppg1/3/5 bit 1 pos1: pulse polarity selection bit ? this bit is used to select the pulse polarity to the external pin for ppg0/2/4. bit 0 reserved bit ? always setting this bit to 1 when setting ppgc0/2/4
316 chapter 12 multi-function timer MB90560 series 12.3.4 registers of 8/16-bit ppg timer 12.3.4.3 ppg clock control register (pcs01/23/45) ppg clock control registers (pcs01/23/45) are used to control the operating clock frequency for ppg0~5. n ppg clock control register (pcs01/23/45) figure 12.3.4.3-1 ppg0/1/2/3/4/5 clock control register (pcd01/23/45) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value ch0,1: 00003e h ch2,3: 000046 h ch4,5: 00004e h pc12 pc11 pc10 pc02 pc01 pc00 000000xx b r/w r/w r/w r/w r/w r/w pc02 pc01 pc00 operation clock for ch0/2/4 0 0 0 f (62.5 ns, f =16mhz) 001 f /2 (125 ns, f =16mhz) 010 f /4 (250 ns, f =16mhz) 011 f /8 (500 ns, f =16mhz) 100 f /16 (1 m s, f =16mhz) 101 f /32 (2 m s, f =16mhz) 110 f /64 (4 m s, f =16mhz) 111 input clock from timebase trimmer f : machine clock pc12 pc11 pc10 operation clock for ch1/3/5 0 0 0 f (62.5 ns, f =16mhz) 001 f /2 (125 ns, f =16mhz) 010 f /4 (250 ns, f =16mhz) 011 f /8 (500 ns, f =16mhz) 100 f /16 (1 m s, f =16mhz) 101 f /32 (2 m s, f =16mhz) 110 f /64 (4 m s, f =16mhz) 111 input clock from timebase trimmer f : machine clock x : indeterminate r/w : read and write : initial value : not used
MB90560 series chapter 12 multi-function timer 317 table 12.3.4.3-1 ppg0/1/2/3/4/5 clock control register (ppg0/2/4) bit function bit 7 bit 6 bit 5 pc12~0: operation clock control bit for ppg1/3/5 ? these bits select the ppg1/3/5 down counter operation clock. note: in 8 + 8-bit ppg mode or in 16-bit ppg mode, ppg1/3/ 5 operates in response to a counter clock from ppg0/ 2/4. therefore, the pcs12~0 bits are invalid. bit 4 bit 3 bit 2 pc02~0: operation clock control bit for ppg0/2/4 ? these bits select the ppg0/2/4 down counter operating clock. bit 1 bit 0 unused bit ? the read values are indeterminate. ? writing to these bits have no effect on the operation.
318 chapter 12 multi-function timer MB90560 series 12.3 registers of multi-function timer 12.3.5 registers of waveform generator this section describe registers of waveform generator and their details. those registers are 8-bit reload register x 3, 8-bit timer control register x 3, waveform control register x 1. n waveform generator registers figure 12.3.5-1 registers of waveform generator 15 14 13 12 11 10 9 8 bit number 8-bit timer control register 7 6 5 4 3 2 1 0 bit number 8-bit reload register address: ch0 000051 h ch1 000053 h ch2 000055 h dtcr0/1/2 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write tmrr0/1/2 address: ch0 000050 h ch1 000052 h ch2 000054 h dmod gten pgen tmif tmie tmd2 tmd1 tmd0 address: 000056 h 76543 2 10 waveform control register sigcr bit number r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 r/w 0 initial value read/write dtie dtil nrsl dck2 dck1 dck0 pgs1 pgs0
MB90560 series chapter 12 multi-function timer 319 12.3.5 registers of waveform generator 12.3.5.1 8-bit reload register (tmrr0/1/2) 8-bit reload registers hold the compare value of 8-bit timers. n 8-bit reload registers (tmrr0/12) figure 12.3.5.1-1 8-bit reload registers (tmrr0/1/2) these registers is used to store the comparison value of 8-bit timers. these registers will be reloaded when the 8-bit timer is started to operate. therefore, if the value is re-written into those registers during timer operation, those value will be valid at the next timer initiation/operation. in dead-time timer mode, these registers are used to set the non-overlap time. ? non-overlap time = (set value +1) x selected clock. note: the value of 00 h cannot be set. in timer mode, these registers are used to set the gate time for ppg timer operation. ? gate time = (set value +1) x selected clock. note: the value of 00 h cannot be set. 7 6 5 4 3 2 1 0 bit number 8-bit reload register r/w x r/w x r/w x r/w x r/w x r/w x r/w x r/w x initial value read/write tmrr0/1/2 address: ch0 000050 h ch1 000052 h ch3 000054 h
320 chapter 12 multi-function timer MB90560 series 12.3.5 registers of waveform generator 12.3.5.2 8-bit timer control register (dtcr0/1/2) 8-bit timer control registers (dtcr0/1/2) are used to control the operation mode, interrupt request enable, interrupt request flag, ppg output enable, gate signal enable and output level polarity for the waveform generator. n 8-bit timer control register (dtcr0/1/2) figure 12.3.5.2-1 8-bit timer control register (dtcr0/1/2) address bit 15 bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 initial value ch0: 000051 h ch1: 000053 h ch2: 000055 h dmod gten pgen tmif tmie tmd2 tmd1 tmd0 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w tmd2 tmd1 tmd0 operation mode bit 0 0 0 waveform generator is stopped. 8-bit timer can be used as reload timer. 001 ppg timer output pulse while rt signal is h. the ppg timer that outputs pulse must be set in advance in the waveform control register. 010 the rising edge of each rt signal will trigger 8- bit timer to start. ppg will run until the 8-bit timer stopped. (timer mode) 100 generate non-overlap signal by rt signal. (dead-time timer mode) 111 rt signal acts as a gate signal for ppg timers. ppg generates non-overlap signal. (dead-time timer mode) tmie interrupt request enable bit 0 disable an interrupt when the 8-bit timer underflow 1 enable an interrupt when the 8-bit timer underflow tmif interrupt request flag bit read write 0 no counter underflow detected clear this bit 1 counter underflow detected no effect pgen ppg output enable bit 0 disable ppg output 1 enable ppg output gten gate signal enable bit 0 disable gate signal output (asynchronous mode) 1 enable gate signal output (synchronous mode) dmod output polarity control bit 0 positive level output 1 negative level output r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 321 table 12.3.5.2-1 8-bit timer control registers (dtcr0/1/2) bit bit function bit 15 dmod: output polarity control bit ? this bit is used to set the output polarity when using 8-bit timer as dead-time timer. ? by setting this bit, it is possible to invert the output polarity. ? if 8-bit timer is not set for dead-time timer operation (bit11:tmd2=0), setting this bit has no effect. bit 14 gten: gate signal enable bit ? this bits is used to enable the gate signal output for ppg timer operation. bit 13 pgen: ppg output enable bit ? this bit is used to enable the output of ppg timers to rto0~5 pins. bit 12 tmif: interrupt request flag bit ? this bit is used as an interrupt request flag for 8-bit timers. ? this bit will be set to 1 when 8-bit timer is underflow. ? writing 0 will clear this bit. writing 1 has no effect. ? in read-modify-write operation, 1 is always read. bit 11 tmie: interrupt request enable bit ? this bit is used as the start bit and the interrupt enable bit for the 8-bit timer. ? writing 1 to this bit will start the operation for the 8-bit timer. ? when this bit is 1 and the interrupt flag bit (bit12:timf) is 1, an interrupt is generated. note: bit2~0:tmd2~0 is 000b is the condition for using the 8-bit timer as reload timer. bit 10 bit 9 bit 8 tmd2~0: operation mode bit ? these bit are used to select the operation mode of the waveform generator. note: in ppg timers, the channel is set by waveform control register. note: setting tmd2:0 other than 000, 0001, 010, 100 and 111 is prohibited. other setting will cause an error. when operating in dead time timer mode, the operation mode of rto1/3/5 must set by 2ch mode.
322 chapter 12 multi-function timer MB90560 series 12.3.5 registers of waveform generator 12.3.5.3 waveform control register (sigcr) waveform control register is used to control how the ppg0~5 output to rto0~5, operating clock frequencies, noise cancelling function enable, dtti input enable and dtti input polarity. n waveform control register (sicgcr) figure 12.3.5.3-1 waveform control register (sigcr) address bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 initial value 000056 h dtie dtil nrsl dck2 dck1 dck0 pgs1 pgs0 00000000 b r/w r/w r/w r/w r/w r/w r/w r/w pgs1 pgs0 operation mode ppg0~5 output thru rto0~5 table rto0 rto1 rto2 rto3 rto4 rto5 0 0 8bit x 6 ch ppg0 ppg1 ppg2 ppg3 ppg4 ppg5 01 8-bit x 3 ch ppg1 ppg1 ppg3 ppg3 ppg5 ppg5 10 8-bit x 2 ch ppg1 ppg3 ppg1 ppg3 ppg1 ppg3 11 8-bit x 1 ch ppg1 ppg1 ppg1 ppg1 ppg1 ppg1 dck2 dck1 dck0 operating clock selection bit 0 0 0 f (62.5 ns, f =16mhz) 001 f /2 (125 ns, f =16mhz) 010 f /4 (250 ns, f =16mhz) 011 f /8 (500 ns, f =16mhz) 100 f /16 (1 m s, f =16mhz) 101 f /32 (2 m s, f =16mhz) 110 f /64 (4 m s, f =16mhz) 111 prohibited f : machine clock nrsl noise cancelling function selection bit 0 dtti input is not go thru the noise cancelling circuit. 1 dtti input is not go thru the noise cancelling circuit. dtil dtti input polarity selection bit 0 0 input 1 1 input dtie dtti input enable bit 0 disable dtti input 1 enable dtti input r/w : read and write : initial value
MB90560 series chapter 12 multi-function timer 323 table 12.3.5.3-1 waveform control register (sigcr) bit function bit 7 dtie: dtti input enable bit ? this bit is used to enable to receive dtti input to control the output level of rto0~5 pin. bit 6 dtil: dtti input polarity selection bit ? this bit is used to select the level polarity of dtti input to control the output level of rto0~5 pin. bit 5 nrsl: noise cancelling function selection bit ? this bit is used to select the noise cancelling function. ? noise cancelling circuit will receive dtti input signal when the valid level is held until the counter overflows. the counter is 2- bit counter which is operated by the valid level input. note: to cancel the noise pulse width, it takes approximately 4 machine cycles. when the noise cancelling circuit is selected, the input will become invalid if the internal clock is stopped, for example in stop mode. bit 4 bit 3 bit 2 dck2~0: operating clock selection bit ? these bits are used to select the operating clock for the 8-bit timer. bit 1 bit 0 pgs1, pgs0: ppg output to rto selection bit ? these bits are to select which the ppg timer is used to output pulses directly to rto0~5. ? when the 8-bit timer control register, bit 14:gten is set to 1, gate signal (synchronized mode) will be output to the corresponding ppg. note: the operation mode in the table on the figure 12.3.5.3- 1 is written with ppg timer setting, so the corresponding ppg timer output and operation start/ stop control is possible when setting 16-bit mode for the ppg timer. also, ppg output is possible without using ppg timer gate function (asynchronized mode), but ppg timer must be operating in software initiation.
324 chapter 12 multi-function timer MB90560 series 12.4 operation of multi-function timer this section describes the operation of the multifunctional timer unit. n operation of multifunctional timers l 16-bit free-running timer the 16-bit free-running timer starts counting up from counter value 0000 h after a reset has been completed. the counter value is used as the reference time for 16-bit output compare and 16-bit input capture. l 16-bit output compare the output compare unit is used to compare the value set in the specified compare register with the value of the 16-bit free-running timer. if a match is detected, the interrupt flag is set and the output level is inverted l 16-bit input capture the input capture unit is used to detect a specified valid edge. if a valid edge is detected, the interrupt flag is set and the value of 16-bit free-run timer is fetched and stored into the capture register. l 8/16-bit ppg timer this ppg timer has two channels of ppg units each of which is 8 bits long. the timer can operate in normal two-channel independent mode. in addition, by connecting the two channels, it can also operate in two other modes, i.e., 8 + 8-bit ppg mode and 16-bit ppg mode. l waveform generator the waveform generator can generate various timing waveforms using the real-time outputs (rt0 to rt5), 8/16-bit ppg timer, and 8-bit timer.
MB90560 series chapter 12 multi-function timer 325 memo
326 chapter 12 multi-function timer MB90560 series 12.4 operation of multi-function timer 12.4.1 operation of 16-bit free-run timer the 16-bit free-running timer starts counting up from counter value 0000 h after a reset has been completed. the counter value is used as the reference time for 16-bit output compare and 16-bit input capture. n 16-bit free-run timer operation the counter value is cleared in the following conditions: ? when an overflow has occurred. ? when a match with output compare clear register is detected. (mode setting is necessary.) ? when 1 is written to the clr bit of the tccs register during operation. ? when 0000 h is written to the tcdt register during stop. ? reset an interrupt can be generated when an overflow occurs or when the counter is cleared due to a match with compare clear register. (compare match interrupts can be used only in an appropriate mode.) figure 12.4.1-1 clearing the counter by an overflow figure 12.4.1-2 clearing the counter upon a match with compare clear register ffff h bfff h 7fff h 3fff h 0000 h counter value overflow time reset interrupt ffff h bfff h 7fff h 3fff h 0000 h bfff h counter value match time reset compare clear interrupt match register value
MB90560 series chapter 12 multi-function timer 327 n 16-bit free-run timer timing the 16-bit free-run timer is incremented based on the input clock (internal or external clock). when external clock is selected, the 16-bit free-run timer counts up at a rising edge. figure 12.4.1-3 16-bit free-run timer count timing the counter can be cleared upon a reset, software clear, or a match with compare clear register. by a reset or software clear, the counter is immediately cleared. by a match with compare clear register, the counter is cleared in synchronization with the count timing. figure 12.4.1-4 16-bit free-run timer clear timing n n+1 counter value external clock count clock input n n 0000h compare register value compare match counter value
328 chapter 12 multi-function timer MB90560 series 12.4 operation of multi-function timer 12.4.2 operation of 16-bit output compare the output compare unit is used to compare the value set in the specified compare register with the value of the 16-bit free-running timer. if a match is detected, the interrupt flag is set and the output level is inverted. n 16-bit output compare operation a) compare operation can be performed for individual channel (cmod=0) figure 12.4.2-1 sample output waveform when compare registers 0 and 1 are used individually when the initial output value is 0. ffff h bfff h 7fff h 3fff h 0000 h rto0 rto1 bfff h 7fff h counter value time reset compare register 0 compare register 1 compare 0 compare 1 value value interrupt interrupt
MB90560 series chapter 12 multi-function timer 329 b) output level can be changed by using a pair of compare registers (cmod=1) figure 12.4.2-2 sample output waveform when compare registers 0 and 1 are used in a pair when the initial output value is 0. ffff h bfff h 7fff h 3fff h 0000 h rto0 rto1 bfff h 7fff h counter value time reset compare register 0 compare register 1 compare 0 compare 1 value value interrupt interrupt
330 chapter 12 multi-function timer MB90560 series n 16-bit output compare timing l output levels can be changed by using two pairs of compare registers. (at cmod = 1) when the free-running timer matches the value set in the compare register, the output compare unit generates a compare match signal to invert the output and generate an interrupt. when a compare match occurs, the output is inverted in synchronization with the count timing of the counter. no comparison is performed with the counter value during replacement of the compare registers.by using 2 compare registers, output level can be changed (1 when cmod=1) note: when the compare register is updated, comparison with the counter value is not performed. figure 12.4.2-3 compare operation upon update of compare registers figure 12.4.2-4 compare interrupt timing figure 12.4.2-5 output pin change timing n m n+1 n+2 n+3 l n+1 n+3 counter value no match signal is generated. compare clear compare 0 stop compare 1 stop compare clear register 0 value register 0 write compare clear compare clear register 1 value register 1 write n n n+1 counter value compare compare interrupt value register match n n+1 n n n+1 counter value compare compare pin output register value match signal
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332 chapter 12 multi-function timer MB90560 series 12.4 operation of multi-function timer 12.4.3 operation of 16-bit input capture the input capture unit is used to detect a specified valid edge. if a valid edge is detected, the interrupt flag is set and the value of 16-bit free-run timer is fetched and stored into the capture register. n 16-bit input capture operation figure 12.4.3-1 sample input capture timing ffff h bfff h 7fff h 3fff h 0000 h in1 in0 3fff h bfff h 7fff h 7fff h counter value reset capture register 0 capture register 1 capture register capture 0 interrupt capture 1 interrupt capture example example in example undefined undefined undefined note: capture 0: rising edge capture 1: falling edge capture example: both edges interrupt is generated with another valid edge interrupt is cleared time by software interrupt
MB90560 series chapter 12 multi-function timer 333 n 16-bit input capture input timing figure 12.4.3-2 16-bit input capture timing for input signals n n+1 n+1 counter value input capture capture signal capture register interrupt valid edge input machine clock
334 chapter 12 multi-function timer MB90560 series 12.4 operation of multi-function timer 12.4.4 operation of 8/16-bit ppg timers this section describe operation and timing of 8/16-bit ppg timers. the operation and timing of ch0/ch1 will be explained here. the operation and timing of ch2 and ch4 is the same as ch 0 and the operation and timing of ch 3 and ch 5 is the same as ch 1. two channels of ppg time can be used in three modes: independent two-channel mode, 8- bit prescaler + 8-bit ppg mode, and single-channel 16-bit ppg mode. each of the 8-bit ppg units has two eight-bit reload registers. one reload register is for the l side (prll) and the other is for the h side (prlh). the values written in these registers are reloaded into the 8-bit down counter (pcnt), from the l side and h side in turn. thus, the values are decremented for each count clock, and the pin output (ppg) value is inverted upon a reload caused by a counter underflow. this operation results in l-wide or h-wide pulse outputs, corresponding to the reload register value. further more the output polarity can be selected by software. the operation is started and resumed by writing data in the corresponding register bit. the table 12.4.4-1 below lists the relationship between the reload operation and pulse outputs. when 1 is set in bit 4 (pie0) of ppgc0 or in bit 12 (pie1) of ppgc1, an interrupt request is output upon an underflow from 00 h to ff h (or underflow from 0000 h to ffff h in 16-bit ppg mode) of each counter. n operation mode this block can be used in three modes: independent two-channel mode, 8-bit prescaler + 8-bit ppg mode, and single-channel 16-bit ppg mode. ? 8-bit 2ch independent mode in this mode, the two channels of 8-bit ppg units operate independently. the ppg0 pin is connected to the ch0 ppg output and the ppg1 pin is connected to the ch1 ppg output. ? 8 + 8-bit ppg mode in this mode, ch0 is used as an 8-bit prescaler while the count in ch1 is based on underflow outputs from ch0. thus, 8-bit ppg waveforms can be output at any cycles. the ppg0 is connected to the ch0 prescaler output and the ppg1 pin is connected to the ch1 ppg output. ? 16-bit ppg mode in this mode, ch0 and ch1 are connected and used as a single 16-bit ppg. the ppg0 and ppg1 pins are connected to the 16-bit ppg output. table 12.4.4-1 reload operation and pulse output reload operation pin output change positive polarity negative polarity prlh ? pcnt ppg0/1 [0 ? 1] - rise ppp0/1 [1 ? 0] fall prll ? pcnt ppp0/1 [1 ? 0] fall ppg0/1 [0 ? 1] - rise
MB90560 series chapter 12 multi-function timer 335 n ppg output operation writing '1' to bit7 (pen0) of ppgc0 register will activate ch0 ppg timer to start counting when bit6 (sst0) of ppgc0 register is 0 (software activation). alternately, gate signal becoming h will activate ch0 ppg timer to start counting when bit6 (sst0) of ppgc0 register is 1 (hardware activation). similarly, writing '1' to bit15 (pen1) of ppgc1 register will activate ch1 ppg timer to start counting when bit14 (sst1) of ppgc1 register is 0 (software activation). alternately, gate signal becoming h will activate ch1 ppg timer to start counting when bit14 (sst1) of ppgc1 register is 1 (hardware activation). once the operation has started, counting is terminated by writing '0' to bit 7 (pen0) of ppgc0 or in bit 15 (pen1) of ppgc1, or when the gate signal changes to l. once the counting is terminated, the pulse output is maintained at the l level when it is positive polarity output. (the pulse output is maintained at the h level when it is negative polarity output.) in 8 + 8-bit ppg mode, do not set ch1 to be in operation while ch0 operation is stopped. for software activation of 16-bit ppg mode, ensure to set bit 7 (pen0) of ppgc0 register and bit 15 (pen1) of ppgc1 register simultaneously to start or stop the ppg timer. the figure 12.4.4-1 below is a diagram of ppg output operation. during ppg operation, a pulse wave is continuously output at a frequency and duty ratio (the ratio of the h-level period of the pulse wave to the l-level period). ppg continues operation until stop is specified explicitly. figure 12.4.4-1 ppg output operation, output waveform pen ppgx t x (l+1) t x (h+1) l : prll value h : prlh value t : input from peripheral clock ( ? , ? /4, ? /16) or timer base counter (depending on the clock selection by ppgc) output pin starts operation based on pen (from l side). when activate ppg timer by software when activate ppg timer by hardware gate ppgx output pin starts operation based on gate signal h sst t x (l+1) t x (h+1)
336 chapter 12 multi-function timer MB90560 series n reload value and pulse width relation the pulse width of the output is determined by multiplying the reload register value + 1 by the count clock cycle. note that when the reload register value is 00 h during 8-bit ppg operation or 0000 h during 16-bit ppg operation, the pulse width is equivalent to one count clock cycle. in addition, note that when the reload register value is ff h during 8-ppg operation, the pulse width is equivalent to 256 count clock cycles. when the reload register value is ffff h during 16-bit ppg operation, the pulse width is equivalent to 65,536 count clock cycles. the formula of pulse width calculation is given below. note: the above formula is for the positive output polarity. the p l and p h setting will be the other way around when negative polarity is used. n count clock selection the count clock used for the operation of this block is supplied from a machine clock or time base timer. the count clock can be selected from 8 types. the count clock for ch 0 ppg timer is selected by setting bit 4 to 2 (pc02 to 0) of the pcs01 register and the count clock for ch1 ppg timer is selected by setting bit 7 to 5 (pc12 to 0) of the pcs01 register. the clock is selected from 1/64 to 1 times of the machine clock and time base timer input. however, in 8 + 8-bit ppg mode or 16-bit ppg mode, the ch1 ppg timer is operated by receiving a count clock from ch0 ppg timer. therefore bit 7 to 5 (pc12 to 0) of the pcs01 register are invalid. note: when the time base counter input is used, the first count cycle after a trigger or a stop may be shifted. the cycle may also be shifted if the time base counter is cleared during operation of this module. in 8 + 8-bit ppg mode, if ch1 is activated while ch0 is in operation and ch1 is stopped, the first count cycle may be shifted. l:prll value h: value t : input clock cycle p l : high pulse width p h : low pulse width p l = t x (l+1) p h = t x (h+1)
MB90560 series chapter 12 multi-function timer 337 n pulse pin output control the pulses generated by the operation of the 8/16-bit ppg timer can be output to external pins ppg0 and ppg1. the external pin output enable can be done by setting bit 5 (poe0) of the ppgc0 register (ppg0 control register) for the ppg0 pin and setting bit 13 (poe1) of the ppgc1 register (ppg1 control register) for the ppg1 pin. when 0 is written to these bits (initial value), the pulses are not output to the corresponding external pins; the pins will work as general-purpose ports. in 16-bit ppg mode, the same waveform is output from ppg0 and ppg1. thus, the same output can be obtained by enabling any one external pin. in 8 + 8-bit ppg mode, the 8-bit prescaler (ch0 ppg timer) toggle output waveform is output to ppg0, while the 8-bit ppg waveform (ch1 ppg timer) is output to ppg1. the figure 12.4.4-2 below is a diagram of output waveforms in this mode. figure 12.4.4-2 8+8 ppg output operation waveform l0 : ch0 prll value and ch0 prlh value l1 : ch1 prll value h1 : ch1 prlh value t : input clock cycle p h 0 : ppg0 high pulse width p l 0 : ppg0 low pulse width p h 1 : ppg1 high pulse width p l 1 : ppg1 low pulse width p h 0 p l 0 p h 1 p l 1 ppg0 ppg 1 p l 0 = t x (l0+1) p h 0 = t x (l0+1) p l 1 = t x (l0+1) x (l1+1) p h 1 = t x (l0+1) x (h1+1) note: set the same value in ch0 prll and ch0 prlh.
338 chapter 12 multi-function timer MB90560 series n interrupts an interrupt request is generated when the reload value is counted out and a underflow occurs. in 8-bit ppg 2ch independent mode or 8 + 8-bit ppg mode, an interrupt request is generated by a underflow in each counter. in 16-bit ppg mode, puf0 and puf1 are set simultaneously by a underflow in the 16-bit counter. therefore, enable only pie0 or pie1 to unify the interrupt causes. in addition, simultaneously clear the interrupt causes for puf0 and puf1. n reload register write timing in any operation mode other than 16-bit ppg mode, it is recommended to use a word transfer instruction to write data in reload registers prll and prlh. if two byte transfer instructions are used to write a data item to these registers, a pulse of unexpected width may be output depending on the timing. figure 12.4.4-3 write timing chart assume that prll is updated from a to c before point ? in the time chart above, and prlh is updated from b to d after point ? . since the prl values at point ? are prll=c and prlh=b, a pulse of l side count value c and h side count value b is output only once. similarly, to write data in prl of ch0 and ch1 in 16-bit ppg mode, use a long word transfer instruction, or use word transfer instructions in the order of ch0 and then ch1. in this mode, the data is only temporarily written to ch0 prl. then, the data is actually written into ch0 prl when the ch1 prl is written to. in any operation mode other than 16-bit ppg mode, ch0 and ch1 prl are written independently. figure 12.4.4-4 prl write operation block diagram ppg0 bbcc a a d d cb ? ch0 prl write data ch0 write in a mode temporary latch transferred in ch1 prl write data ch0 prl ch1 write ch1 prl synchronization with ch1 write in 16-bit ppg mode other than 16-bit ppg mode
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340 chapter 12 multi-function timer MB90560 series 12.4.4 operation of waveform generator 12.4.5 operation of waveform generator waveform generator can produce various waveform such as dead-time, by using the realtime outputs (rt0~5), 8/16-bit ppg timers and 8-bit timers. n waveform generator the waveform generator can generate several timing waveform as follows: ? by using 8-bit timer as dead-time timer, non-overlap signal of rt1, 3, 5 inverting signal can be generated. it is possible to make non-overlap signal of the selected ppg timer clock inverted signal only when rt1, 3, 5 is at the h level.(dead-time generation). ? with rt0~5 rising edge, the 8-bit timer is started and the selected ppg timer keeps outputting until when the value of the 8-bit timer is matched with the value of tmrr register (8-bit reload register). figure 12.4.5-1 is the block diagram of the waveform generator. figure 12.4.5-1 waveform generator g0 g1 g2 g3 g4 g5 ppg output and gate signal control circuit 8-bit timer 0 8-bit timer 1 8-bit timer 2 dead-time selector port rto0/u rt0 dtti selector port rto1/x selector port rto2/v rt1 rt2 rt3 rt4 rt5 ppg0 ppg1 ppg2 ppg3 ppg4 ppg5 selector port rto3/x selector port rto4/w selector port rto5/z o o o o o o control circuit
MB90560 series chapter 12 multi-function timer 341 memo
342 chapter 12 multi-function timer MB90560 series 12.4.5 operation of waveform generator 12.4.5.1 operation of dead-timer control circuit the dead-time control circuit will input the realtime output (rt1/3/5) and the selected ppg timer pulse output, and output non-overlap signals (inverted signals) to external pins. n making non-overlap signals by using rt1/3/5 when selecting non-overlap signal for a active level 0 (positive polarity) in dtcr:bit 15 (dmod), a delay corresponding to the non-overlap time set in the tmrr register (8-bit reload register) is applied. the delay is applied at a rising edge of rt1/3/5 or its falling edge. if rt1/3/5 pulse width is smaller than the set non-overlap time, the 8-bit timer will restart counting from 00 h at the nest rts edge. figure 12.4.5.1-1 positive polarity non-overlap signal generation by rt1/3/5 setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : xxxxxx00 b (dtti input and 8-bit timer count clock setting) note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---1xxxxxxxx--11 b ? dtcr0~2 : 00000100 b count value rt1 u x one machine cycle one machine cycle tmrr set value pin name output signal u signal with delay is applied at rt1 rising edge v signal with delay is applied at rt3 rising edge w signal with delay is applied at rt5 rising edge x signal with delay is applied at rt1 falling edge y signal with delay is applied at rt3 falling edge z signal with delay is applied at rt5 falling edge
MB90560 series chapter 12 multi-function timer 343 when selecting non-overlap signal for a active level 1 (positive polarity) in dtcr:bit 15 (dmod), a delay corresponding to the non-overlap time set in the tmrr register (8-bit reload register) is applied. the delay is applied at a rising edge of rt1/3/5 or its falling edge. if rt1/3/5 pulse width is smaller than the set non-overlap time, the 8-bit timer will restart counting from 00 h at the nest rts edge. figure 12.4.5.1-2 negative polarity non-overlap signal generation by rt1/3/5 setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : xxxxxx00 b (dtti input and 8-bit timer count clock setting note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---1xxxxxxxx--11 b ? dtcr0~2 : 10000100 b count value rt1 u x one machine cycle one machine cycle tmrr set value pin name output signal u signal with delay is applied at rt1 rising edge v signal with delay is applied at rt3 rising edge w signal with delay is applied at rt5 rising edge x signal with delay is applied at rt1 falling edge y signal with delay is applied at rt3 falling edge z signal with delay is applied at rt5 falling edge
344 chapter 12 multi-function timer MB90560 series n making non-overlap signals by using ppg when selecting non-overlap signal for a active level 0 (positive polarity) in dtcr:bit 15 (dmod), a delay corresponding to the non-overlap time set in the tmrr register (8-bit reload register) is applied. the delay is applied at a rising edge of ppg timer pulse signal or its inverted signal. if ppg timer pulse width is smaller than the set non-overlap time, the 8-bit timer will start counting from 00 h at the next edge of ppg pulse. figure 12.4.5.1-3 positive polarity non-overlap signal generation by ppg timer setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : xxxxxx00 b (dtti input and 8-bit timer count clock setting) note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---1xxxxxxxx--11 b ? dtcr0~2 : 01000111 b count value ppg1 u x one machine cycle one machine cycle tmrr set value pin name output signal u signal with delay is applied at ppg1 rising edge v signal with delay is applied at ppg3 rising edge w signal with delay is applied at ppg5 rising edge x signal with delay is applied at ppg1 falling edge y signal with delay is applied at ppg3 falling edge z signal with delay is applied at ppg5 falling edge
MB90560 series chapter 12 multi-function timer 345 when selecting non-overlap signal for a active level 1 (positive polarity) in dtcr:bit 15 (dmod), a delay corresponding to the non-overlap time set in the tmrr register (8-bit reload register) is applied. the delay is applied at a rising edge of ppg timer pulse signal or its inverted signal. if ppg timer pulse width is smaller than the set non-overlap time, the 8-bit timer will start counting from 00 h at the next edge of ppg pulse. figure 12.4.5.1-4 negative polarity non-overlap signal generation by ppg timer setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : xxxxxx00 b (dtti input and 8-bit timer count clock setting) note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---1xxxxxxxx--11 b ? dtcr0~2 : 11000111 b count value ppg1 u x one machine cycle one machine cycle tmrr set value pin name output signal u signal with delay is applied at ppg1 rising edge v signal with delay is applied at ppg3 rising edge w signal with delay is applied at ppg5 rising edge x signal with delay is applied at ppg1 falling edge y signal with delay is applied at ppg3 falling edge z signal with delay is applied at ppg5 falling edge
346 chapter 12 multi-function timer MB90560 series 12.4.5 operation of waveform generator 12.4.5.2 operation of ppg output and gate signal control circuit the ppg output and gate signal control circuit will output the selected ppg pulse to external pins when 1 is written to dctr:bit 14, 13 (gten, pgen). furthermore, it output the gate signal which controls ppg timer operation. it generated gate signal by using realtime outputs or 8-bit timers and output to ppg timers. n generating a ppg output/gate signal during each rt is at h level figure 12.4.5.2-1 generating ppg output/gate signal during each rt is at h level setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : xxxxxx00 b (dtti input and 8-bit timer count clock setting note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---0xxxxxxxx--11 b ? dtcr0~2 : 01111001 b count value ffff h bfff h 3fff h 0000 h 7fff h time bfff h 7fff h ppg0 ppg1 compare register 0 value compare register 1 value rt0 rt1 gate0 gate1 rto0 rto1
MB90560 series chapter 12 multi-function timer 347 n generating ppg output/gate signal until value of 8-bit timer and 8-bit reload register is matched. (starting the 8-bit timer at every rising edge of the rt) figure 12.4.5.2-2 generating ppg output/gate signal until the value 8-bit timer and 8-bit reload regis- ter is matched. note: each 8-bit timer is used for two rts. i.e. 8-bit timer 0 is used for rt0 and rt1; 8-bit timer 1 is used for rt2 and rt3; 8-bit timer 2 is used for rt4 and rt5. therefore, do not use an rt and attempt to start the corresponding timer that is already operating. doing so may cause that the outputting gate signal will be extended and malfunction will be occurred. setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : xxxxxx00 b (dtti input and 8-bit timer count clock setting note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---0xxxxxxxx--11 b ? dtcr0~2 : 01111010 b count value ffff h bfff h 3fff h 0000 h 7fff h time bfff h 7fff h ppg0 ppg1 compare register 0 value compare register 1 value rt0 rt1 gate0 gate1 rto0 rto1 time of 8-bit timer 1 time of 8-bit timer 0
348 chapter 12 multi-function timer MB90560 series 12.4.5 operation of waveform generator 12.4.5.3 operation of dtti pin control by setting 1 to waveform control register, sigcr:bit 7 (dtie), for the wave output of rto0~5 can be controlled by the dtti pin. a valid input level which is set by sigcr:bit 6 (dtil) and is detected, the output of rto0~5 will be fixed to an inactive level. the inactive level can be set pin by pin to pdr3 of port 3 by software. n dtti pin input operation even when the valid dtti pin input is detected, the timer will keep running for the waveform generator operation, but no waveform will outputted to external pins. figure 12.4.5.3-1 operation when dtti input is enabled setting up registers: ? tcdt : 0000 h ? tccs : ------xxxx0x0xxx b ? occp0~5 : xxxx h (compare value) ? tmrr0~2 : xxxxxxxxx b (non-overlap timing setting) ? sigr : 110xxxxx b (dtti input and 8-bit timer count clock setting) note: x must be set according to the operation. ? cpclr : xxxx h (cycle setting) ? osc0~5 : ---1xxxxxxxx--11 b ? dtcr0~2 : 00000100 b count value ffff h bfff h 3fff h 0000 h 7fff h time bfff h 7fff h compare register 0 value compare register 1 value rt1 rto0 rto1 dtti
MB90560 series chapter 12 multi-function timer 349 n dtti pin noise cancelling function by setting bit 5 (nrsl) of the waveform control register (sigcr) to 1, the noise cancelling function for dtti pin input is enabled. when noise cancelling function is enabled, approximately 4 machine cycles of delay (due to noise cancelling circuit) will be occurred for inactive level fix timing of output pin. since the noise cancelling circuit operates by using machine clock, the dtti input is invalid at stop mode (oscillator is stopped) even if the dtti input is enabled.

chapter 13 uart this chapter explains the functions and operation of uart. 13.1 overview of uart ........................................................................ 352 13.2 configuration of uart.................................................................. 354 13.3 uart pins .................................................................................... 358 13.4 uart registers............................................................................ 360 13.5 uart interrupts............................................................................ 372 13.6 uart baud rates ........................................................................ 376 13.7 operation of uart ....................................................................... 386 13.8 notes on using uart .................................................................. 396 13.9 sample program for uart........................................................... 398
352 chapter 13 uart MB90560 series 13.1 overview of uart uart is a general-purpose serial data communication interface for performing synchronous or asynchronous (start-stop synchronization) communication with external devices. the uart has a normal bidirectional communication function (normal mode), additionally the master-slave communication function (multiprocessor mode) is only available for the master system. n uart functions l uart functions uart is a general-purpose serial data communication interface for transmitting serial data to and receiving data from another cpu and peripheral devices. it has the functions listed in table 13.1-1. table 13.1-1uart functions during clock synchronous transfer, start and stop bits are not added so only data is transferred in uart. function data buffer full-duplex, double buffering transfer mode clock synchronous (using start and stop bits) clock asynchronous (start-stop synchronization) baud rate a dedicated baud rate generator is provided. eight settings can be selected. an external clock can be input. internal clock (internal clocks supplied from 16-bit reload timer 0 can be used.) data length 7 bits (in asynchronous normal mode only) 8 bits signal mode non-return to zero (nrz) reception error detection framing error overrun error parity error (cannot be detected in multiprocessor mode.) interrupt request reception interrupt (reception completion and reception error detection) transmission interrupt (transmission completion) extended intelligent i/o service (ei20s) is available for both trans- mission and reception interrupts. master-slave communication function (multiprocessor mode) one-to-n communication (one master to n slaves) can be performed. (this function is supported only for the master system.)
MB90560 series chapter 13 uart 353 figure 13.1-1 uart operation mode C : setting not possible *1 : "+1" indicates the address/data selection bit (a/d) for communication control. *2 : during reception, only one stop bit can be detected. n uart interrupt and ei2os table 13.1-2 uart interrupt and ei2os : provided with a function that detects a uart reception error and stops ei2os d : usable when icr13 and icr14 or interrupt causes that share an interrupt vector are not used operation mode data length synchronization mode stop bit length when parity is disabled when parity is enabled 0 normal mode 7 or 8 bits asynchronous 1 or 2 bits * 2 1 multiprocessor 8+1* 1 C asynchronous 2 normal mode 8 C synchronous none interrupt cause interrupt number interrupt control register vector table address ei2os register name address lower upper bank uart1 reception interrupt #37(25h) icr13 0000bdh ffff68h ffff69h ffff6ah uart1 transmission interrupt #38(26h) icr13 0000bdh ffff64h ffff65h ffff66h d uart0 reception interrupt #39(27h) icr14 0000beh ffff60h ffff61h ffff62h uart0 transmission interrupt #40(28h) icr14 0000beh ffff5ch ffff5dh ffff5eh d
354 chapter 13 uart MB90560 series 13.2 configuration of uart uart consists of the following 11 blocks: ? clock selector serial mode control register (smr0/1) ? reception control circuit serial control register (scr0/1) ? transmission control circuit serial status register (ssr0/1) ? reception status detection circuit serial input data register (sidr0/1) ? reception shift register serial output data register (sodr0/1) ? transmission shift register n block diagram of uart figure 13.2-1 block diagram of uart p40/sck0 start bit detection circuit transmission start circuit received bit counter transmission bit counter received parity counter transmission parity counter reception shift register reception status detection circuit transmission shift register smr0/1 register scr0/1 register md1 md0 cs2 cs1 bds scke soe tdre ssr0/1 register pen p sbl cl a/d rec rxe sidr0/1 internal data bus *1: interrupt number sodr0/1 cs0 txe rie tie pe ore fre rdrf reception error reception signal for ei2os (to cpu) control bus dedicated baud rate generator 16-bit reload timer pin p36/sin0 pin pin clock selector transmission clock reception clock completion of reception start of transmission reception control circuit transmission control circuit reception interrupt signal #39 (28 h )(*1) <#37 (25h)> transmission interrupt signal #40 (28 h )(*1) <#38 (26h)> p37/sot1
MB90560 series chapter 13 uart 355 l clock selector the clock selector selects the dedicated baud rate generator, external input clock, or internal clock (clock supplied from the 16-bit reload timer) as the transmitting and receiving clocks. l reception control circuit the reception control circuit consists of a received bit counter, start bit detection circuit, and received parity counter.the received bit counter counts receive data bits. when reception of one data item for the specified data length is complete, the received bit counter generates a reception interrupt request. the start bit detection circuit detects start bits from the serial input signal. when the circuit detects a start bit, it writes data in the sidr1 register by shifting at the specified transfer rate. the received parity counter calculates the parity of the receive data. l transmission control circuit the transmission control circuit consists of a transmission bit counter, transmission start circuit, and transmission parity counter.the transmission bit counter counts transmission data bits. when transmission of one data item of the specified data length is complete, the transmission bit counter generates a transmission interrupt request. the transmission start circuit starts transmission when data is written to sodr0/1. the transmission parity counter generates a parity bit for data to be transmitted when parity is enabled. l reception shift register the reception shift register fetches receive data input from the sin pin, shifting the data bit by bit. when reception is complete, the reception shift register transfers receive data to the sidr0/1 register. l transmission shift register the transmission shift register transfers data written to the sodr0/1 register to itself and outputs the data to the sot pin, shifting the data bit by bit. l serial mode control register 1 (smc0/1) this register performs the following operations: ? selecting a uart operation mode ? selecting a clock input source ? setting up the dedicated baud rate generator ? selecting a clock rate (clock division value) when using the dedicated baud rate generator ? specifying whether to enable serial data output to the corresponding pin ? specifying whether to enable clock output to the corresponding pin
356 chapter 13 uart MB90560 series l serial control register 1 (scr0/1) this register performs the following operations: ? specifying whether to provide parity bits ? selecting parity bits ? specifying a stop bit length ? specifying a data length ? selecting a frame data format in mode 1 ? clearing a flag ? specifying whether to enable transmission ? specifying whether to enable reception l serial status register 1 (ssr0/1) this register checks the transmission and reception status and error status, and enables and disables transmission and reception interrupt requests. l serial input data register 1 (sidr0/1) this register retains receive data. serial input data is converted and stored in this register. l serial output data register 1 (sodr0/1) this register retains transmission data. data written to this register is converted to serial data and output.
MB90560 series chapter 13 uart memo
358 chapter 13 uart MB90560 series 13.3 uart pins this section describes the uart pins and provides a pin block diagram. n uart pins the uart pins also serve as general ports. table 13.3-1 lists the pin functions, i/o formats, and settings required to use uart. table 13.3-1uart pins pin name pin function i/o format pull-up standby control setting required to use pin p36/sin0 port 3 i/o or serial data input cmos output and cmos hysteresis input not available provided set as an input port (ddr3: bit6 = 0) p37/sot0 port 3 i/o or serial data output set to output enable mode (smr0: soe = 1) p40/sck0 port 4 i/o or serial clock input/output set as an input port when a clock is input (ddr4: bit 0=0) set to output enable mode when a clock is output (smr0: scke = 1) p60/sin1 port 6 i/o or serial data input cmos output and cmos hysteresis input not available provided set the pin as an input port (ddr6: bit0 = 0) p61/sot1 port 6 i/o or serial data output set the pin as an input port (smr1: soe = 1) p62/sck1 port 6 i/o or serial clock input/output set as an input port when a clock is input (ddr6: bit2 = 0) set to output enable mode when a clock is output (smr1:scke = 1)
MB90560 series chapter 13 uart 359 n block diagram of uart pins figure 13.3-1 block diagram of uart pins port data register (pdr) ddr read port direction register (ddr) ddr write pdr write pdr read internal data bus output latch direction latch pch nch p60/sin1 p61/sot1 p62/sck1 p36/sin0 pin p37/sot0 p40/sck0 peripheral input (*1) peripheral output (*1) peripheral output enable (*1) standby control (spl=1) standby control: stop mode, timebase timer mode and spl=1 *1: peripheral are input or output to or from pins having peripheral functions.
360 chapter 13 uart MB90560 series 13.4 uart registers the following figure shows the uart registers. n uart registers figure 13.4-1 uart registers address bit15 bit8 bit7 bit0 ch0:000021 h ,20 h ch0:000025 h ,24 h scr (serial control register) smr (serial mode control register) ch0:000023 h ,22 h ch0:000027 h ,26 h ssr (serial status register) sidr/sodr (serial input/output data register) ch0:000029 h ch1:00002b h cdcr (communication prescaler con- trol register) reserved
MB90560 series chapter 13 uart 361 memo
362 chapter 13 uart MB90560 series 13.4 uart registers 13.4.1 serial control register 1 (scr0/1) this register specifies parity bits, selects the stop bit and data lengths, selects a frame data format in mode 1, clears the reception error flag, and specifies whether to enable transmission and reception. n serial control register (scr0/1) figure 13.4-2 serial control register (scr0/1) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 (smr) txe rxe rec a/d cl sbl p pen txe 0 1 r/w r/w r/w r/w r/w w r/w r/w ch0:000021 h ch1:000025 h 00000100 b r/w : read/write : write only : initial value w y rxe 0 1 rec 0 1 ad 0 1 cl 0 1 sbl 0 1 0 1 p pen 0 1 transmission enable bit disables transmission. enables transmission. reception enable bit disables reception. enables reception. reception error flag clear bit clears the fre, ore, and pe flags. has no effect on the others. address/data selection bit data frame address frame data length selection bit 7 bits 8 bits stop bit length selection bit 1-bit length 2-bit length enabled only when parity is provided (pen=1) parity selection bit even parity odd parity parity enable bit provides no parity bit. provides a parity bit. address initial value
MB90560 series chapter 13 uart 363 table 13.4-1 functions of each bit of serial control register (scr0/1) bit name function bit15 pen: parity enable bit this bit selects whether to add a parity bit during transmission in serial data input-output mode or to detect it during reception. no parity can be used in operation modes 1 and 2, so that fix this bit to 0. bit14 p: parity selection bit when parity is provided (pen=1), this bit selects an even or odd parity. bit13 sbl: stop bit length selection bit this bit selects the length of the stop bits or the frame end mark of send data in asynchronous transfer mode. during reception, only the first bit of the stop bits is detected. bit12 cl: data length selection bit this bit specifies the length of send and receive data. seven bits can be selected in operation mode 0 (asynchronous) only. be sure to select eight bits (cl=1) in operation mode 1 (multi- processor mode) and operation mode 2 (synchronous). bit11 a/d: address/data selection bit specify the data format of a frame to be sent or received in multi- processor mode (mode 1). select normal data when this bit is 0, and select address data when the bit is 1. bit10 rec: reception error flag clear bit this bit clears the fre, ore, and pe flags of the status register (ssr). write 0 to this bit to clear the fre, ore, and pe flag. writing 1 to this bit has no effect on the others. if uart is active and a reception interrupt is enabled, clear the rec bit only when the fre, dre, or pe flag indicates 1. bit9 rxe: reception enable bit this bit controls uart reception. when this bit is 0, reception is disabled. when it is 1, reception is enabled. if reception operation is disabled during reception, finish frame reception and store the received data in the receive data buffers (sidri). then stop the reception operation. bit8 txe: transmission enable bit this bit controls uart transmission. when this bit is 0, transmission is disabled. when the bit is 1, transmission is enabled. when transmission operation is disabled during transmission, wait until there is no data in the send data buffers (sodr1) before stop- ping the transmission operation.
364 chapter 13 uart MB90560 series 13.4 uart registers 13.4.2 serial mode control register (smr0/1) this register selects an operation mode and baud rate clock and specifies whether to enable output of serial data and clocks to the corresponding pin. n serial mode control register (smr0/1) figure 13.4-3 serial mode control register (smr0/1) md1 md0 0 0 1 1 0 1 0 1 0 - 1 2 scke 0 1 r/w r/w r/w r/w r/w r/w r/w bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit8 (scr) ch0:000020 h ch1:000024 h md1 md0 cs2 cs1 cs0 scke soe r/w bch 00000000 b soe 0 1 cs2~0 "000 b "~"100 b " "101 b " "110 b " "111 b " r/w : enables read and write. : initial value : not used - serial data output enable bit (p37/sot0, p61/sot1 pin) uses the pin as a general i/o port. uses the pin as the serial data output pin of uart1. serial clock output enable bit (p50sck1, p63/sck1 pin) uses the pin as a general i/o port or clock input pin of uart1 uses the pin as the clock output pin of uart1. clock selection bit baud rate by dedicated baud rate generator disables setting. baud rate by internal timer (16-bit reload timer 0) baud rate by external clock operation mode operation mode selection bit asynchronous (normal mode) asynchronous (multiprocessor mode) synchronous (normal mode) disables setting. address initial value mode # bch 0 1
MB90560 series chapter 13 uart 365 table 13.4-2 functions of each bit of serial mode control register (smr0/1) bit name function bit7 bit6 md1 and md0: operation mode selection bits these bits select an operation mode. operation mode 1 (multiprocessor mode) can be used only from the master system during master-slave communication. uart cannot be used from the slave system because it has no address/data detection function during reception. bit5 bit4 bit3 cs2 to cs0: clock selection bits this bit selects a baud rate clock source. when the dedicated baud rate generator is selected, the baud rate is determined at the same time. when the dedicated baud rate generator is selected, eight baud rates can be selected: five in asynchronous transfer mode and three in synchronous transfer mode. input clocks can be selected from external clocks (sck0/1 pin), 16- bit reload timer 0, and the dedicated baud rate generator. bit2 bch: bit1 scke: serial clock output enable bit this bit controls the serial clock input-output ports. when this bit is 0, the p40/sck0 and p62/sck1 pins operate as general input-output ports (p40 and p62) or serial clock input pins. when this bit is 1, the pins operate as serial clock output pins. when using the p40/sck0 and p62/sck1 pins as serial clock input (scke=0) pins, set the p40 and p62 as input ports. also, select external clocks (smr0/1: cs2 to cs0 = 111b) using the clock selection bits. when using the pins as serial clock output (scke=1) pins, select clocks other than external clocks (other than smr0/1: cs2 to cs0 = 111b). when the sck0/1 pin is assigned to serial clock output (scke=1), it functions as the serial clock output pin regardless of the status of the general input-output ports. bit0 soe: serial data output enable bit this bit enables or disables the output of serial data. when this bit is 0, the p37/sot0 and p61/sot1 pins operate as general input-output ports (p37 and p61). when this bit is 1, the p37/sot0 and p61/sot1 pins operate as serial data output pins (sot0/1). when serial data is output (soe=1), the enabled, the p37/sot0 and p61/sot1 pins function as sot0/1 pins regardless of the status of general input-output ports (p37 and p61)
366 chapter 13 uart MB90560 series 13.4 uart registers 13.4.3 serial status register (ssr0/1) this register checks the transmission and reception status and error status, and enables and disables the transmission and reception interrupts. n serial status register (ssr0/1) figure 13.4-4 status register (ssr0/1) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 (sidr/sodr) tie rie bds tdre rdrf fre ore pe tie 0 1 r r r r r r/w r/w ch0:000023 h ch1:000027 h 00001000 b rie 0 1 bds 0 1 tdre 0 1 rdrf 0 1 0 1 fre ore 0 1 r/w r r/w pe 0 1 : read/write : read only : initial value transmission interrupt request enable bit disables transmission interrupt request. enables transmission interrupt request. reception enable bit disables reception interrupt request. enables reception interrupt request. transfer direction selection bit lsb first (transfer from the least significant bit) msb first (transfer from the most significant bit) transmission data empty flag bit transmission data exists. (writing transmission data is not allowed.) transmission data does not exist. (writing transmission data is allowed.) receive data full flag bit no receive data exists. receive data exists. framing error flag bit no framing error occurred. a framing error occurred. overrun error flag bit no overrun error occurred. an overrun error occurred. parity error flag bit no parity error occurred. a parity error occurred. address initial value
MB90560 series chapter 13 uart 367 table 13.4-3 functions of each bit of serial status register (ssr0/1) no. bit name function bit15 pe: parity error flag bit this bit is set to 1 when a parity error occurs during reception and is cleared when 0 is written to the rec bit of the serial control register (scr0/1). a reception interrupt request is generated when this bit and the rie bit are 1. data in serial input data register (sidr0/1) is invalid when this flag is set. bit14 ore: overrun error flag bit this bit is set to 1 when an overrun error occurs during reception and is cleared when 0 is written to the rec bit of the serial control register (scr0/1). a reception interrupt request is generated when this bit and the rie bit are 1. data in the serial input data register (sidr0/1) is invalid when this flag is set. bit13 fre: framing error flag bit this bit is set to 1 when a framing error occurs during reception and is cleared when 0 is written to the rec bit of the serial control register (scr0/1). a reception interrupt request is generated when this bit and the rie bit are 1. data in the serial input data register (sidr0/1) is invalid when this flag is set. bit12 rdrf: receive data full flag bit this flag indicates the status of the input data register (sidr0/1). this bit is set to 1 when receive data is loaded into sidr0/1 and is cleared to 0 when serial input data register sidr0/1 is read. a reception interrupt request is generated when this bit and the rie bit are 1. bit11 tdre: transmission data empty flag bit this flag indicates the status of output data register (sodr0/1). this bit is cleared to 0 when transmission data is written to sodr0/1 and is set to 1 when data is loaded into the transmission shift register and transmission starts. a transmission interrupt request is output when this bit and the rie bit are 1. this bit is set to 1 (sodr0/1 empty) as its initial value. bit10 bds: transfer direction selection bit this bit selects whether to transfer serial data from the least significant bit (lsb first, bds=0) or the most significant bit (msb first, bds=1). the high-order and low-order sides of serial data are interchanged with each other during reading from or writing to the serial data register. if this bit is set to another value after the data is written to the sdr register, the data becomes invalid. bit9 rie: reception interrupt request enable bit this bit enables or disables reception interrupt request to the cpu. a reception interrupt request is generated when this bit and the receive data flag bit (rdrf) are 1 or this bit and one or more error flag bits (pe, ore, and fre) are 1. bit8 tie: transmission interrupt request enable bit this bit enables or disables transmission interrupt request o the cpu. a transmission interrupt request is generated when this bit and the tdre bit are 1.
368 chapter 13 uart MB90560 series 13.4 uart registers 13.4.4 serial input data register (sidr0/1) and serial output data register (sor0/1) the serial input data register (sidr0/1) is a serial data reception register. the serial output data register (sodr0/1) is a serial data transmission register. both sidr0/1 and sodr0/1 registers are located in the same address. n serial input data register (sidr0/1) figure 13.4-5 shows the bit configuration of serial input data register 1. figure 13.4-5 serial input data register (sidr0/1) sidr0/1 is a register that contains receive data. after the serial data signal transmitted from the sin0/1 pin to the shift register, the data is stored there. when the data length is 7 bits, the uppermost bit (d7) contains invalid data. when receive data is stored in this register, the receive data full flag bit (ssr0/1: rdrf) is set to 1. if a reception interrupt request is enabled at this point, a reception interrupt request is generated. read sidr0/1 when the rdrf bit of the status register (ssr0/1) is 1. the rdrf bit is cleared automatically to 0 when sidr01/1 is read. data in sidr0/1 is invalid when a reception error occurs (ssr0/1: pe, ore, or fre = 1). n serial output data register (sodr0/1) figure 13.4-6 shows the bit configuration of the serial output data register. figure 13.4-6 output data register (sodr0/1) when data to be transmitted is written to this register in transmission enable state, it is transferred to the transmission shift register, then converted to serial data, and transmitted to the serial data output terminal (sot0/1 pin). when the data length is 7 bits, the uppermost bit (d7) contains invalid data. rr r r rr r r d3 d0 d1 d2 d7 d4 d5 d6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b ch0:000022 h ch1:000026 h r x address initial value : read only : indefinite d3 d0 d1 d2 d7 d4 d5 d6 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 xxxxxxxx b ch0:000022 h ch1:000026 h r x address initial value : write only : indefinite w w w w w w w w
MB90560 series chapter 13 uart 369 when transmission data is written to this register, the transmission data empty flag bit (ss0/1: tdre) is cleared to 0. when transfer to the transmission shift register is complete, the bit is set to 1. when the tdre bit is 1, the next transmission data can be written. if output transmission interrupt requests have been enabled, a transmission interrupt request is generated. write the next transmission data when a transmission interrupt is generated or the tdre bit is 1. sodr0/1 is a write-only register and sidr0/1 is a read-only register. these registers are located in the same address, so the read value is different from the write value. therefore, instructions that perform a read-modify-write (rmw) operation, such as the inc/dec instruction, cannot be used.
370 chapter 13 uart MB90560 series 13.4 uart registers 13.4.5 communication prescaler control register (cdcr0/1) this register controls the division of machine clocks. n communication prescaler control register (cdcr0/1) the operation clocks of uart can be obtained by dividing machine clocks. uart is designed to obtain certain baud rates for various machine cycles. output from the communication prescaler is used for the operation clocks of extended i/o serial interfaces. the cdcr bit configuration is shown below. [bit 15] md(machine clock divide mode select) operation enable bit of the communication prescaler 0: stops the communication prescaler. 1: operates the communication prescaler. [bit 11,10,9,8] div3 ~ 0(divide3 ~ 0) machine clock division ratios are determined according to the table in table 13.4-4. table 13.4-4communication prescaler if a division ratio is changed, wait two time cycles as clock stabilization time before starting communication. md div3 div2 div1 div0 divided by 0 CCCC stop 10000 1 10001 2 10010 3 10011 4 10100 5 10101 6 10110 7 10111 8 r/w r/w r/w r/w r/w div1 div0 div2 div3 -- - md 15 14 13 12 10 11 9 8 0---0000h cdcr address initial value ch0:000029 h ch1:00002b h
MB90560 series chapter 13 uart 371 memo
372 chapter 13 uart MB90560 series 13.5 uart interrupts uart uses both reception and transmission interrupts. an interrupt request can be generated for either of the following causes: ? receive data is transferred to the serial input register (sidr0/1), or a reception error occurs. ? transmission data is transferred from the serial output data register 1 (sodr0/1) to the transmission shift register. the extended intelligent i-o service (ei2os) is available for these interrupts. n uart interrupts table 13.5-1 lists the interrupt control bits and causes of uart. table 13.5-1 interrupt control bits and interrupt causes of uart o: used x : not used l reception interrupt if one of the following events occurs in reception mode, the corresponding flag bit of the status register is set to 1: ? data reception is complete (ssr0/1: rdrf) ? overrun error (ssr0/1: ore) ? framing error (ssr0/1; fre) ? parity error (ssr0/1: pe) when at least one of the flag bits is 1 and the reception interrupts are enabled (ssr0/1: rie=1), a reception interrupt request is generated to the interrupt controller. when the serial input data register (sidr0/1) is read, the receive data full flag (ssr0/1: rdrf) is automatically cleared to 0. when 0 is written to the rec bit of the serial control register (scr0/1), all the reception error flags (ssr0/1: pe, ore, and fre) are cleared to 0. reception/ transmission interrupt request flag bit operation mode interrupt cause interrupt cause enable bit when interrupt request flag is cleared 01 2 reception rdrf o o o loading receive data into buffers (sidr0/1) ssr0/1:rie receive data is read. ore o o o overrun error 0 is written to the reception error flag clear bit (ssr1: rec). fre o o x framing error pe o x x parity error transmission tdre o o o empty transmission buffer (sodr0/1) ssr0/1:tie transmission data is written.
MB90560 series chapter 13 uart 373 l transmission interrupt when transmission data is transferred from the serial output data register (sodr0/1) to the transfer shift register, the tdre bit of the serial status register (ssr0/1) is set to 1. when the transmission interrupts have been enabled (ssr0/1: tie=1), a transmission interrupt request is generated to the interrupt controller. n uart interrupts and ei2os table 13.5.2 uart interrupts and ei2os : provided with a function that detects a uart reception error and stops ei2os d : usable when interrupt causes that share the icr13 and icr14 or the interrupt vectors are not used n uart ei2os functions uart has a circuit for operating ei2os, which can be started up for either reception or transmission interrupts. l for reception ei2os can be used regardless of the status of other resources. l for transmission uart shares the interrupt registers (icr13 and icr14) with the uart reception interrupts. therefore, ei2os can be started up only when no uart reception interrupts are used. interrupt cause interrupt number interrupt control register vector table address ei2os register name address lower upper bank uart1 reception interrupt #37(25h) icr13 0000bdh ffff68h ffff69h ffff6ah uart1 transmission interrupt #38(26h) icr13 0000bdh ffff64h ffff65h ffff66h d uart0 reception interrupt #39(27h) icr14 0000beh ffff60h ffff61h ffff62h uart0 transmission interrupt #40(28h) icr14 0000beh ffff5ch ffff5dh ffff5eh d
374 chapter 13 uart MB90560 series 13.5 uart interrupts 13.5.1 reception interrupt generation and flag set timing the following are the reception interrupt causes: completion of reception (ssr0/1: rdrf) and occurrence of a reception error (ssr0/1: pe, ore, or fre). n reception interrupt generation and flag set timing receive data is stored in the serial input data register 1 (sidr0/1) if a stop bit is detected (in operation mode 0 or 1) or the last bit of data is detected (in operation mode 2) during reception. if a reception error is detected, the error flags (ssr0/1: pe, ore, and fre) are set, then the receive data flag (ssr0/1: rdrf) is set to 1. if one of the error flags is 1 in each mode, the sidr0/1 register contains invalid data. l operation mode 0 (asynchronous, normal mode) the rdrf bit is set to 1 when a stop bit is detected. if a reception error is detected, the error flags (pe, ore, and fre) are set. l operation mode 1 (asynchronous, multiprocessor mode) the rdrf bit is set to 1 when a stop bit is detected. if a reception error is detected, the error flags (ore and fre) are set. parity errors cannot be detected. l operation mode 2 (synchronous, normal mode) the rdrf bit is set when the last bit of receive data (d7) is detected. if a reception error is detected, the error flag (ore) is set. parity and framing errors cannot be detected. the figure below shows the reception operation and flag set timing. figure 13.5-1 reception operation and flag set timing l reception interrupt generation timing when the rdrf, pe, ore, or fre flag is set to 1 in the reception interrupt enable state (ssr0/1: rie=1), reception interrupt requests (#37 and #39) are generated. pe, ore, fre* receive data (operation mode 0) receive data (operation mode 1) receive data (operation mode 2) * : the pe flag cannot be used in mode 1. the pe and pre flags cannot be used in mode 2. st : start bit sp : stop bit a/d : mode 2 (multiprocessor mode) address/data selection bit rdrf a reception interrupt occurs. d0 d1 d6 d7 a/d d5 d6 d7/p sp st d0 d1 sp st d0 d1 d4 d5 d6 d7
13.5 uart interrupts MB90560 series chapter 13 uart 13.5.2 transmission interrupt generation and flag set timing a transmission interrupt is generated when the next piece of data is ready to be written to the output data register (sodr0/1). n transmission interrupt generation and flag set timing the transmission data empty flag bit (ssr0/1: tdre) is set to 1 when data written to the output data register (sodr0/1) is transferred to the transmission shift register, and the next data is ready to be written. tdre is cleared to 0 when transmission data is written to sodr0/1. figure 13.5-2 shows the transmission operation and flag set timing. figure 13.5-2 transmission operation and flag set timing l transmission interrupt request generation timing if the tdre flag is set to 1 when a transmission interrupt is enabled (ssr0/1: tie=1), transmission interrupt requests (#38 and #40) are generated. a transmission completion interrupt is generated immediately after the transmission interrupts are enabled (tie=1) because the tdre bit is set to 1 as its initial value. tdre is a read- only bit that can be cleared only by writing new data to the serial output data register (sodr0/1). carefully specify the transmission interrupt enable timing. st d0~d7 sp a/d d2 d3 d5 d6 d4 st d0 d1 st d0 d2 d3 d1 d7 sp a/d sp sodr writing [operation modes 0 and 1] a transmission interrupt occurs. a transmission interrupt occurs. a transmission interrupt occurs. a transmission interrupt occurs. [operation modes 2] tdre sot output d3 d4 d6 d7 d5 d0 d1 d2 d3 d4 d6 d7 d5 d0 d1 d2 sodr writing tdre sot output : start bit : data bit : stop bit : address/data selection bit
376 chapter 13 uart MB90560 series 13.6 uart baud rates one of the following can be selected as the uart transmitting/receiving block: ? dedicated baud rate generator ? internal clock (16-bit reload timer 0) ? external clock (clock input to the sck pin) n uart baud rate selection the baud rate selection circuit is designed as shown below. one of the following three types of baud rates can be selected: l baud rates determined using the dedicated baud rate generator uart has an internal dedicated baud rate generator. one of eight baud rates can be selected using the communication prescaler control register (cdcr0/1). an asynchronous or clock synchronous baud rate is selected using the machine clock frequency and the bch and cs2 to cs0 bits of the mode control register (smr0/1). l baud rates determined using the internal timer the internal clock supplied from 16-bit reload timer 0 is used as it is (synchronous) or by dividing it by 16 (asynchronous) for the baud rate. any baud rate can be set by setting the reload value of 16-bit reload register (tmrlr0). l baud rates determined using the external clock the clock input from the uart clock pulse input pins (sck0/p40 and sck1/p62) is used as it is (synchronous) or by dividing it by 16 (asynchronous) for the baud rate. any baud rate can be set externally.
MB90560 series chapter 13 uart 377 figure 13.6-1 baud rate selection circuit 0 4 f /4 1 f /5 smr0/1:cs2~0 (clock selection bits) smr1:bch [dedicated baud rate generator] 16/10mhz tmcsr0/1 csl1, csl0 uf sck0/p40,sck1/p62 16-bit reload timer 0 smr0/1 md1, md0 f /2 1 f /2 3 f /2 5 2 clock selector when the bits are 000 b to 100 b prescaler f frequency divider (synchronous) selects 1/2, 1/4, or 1/8. (asynchronous) selects the internal fixed division ratio. [internal timer] when the bits are 110 b clock selector down counter 1/1 (synchronous) 1/16 (asynchronous) 1/1 (synchronous) 1/16 (asynchronous) baud rate prescaler [external clock] [pin] when the bits are 111 b f : machine clock frequency (clock synchronous/asynchronous selection) f
378 chapter 13 uart MB90560 series 13.6 uart baud rates 13.6.1 baud rates determined using the dedicated baud rate generator this section describes the baud rates that can be set when the clock from the dedicated baud rate generator is selected as the uart transfer clock. n baud rates determined using the dedicated baud rate generator when the transfer clock is generated using the dedicated baud rate generator, the machine clock is divided with the machine clock prescaler. the divided machine clock is divided by the transfer clock division ratio selected with the clock selector again.the machine clock division ratios are common to the asynchronous and synchronous baud rates, but different values set internally are selected as the transfer clock division ratio for the asynchronous and synchronous baud rates. the actual transfer rate can be calculated using the following formulas: asynchronous baud rate = f x (prescaler division ratio) x (asynchronous transfer clock division ratio) synchronous baud rate = f x (prescaler division ratio) x (synchronous transfer clock division ratio) f : machine clock frequency l division ratios for the prescaler (common to asynchronous and synchronous baud rates) each machine clock division ratio is selected using the div3 to div0 bits of the cdcr register as listed in table 13.6-1. table 13.6-1 selection of each division ratio for the machine clock prescaler md div3 div2 div1 div0 divided by (div) 0 CCCC stop 10000 1 10001 2 10010 3 10011 4 10100 5 10101 6 10110 7 10111 8
MB90560 series chapter 13 uart 379 l synchronous transfer clock division ratios a division ratio for synchronous baud rates is selected using the cs2 to cs0 bits of the mode control register (smr0/1) as listed in table 13.6-2. table 13.6-2 selection of synchronous baud rate division ratios the division ratio is calculated supposing that machine cycle f = 16 mhz and div = 4. l asynchronous transfer clock division ratios a division ratio for asynchronous baud rates is selected using the cs2 to cs0 bits of the mode control register (smr0/1) as listed in table 13.6-3. table 13.6-3 selection of synchronous baud rate division ratios the division ratio is calculated supposing that machine cycle f = 16 mhz and div = 1. cs2 cs1 cs0 division ratio for clk synchronization calculation formula scki 0 0 0 16m ( f ? div)/1 ( f ? div)/1 001 8m ( f ? div)/2 ( f ? div)/2 010 4m ( f ? div)/4 ( f ? div)/4 011 2m ( f ? div)/8 ( f ? div)/8 100 1m ( f ? div)/16 ( f ? div)/16 1 0 1 500k ( f ? div)/32 ( f ? div)/32 cs2 cs1 cs0 asynchronus (start- stop synchronization) calculation formula scki 0 0 0 76923 ( f ? div)/(8x13x2) ( f ? div)/(13x1) 0 0 1 38461 ( f ? div)/(8x13x4) ( f ? div)/(13x2) 0 1 0 19230 ( f ? div)/(8x13x8) ( f ? div)/(13x4) 011 9615 ( f ? div)/(8x13x16) ( f ? div)/(13x8) 1 0 0 500k ( f ? div)/(8x2x2) ( f ? div)/2 1 0 1 250k ( f ? div)/(8x13x4) ( f ? div)/4
380 chapter 13 uart MB90560 series l internal timer when cs2 to cs0 are set to 110 and the internal timer is selected, the formulas for calculating baud rates (when using the reload timer) are as follows: asynchronous (start-stop synchronization): ( f ? n)/(16 x 2 x (n + 1)) clk synchronization: ( f ? n)/(2 x (n + 1)) n: timer count clock sourcen: timer reload value in mode 2 (clk synchronization mode), sck0 is up to three clocks later than scki. a logically attainable transfer rate is 1/3 of the system clock frequency. however, 1/4 of the system clock frequency is recommended as taken from the actual specifications. l external clock when cs2 to cs0 are set to 111 and the external clocks are selected, note the following: if the external clock frequency is specified as f, the following baud rates are assumed: asynchronous (start-stop synchronization): f/16 clk synchronization: f ' note that f is up to 1/2 of the machine clock, and f' is up to 1/8 of the machine clock.
MB90560 series chapter 13 uart memo
382 chapter 13 uart MB90560 series 13.6 uart baud rates 13.6.2 baud rates determined using the internal timer (16-bit reload timer 0) this section describes the settings used when the internal clock supplied from 16-bit reload timer 0 is selected as the uart transfer clock. it also shows the baud rate calculation formulas. n baud rates determined using the internal timer (16-bit reload timer 0) writing 110 b to the cs2 to cs0 bits of the mode control register (smr0/1) selects the baud rate determined using the internal timer. any baud rate can be set by specifying a prescaler division ratio and reload value for 16-bit reload timer 0. figure 13.6-2 shows the baud rate selection circuit for the internal timer. figure 13.6-2 baud rate selection circuit for the internal timer (16-bit reload timer 0) l baud rate calculation formulas f : machine clock frequency x: division ratio for the prescaler of 16-bit reload timer 0 (2 1 , 2 3 , or 2 5 ) n: reload value for 16-bit reload timer 0 (0 to 65535) smr1 : cs2~0="110 b " smr1 md1, md0 (selects the internal timer.) clock selector 16-bit reload timer output (the frequency is specified with a prescaler division ratio and reload value.) 1/1 (synchronous) 1/16 (asynchronous) baud rate (clock synchronous/asynchronous selection) : asynchronous baud rate = f x (n + 1) x 2 x 16 bps synchronous baud rate = f bps x (n + 1) x 2
MB90560 series chapter 13 uart 383 l examples of setting reload values (machine clock: 7.3728 mhz) table 13.6-4 baud rates and reload values x : division ratio for the prescaler of 16-bit reload timer 0 C : setting not allowed baud rate reload value clock asynchronous (start-stop synchronization) clock synchronous x=2 1 (machine cycle divided by 2) x=2 3 (machine cycle divided by 8) x=2 1 (machine cycle divided by 2) x=2 3 (machine cycle divided by 8) 38400 2 C 47 11 19200 5 C 95 23 9600 11 2 191 47 4800 23 5 383 95 2400 47 11 767 191 1200 95 23 1535 383 600 191 47 9071 767 300 383 95 6143 1535
384 chapter 13 uart MB90560 series 13.6 uart baud rates 13.6.3 baud rates determined using the external clock this section describes the settings used when the external clock is selected as the uart transfer clock. it also shows the baud rate calculation formulas. n baud rates determined using the external clock the following three settings are required to select the baud rate determined by using the external clock: ? write 111 b to the cs2 to cs0 bits of the serial mode control register (smr0/1) to select the baud rate determined by using the external clock input. ? set the sck0/p40 and sck1/p62 pins as input ports (ddr4: bit 0 = 0 and ddr6: bit 2 = 0). ? write 0 to the scke bit of the serial mode control register (smr0/1) to set the pin as an external clock input pin. as shown in figure 13.6-3, a baud rate is selected using the external clock input from the sck1 pin. to change the baud rate, the external input clock cycle must be changed because the internal division ratio is fixed. figure 13.6-3 baud rate selection circuit for the external clock l baud rate calculation formulas asynchronous baud rate = f/16 synchronous baud rate = f f: external clock frequency (up to 2 mhz) smr1 : cs2~0="111 b " sck1/p62 smr1 md1, md0 (select the external clock.) pin clock selector 1/1 (synchronous) 1/16 (asynchronous) baud rate (synchronous/asynchronous selection)
MB90560 series chapter 13 uart 385 memo
386 chapter 13 uart MB90560 series 13.7 operation of uart uart operates in operation modes 0 and 2 for normal bidirectional serial communication and in operation mode 1 for master-slave communication. n operation of uart l operation modes there are three uart operation modes: modes 0 to 2. as listed in table 13.7-1, an operation mode can be selected according to the inter-cpu connection method and data transfer mode. table 13.7-1uart operation mode C : setting not possible *1 : "+1" indicates the address/data selection bit (a/d) for communication control. *2 :during reception, only one stop bit can be detected. operation mode 1 of uart is used only from the master system during master-slave connection. l inter-cpu connection method one-to-one connection (normal mode) and master-slave connection (multiprocessor mode) can be selected. for either connection method, the data length, whether to enable parity, and the synchronization method must be common to all cpus. select an operation mode as follows: ? in the one-to-one connection method, operation mode 0 or 2 must be used in the two cpus. select operation mode 0 for asynchronous transfer mode and operation mode 2 for synchronous transfer mode. ? select operation mode 1 for the master-slave connection method and use it from the master system. select "when parity is disabled" for this connection method. l synchronization method asynchronous mode (start-stop synchronization) or clock synchronous mode can be selected in any operation mode. l signal uart can treat data only in non-return to zero (nrz) format. operation mode data length synchronizati on mode stop bit length when parity is disabled when parity is enabled 0 normal mode 7 or 8 bits asynchronous 1 or 2 bits * 2 1 multiprocessor 8+1* 1 C asynchronous 2 normal mode 8 C synchronous none
MB90560 series chapter 13 uart 387 l operation enable bit uart controls both transmission and reception using the operation enable bit for txe (transmission) and that for rxe (reception). if each of the operations is disabled, stop it as follows: ? if reception operation is disabled during reception (data is input to the reception shift register), finish frame reception and store the received data in the serial input data register (sidri). then stop the reception operation. ? if the transmission operation is disabled during transmission (data is output from the transmission shift register), wait until there is no data in the serial output data register (sodr0/1) before stopping the transmission operation.
388 chapter 13 uart MB90560 series 13.7 operation of uart 13.7.1 operation in asynchronous mode (operation modes 0 and 1) when uart is used in operation mode 0 (normal mode) or operation mode 1 (multiprocessor mode), the asynchronous transfer mode is selected. n operation in asynchronous mode l transfer data format transfer data begins with the start bit (level l) and ends with the stop bit (level h). the data of the specified data bit length is transferred in lsb first mode. ? in operation mode 0, the length of data with no parity is fixed to 7 bits, and that of data with parity is fixed to 8 bits. ? in operation mode 1, the length of data is fixed to 8 bits with an address/data (a/d) selection bit added instead of parity. figure 13.7-1 shows the data format in asynchronous mode. figure 13.7-1 transfer data format (operation modes 0 and 1) l transmission operation transmission data is written to the serial output data register (sodr0/1) when the transmission data empty flag bit (ssr1: tdre) is 1. this data is transmitted if the transmission operation is enabled (scr0/1: txe=1). the tdre flag is again set to 1 when the transmission data is transferred to the transmission shift register and its transmission starts. then, the next transmission data gets ready to be set. at this point, a transmission interrupt request is generated that the next transmission data can be set in the sodr0/1 register if that request is enabled (ssr0/1: tie=1). the tdre flag is cleared to 0 when the transmission data is written to sodr0/1. l reception operation reception operation is performed every time it is enabled (scr0/1: rxe=1). when a start bit is detected, a frame of data is received according to the data format specified by the serial control register (scr0/1). after the frame has been received, the receive data full flag bit (ssr0/1: rdrf) is set to 1. however, the error flag is set if an error occurs. at this point, a reception interrupt request is output if it is enabled (ssr1: tie=1). check each flag of the serial status reister(ssr0/1). if the reception is normal, read the serial input data register (sidr0/1). if an error is found, proceed to error handling. the rdrf flag is cleared to 0 every time receive data is read from sidr0/1. d7/p sp st d0 d1 d2 d3 d5 d4 d6 d7 a/d sp st d0 d1 d2 d3 d5 d4 d6 [operation mode 0] [operation mode 1] * : d7 (bit 7) when parity is not provided p (parity) when parity is provided st : start bit sp : stop bit a/d : address/data selection bit in operation mode 1 (multiprocessor mode) *
MB90560 series chapter 13 uart 389 l stop bit for transmission, 1 or 2 bits can be selected. during reception however, the first bit is the only one that is always checked. l error detection ? in mode 0, parity, overrun, and framing errors can be detected. ? in mode 1, overrun and framing errors can be detected but parity errors cannot be detected. l parity 0 parity can only be used in operation mode 0 (asynchronous, normal mode). whether to provide parity can be specified using the pen bit of the serial control register (scr0/1). even or odd parity can also be specified using the p bit of the serial control register (scr0/1). in operation mode 1 (asynchronous, multiprocessor mode) and operation mode 2 (synchronous, normal mode), parity cannot be used. figure 13.7-2 shows both transmission and receive data when parity is enabled. figure 13.7-2 transmission data when parity is enabled sin1 1011000 sot1 1011001 sot1 1011000 st sp st sp st sp a parity error occurs during reception with even parity. (scr1: p=0) transmission with even parity (scr1: p=0) transmission with odd parity (scr1: p=1) data parity st : start bit sp : stop bit note : parity is disabled in operation modes 1 and 2.
390 chapter 13 uart MB90560 series 13.7 operation of uart 13.7.2 operation in synchronous mode (operation mode 2) the clock synchronous transfer method is used for uart operation mode 2 (normal mode). n operation in synchronous mode (operation mode 2) l transfer data format in synchronous mode, 8-bit data is transferred using the lsb first method, in which start and stop bits are not added. figure 13.7-3 shows the data format in clock synchronous mode. figure 13.7-3 transfer data format (operation mode 2) l clock supply in clock synchronous mode (i/o extended serial), as same number of clock as the number of transmission and reception bits must be supplied. ? when the internal clock (dedicated baud rate generator or internal timer) is selected, the data receiving synchronous clocks is generated automatically if data is transmitted. ? when the external clock is selected, confirm that the transmission side uart serial output data register (sodr0/1) contains data (ssr0/1: tdre=0). then, clocks for just 1 byte must be supplied from outside. the mark level (h) must be retained before transmission starts and after it is complete. l error detection only overrun errors can be detected; parity and framing errors cannot be detected. 10110 rxe, txe lsb msb transmission data writing transmitting and receiving clocks transmission and receive data data mark level 010
MB90560 series chapter 13 uart 391 l initialization the following shows the set values of each control register using the synchronous mode: [serial mode control register (smr0/1)] md1,md0: "10 b " cs2,cs1,cs0: specify clock input using the clock selector. scke : 1 for dedicated baud rate generator or internal timer 0 for clock output and external clock (clock input) soe: 1 for transmission; 0 for reception only [serial control register (scr0/1)] pen: "0" p,sbl,a/d: these bits make no sense. cl: 1 (8-bit data) rec: 0 (the error flag is cleared for initialization.) rxe,txe: at least one of the two bits is set to 1. [serial status register (ssr0/1)] rie: 1 when using interrupts; 0 when using no interrupts. tie: "0" l starting communication write data to the serial output data register (sodr0/1) to start communication. temporary data must be written to sodr0/1 to start communication for reception. l ending communication the rdrf flag of the serial status register (ssr0/1) is set to 1 when transmission or reception of a data frame is complete. during reception, check the overrun error flag bit (ssr0/1) to see if communication is performing normally.
392 chapter 13 uart MB90560 series 13.7 operation of uart 13.7.3 bidirectional communication function (normal mode) in operation mode 0 or 2, normal serial bidirectional communication (one-to-one connection) is available. select operation mode 0 for asynchronous communication and operation mode 2 for synchronous communication. n bidirectional communication function the settings shown in figure 13.7-4 are required to operate uart in normal mode (operation mode 0 or 2). figure 13.7-4 settings for uart1 operation mode 0 l inter-cpu connection as shown in figure 13.7-5, interconnect two cpus. figure 13.7-5 connection example of uart1 bidirectional communication cl ad rxe txe rec pen p sbl scr1, smr1 000 01010 rie tie cs1 cs0 scke soe bch md1 md0 cs2 rdrf tdre pe ore fre ssr1, sidr1/sodr1 ddr6*1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 *1 : set bit 7 of ddr2 and bit 0 of ddr4 to use uart0. mode 0 mode 2 mode 0 mode 2 set transmit data (during writing). retain receive data (during reading). : bit used x : bit not used 1 : set "1". 0 : set "0". : set "0" to use an input pin. - sot1 sin1 sck1 sot1 sin1 sck1 cpu-1 cpu-2 output input
MB90560 series chapter 13 uart 393 l communication procedure communication starts from the transmitting system at an optional timing when transmission data has been prepared. an ans is returned periodically (byte by byte in this example) when the receiving system receives transmission data. figure 13.7-6 shows an example of a bidirectional communication flowchart. figure 13.7-6 example of bidirectional communication flowchart no no yes yes (transmitting system) (receiving system) start start set operation mode (0 or 2) set operation mode(same mode as that for the transmitting side) set 1-byte data in sodr and perform communication data transmission data transmission any received data? any received data? read and process received data. read and process received data. transmit 1-byte data (ans)
394 chapter 13 uart MB90560 series 13.7 operation of uart 13.7.4 master-slave communication function (multiprocessor mode) with uart, communication with multiple cpus connected in master-slave mode is available. however, uart can be used only from the master system. n master-slave communication function the settings shown in figure 13.7-7 are required to operate uart in multiprocessor mode (operation mode 1). figure 13.7-7 settings for uart operation mode 1 l inter-cpu connection as shown in figure 13.7-8, a communication system consists of one master cpu and multiple slave cpus connected to two communication lines. uart1 can be used only from the master cpu. figure 13.7-8 connection example of uart master-slave communication cl ad rxe txe rec pen p sbl scr1, smr1 01001 0 rie tie cs1 cs0 scke soe bch md1 md0 cs2 rdrf tdre pe ore fre ssr1, sidr1/sodr1 ddr6 (*1) bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 set transmission data (during writing). retain receive data (during reading). *1 : set bit 6 of ddr3 and bit 0 of ddr4 to use uart0. : bit used x : bit not used 1 : set "1". 0 : set "0". : set "0" to use an input pin. - sot1 sin1 sot sin sot sin master cpu slave cpu #0 slave cpu #1
MB90560 series chapter 13 uart 395 l function selection select the operation mode and data transfer mode for master-slave communication as shown in table 13.7-2. table 13.7-2 selection of the master-slave communication function l communication procedure when the master cpu transmits address data, communication starts. the a/d bit in the address data is set to 1, and the communication destination slave cpu is selected. each slave cpu checks the address data using a program. when the address data indicates the address assigned to a slave cpu, the slave cpu communicates with the master cpu (ordinary data). figure 13.7-9 shows a flowchart of master-slave communication (multiprocessor mode). figure 13.7-9 master-slave communication flowchart operation mode data parity synchronizati on method stop bit master cpu slave cpu address transmiss ion and reception mode 1 C a/d="1" + 8-bit address a/d="0" + 8-bit data none asynchronous 1 or 2 bits data transmiss ion and reception yes no yes no (master cpu) start set operation mode to 1 set sin pin as the serial data input pin set 1-byte data for selecting the slave cpu (address data) in d0 to d7,and transmit data (a/d=1) set 0 in a/d enable reception operation communicate with slave cpu is communication complete? communicating with another slave cpu? disable reception operation end
396 chapter 13 uart MB90560 series 13.8 notes on using uart notes on using uart are given below. n notes on using uart l enabling operations in uart, the serial control register (scr0/1) has both txe (transmission) and rxe (reception) operation enable bits. both transmission and reception operations must be enabled before the transfer starts because they have been disabled as the default value (initial value). the transfer can also be canceled by disabling its operation as required. l communication mode setting set the communication mode while the system is not operating. if the mode is set during transmission or reception, the transmission or reception data is not guaranteed. l synchronous mode uart clock synchronous mode (operation mode 2) uses clock control (i/o extended serial) mode, in which start and stop bits are not added to the data. l transmission interrupt enabling timing the default (initial value) of the transmission data empty flag bit (ssr0/1: tre) is 1 (no transmission data and transmission data write enable state). a transmission interrupt request is generated as soon as the transmission interrupt requests are enabled (ssr0/1: tie=1). be sure to set the tie flag to 1 after setting the transmission data.
MB90560 series chapter 13 uart 397 memo
398 chapter 13 uart MB90560 series 13.9 sample program for uart this section contains a sample program for uart. n sample program for uart l processing specifications the uart1 bidirectional communication function (normal mode) is used to perform serial transmission and reception. ? operation mode 0, asynchronous mode, eight data bits, two stop bits, and no parity are set. ? the p60/sin1 and p61/sot1 pins are used for communication. ? the dedicated baud rate generator is used and the baud rate is set to about 9600 bps. ? character 13h is transmitted from the sot1 pin and is received using an interrupt. ? the machine clock ( f ) is assumed to be 16 mhz. l coding example icr13 equ 0000bdh ; uart1 transmission interrupt control register icr13 equ 0000bdh ; uart1 reception interrupt control register ddr3 equ 000013h ; port-3 data direction register smr1 equ 000024h ; mode control register 1 scr1 equ 000025h ; control register 1 sidr1 equ 000026h ; input data register 1 ssr1 equ 000026h ; output data register 1 sodr1 equ 000027h ; status register 1 rec equ scr1:2 ; reception error flag clear bit ;-------main program------------------------------------------------------------------------------------------------ code cseg abs = 0ffh start: ; : ; assumes that stack pointer (sp) has already been ; initialized. and ccr,#0bfh ; disables interrupts. mov i:icr13,#00h ; interrupt level 0 (highest) mov i:ddr3,#00000000b ; sets sin0 pin as input pin mov i:smr1,#00000001b ; operation mode 0 (asynchronous) ; uses dedicated baud rate generator (9615 bps) ; disables clock pulse output and enables data output. mov i:scr1,#00010011b ; no parity and two stop bits ; clears eight data bits and reception error flag. ; enables transmission and reception operations. mov i:ssr1,#00000010b ; disables transmission interrupts and enables reception ; interrupts. mov i:sodr1,#13h ; writes transmission data. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h bra loop ;-------interrupt program------------------------------------------------------------------------------------------- wari: mov a,sidr1 ; reads receive data. clrb i:rec ; clears reception interrupt request flag. ; :
MB90560 series chapter 13 uart 399 ; user processing ; : reti ; returns from the interrupt. code ends ;-------vector setting------------------------------------------------------------------------------------------------ vect cseg abs=0ffh org 0ff68h ; sets vector for interrupt #37 (25 h ). dsl wari org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends

chapter 14 dtp/external interrupt circuit this chapter describes the functions and operation of the dtp/external interrupt circuit. 14.1 overview of the dtp/external interrupt circuit............................. 402 14.2 configuration of the dtp/external interrupt circuit ...................... 404 14.3 dtp/external interrupt circuit pins............................................... 406 14.4 dtp/external interrupt circuit registers....................................... 408 14.5 operation of the dtp/external interrupt circuit ............................ 414 14.6 usage notes on the dtp/external interrupt circuit ...................... 420 14.7 sample programs for the dtp/external interrupt circuit.............. 422
402 chapter 14 dtp/external interrupt circuit MB90560 series 14.1 overview of the dtp/external interrupt circuit the data transfer peripheral, dtp/external interrupt circuit is located between external peripherals and the f 2 mc-16lx cpu. it receives interrupt requests and data transfer requests from peripherals and passes them to the cpu to generate external interrupt requests or activate the extended intelligent i/o service (ei 2 os). n dtp/external interrupt functions the dtp/external interrupt circuit is activated by the signal supplied to a dtp/external interrupt pin. the cpu accepts the signal using the same procedure it uses for normal hardware interrupts and generates external interrupts or activates the extended intelligent i/o service (ei 2 os). if the extended intelligent i/o service (ei 2 os) is disabled when an interrupt request is accepted by the cpu, the circuit executes its external interrupt function and branches to an interrupt routine. if ei 2 os is enabled, the circuit executes its dtp function, which performs automatic data transfer using ei 2 os and branches to an interrupt processing routine after the data transfer has been performed a specified number of times. table 14.1-1 provides an overview of the dtp/external interrupt circuit. table 14.1-1 overview of the dtp/external interrupt circuit icr: interrupt control register external interrupt function dtp function input pins eight(p10/int0 to p16/int6 and p63/int7) interrupt cause by using the request level setting register (elvr), the level or edge to be detected can be selected for each pin. input of h level or l level or ris- ing edge or falling edge input of h level or l level interrupt number #25 (19 h ) to #28 (1c h ) interrupt control the output of interrupt requests is enabled and disabled using the dtp/ interrupt enable register (enir). interrupt flag interrupt causes are stored in the dtp/interrupt cause register (eirr). processing selection ei 2 os is disabled (icr: ise = 0). ei 2 os is enabled (icr: ise = 1). processing the circuit branches to an external interrupt processing routine. the circuit performs automatic data transfer using ei 2 os for a specified number of times and then branches to an interrupt routine.
MB90560 series chapter 14 dtp/external interrupt circuit n interrupt of the dtp/external interrupt circuit and ei 2 os table 14.1-2 interrupt of the dtp/external interrupt circuit and ei 2 os d : available when not using an interrupt request that shares the icr07 and icr08 registers. channel interrupt number interrupt control register vector table address ei 2 os register name address lower upper bank int0/int1 #25 (19h) icr07 0000b6h ffff98h ffff99h ffff9ah d int2/int3 #26 (1ah) ffff94h ffff95h ffff96h int4/int5 #27 (1bh) icr08 0000b7h ffff90h ffff91h h ffff92h int6/int7 #28 (1ch) ffff8ch ffff8dh ffff8eh
404 chapter 14 dtp/external interrupt circuit MB90560 series 14.2 configuration of the dtp/external interrupt circuit the dtp/external interrupt circuit consists of four blocks: ? dtp/interrupt input detection circuit ? request level setting register (elvr) ? dtp/interrupt cause register (eirr) ? dtp/interrupt enable register (enir) n block diagram of the dtp/external interrupt circuit figure 14.2-1 block diagram of the dtp/external interrupt circuit request level setting register (elvr) p10/int0 pin p11/int1 pin p12/int2 pin p13/int3 pin p14/int4 pin p15/int5 pin lb7 la7 lb6 la6 lb5 la5 lb4 la4 lb3 la3 lb2 la2 lb1 la1 lb0 la0 p16/int6 pin p63/int7 pin selector selector selector selector selector selector selector selector er7 er6 er5 er4 er3 er2 er1 er0 en7 en6 en5 en4 en3 en2 en1 en0 interrupt request number #25(19h) #26(1ah) #27(1bh) #28(1ch) internal data bus dtp/interrupt cause register (eirr) dtp/interrupt enable register (enir)
MB90560 series chapter 14 dtp/external interrupt circuit l dtp/external interrupt input detection circuit upon detecting the level or edge selected for each pin by the interrupt request level setting register (elvr), this circuit sets to 1 the er bit of the dtp/external interrupt cause register (eirr) that corresponds to the pin. l request level setting register (elvr) this register selects the effective level or edge for each pin. l dtp/interrupt cause register (eirr) this register stores dtp/external interrupt causes. it contains an external interrupt request flag bit for each pin. the bit is set to 1 if a valid signal is input to the corresponding pin. l dtp/interrupt enable register (enir) this register enables and disables external interrupts for each pin.
406 chapter 14 dtp/external interrupt circuit MB90560 series 14.3 dtp/external interrupt circuit pins this section describes the dtp/external interrupt circuit pins and provides a pin block diagram. n dtp/external interrupt circuit pins the dtp/external interrupt circuit pins are also used as general ports. table 14.3-1 lists the pin functions, i/o formats, and settings required to use the dtp/external interrupt circuit. table 14.3-1 dtp/external interrupt circuit pins pin name function i/o format pull-up resistor standby control setting required to use pins p10/int0 port 1 input- output/external interrupt input cmos output/ cmos hysteresis input select- able not pro- vided set the pin as an input port (ddr1: bit0 = 0) p11/int1 set the pin as an input port (ddr1: bit1 = 0) p12/int2 set the pin as an input port (ddr1: bit2 = 0) p13/int3 set the pin as an input port (ddr1: bit3 = 0) p14/int4 set the pin as an input port (ddr1: bit4 = 0) p15/int5 set the pin as an input port (ddr1: bit5 = 0) p16/int6 set the pin as an input port (ddr1: bit6 = 0) p41/int7 port 1 input- output/external interrupt input not pro- vided set the pin as an input port (ddr6: bit3 = 0)
MB90560 series chapter 14 dtp/external interrupt circuit n block diagram of the dtp/external interrupt circuit pins figure 14.3-1 block diagram of the dtp/external interrupt circuit pins (for p10/int0 ~ p16/int6 only) figure 14.3.2 block diagram of the dtp/external interrupt circuit pins (for p63/ int7 only) rdr pdr (port data register) pdr read pdr write output latch ddr read ddr write direction latch ddr (port direction register) pin standby control (spl = 1) pull-up resistor about 50k peripherial input (int) internal data bus p10/int0 p16/int6 to pdr (port data register) pdr read pdr write output latch ddr read ddr write direction latch ddr (port direction register) pin standby control (spl = 1) peripherial input (int) internal data bus p63/int7
408 chapter 14 dtp/external interrupt circuit MB90560 series 14.4 dtp/external interrupt circuit registers this section describes dtp/external interrupt circuit registers. figure 14.4-2 dtp/external interrupt circuit registers dtp/interrupt cause register (eirr) dtp/interrupt enable register (einr) request level setting register (elvr) 000031 h 000033 h address , 30 h , 32 h bit7 bit8 bit0 bit15
14.4 dtp/external interrupt circuit registers MB90560 series chapter 14 dtp/external interrupt circuit 409 14.4.1 dtp/interrupt cause register (eirr) the dtp/interrupt cause register (eirr) stores and clears interrupt causes. n dtp/interrupt cause register (eirr) figure 14.4-2 dtp/interrupt cause register (eirr) table 14.4-1 function description of each bit of the dtp/interrupt cause register (eirr) bit name function bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 er7 to er0: external interrupt request flag bits each of these bits is set to 1 if a signal with the edge or level selected by the request level setting register (elvr) is input to the dtp/external interrupt pin (stores an interrupt cause). if these bits and corresponding bits en7 to en0 of the dtp/ interrupt enable register (enir) are 1, an interrupt request is output to the cpu. writing 0 to this bit clears the bit. writing 1 to this bit does not change the bit value and has no effect on other bits. if more than one external interrupt request enable bit is set to 1 (enir: en7 to en0 = 1), clear only the bit that caused the cpu to accept an interrupt (er3 to er0 that is set to 1). do not clear the other bits without reason. when the extended intelligent i/o service (ei2os) is acti- vated, the corresponding external interrupt request flag bit is automatically cleared when the transfer of one data ends. address (enir) r/w r/w r/w r/w initial value 000031 h 00000000 b er7 er6 er5 er4 er3 er2 er1 er0 external interrupt request flag bit no dtp/external interrupt is input. a dtp/external interrupt is input. this bit is cleared. no change, no effect on other bus 0 1 reading writing er7 er0 r/w : read/write enabled : initial value bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0 r/w r/w r/w r/w
410 chapter 14 dtp/external interrupt circuit MB90560 series 14.4 dtp/external interrupt circuit registers 14.4.2 dtp/interrupt enable register (enir) the dtp/interrupt enable register (enir) enables and disables the output of interrupt requests to the cpu. n dtp/interrupt enable register (enir) figure 14.4-3 dtp/interrupt enable register (enir) table 14.4-2 function description of each bit of the dtp/interrupt enable register (enir) bit name function bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 en7 to en0: external interrupt request enable bits each of these bits enables and disables interrupt requests to the cpu. if these bits and corresponding bits er7 to er0 of the dtp/interrupt cause register (eirr) are 1, an interrupt request is output to the cpu. [reference] to use a dtp/external interrupt pin, write 0 to the corre- sponding bit of the port direction register to set the pin as an input port. the states of the dtp/external interrupt pins can be read directly using the port data register regardless of the states of external interrupt request enable bits. bits er7 to er0 of the dtp/interrupt cause register (eirr) are set to 1 if an interrupt cause is detected regardless of the values of external interrupt request enable bits. address r/w r/w r/w r/w initial value (eirr) 000030 h en7 en6 en5 en4 en3 en2 en1 en0 00000000 b external interrupt request enable bits 0 1 an external interrupt request is disabled. an external interrupt request is enabled. en7 en0 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 bit15 bit8 r/w r/w r/w r/w r/w : read/write enabled : initial value
MB90560 series chapter 14 dtp/external interrupt circuit table 14.4-3 correspondence between the dtp/interrupt control registers (eirr and enir) and each channel dtp/external interrupt pin interrupt number external interrupt request flag bit external interrupt request enable bit p63/int7 #28 (1ch) er7 en7 p16/int6 er6 en6 p15/int5 #27 (1bh) er5 en5 p14/int4 er4 en4 p13/int3 #26 (1ah) er3 en3 p12/int2 er2 en2 p11/int1 #25 (19h) er1 en1 p10/int0 er0 en0
412 chapter 14 dtp/external interrupt circuit MB90560 series 14.4 dtp/external interrupt circuit registers 14.4.3 request level setting register (elvr) the request level setting register (elvr) selects the level or edge of the signal input to each dtp/external interrupt pin that is to be detected as a dtp/external interrupt cause. n request level setting register (elvr) figure 14.4-4 request level setting register (elvr) table 14.4-4 function description of each bit of the request level setting register (elvr) bit name function bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 lb7 to lb0 and la7 to la0: request detection selection bits each of these bits selects the level or edge of the signal input to the dtp/external interrupt pin to be detected as a dtp/external interrupt cause. two bits are assigned to each pin. [reference] if the selected detection signal is input to a dtp/external interrupt pin, the external interrupt request flag bit is set to 1 regardless of the settings of the dtp/interrupt enable register (enir). lb 7 lb 0 la 7 la 0 external interrupt request detection selection bits 0 0 the l level is to be detected. 0 0 the h level is to be detected. 1 1 a rising edge is to be detected. 1 1 a falling edge is to be detected. address 000033 h lb3 bit7 bit0 la3 lb2 la2 lb1 la1 lb0 la0 bit6 bit5 bit4 bit3 bit2 bit1 r/w r/w r/w r/w r/w r/w r/w r/w 00000000 b initial value lb7 bit15 bit8 la7 lb6 la6 lb5 la5 lb4 la4 bit14 bit13 bit12 bit11 bit10 bit9 r/w r/w r/w r/w r/w r/w r/w r/w r/w: read/write enabled : initial value 00000000 b
MB90560 series chapter 14 dtp/external interrupt circuit table 14.4-5 correspondence between request level setting register (elvr) and each channel dtp/external interrupt pin interrupt number bit name p63/int7 #28 (1ch) lb7, la7 p16/int6 lb6, la6 p15/int5 #27 (1bh) lb5, la5 p14/int4 lb4, la4 p13/int3 #26 (1ah) lb3, la3 p12/int2 lb2, la2 p11/int1 #25 (19h) lb1, la1 p10/int0 lb0, la0
414 chapter 14 dtp/external interrupt circuit MB90560 series 14.5 operation of the dtp/external interrupt circuit the dtp/external interrupt circuit provides the external interrupt function and the dtp function. this section describes the settings required for each function and the operation of the circuit. n setting the dtp/external interrupt circuit figure 14.5-1 shows the settings required to operate the dtp/external interrupt circuit. figure 14.5-1 dtp/external interrupt circuit set the dtp/external interrupt circuit registers with the following procedure: 1. clear the target bit of the dtp/interrupt enable register (enir) to disable interrupts. 2. set the target bit of the request level setting register (elvr). 3. clear the target bit of the dtp/interrupt cause register (eirr). 4. set the target bit of the dtp/interrupt enable register (enir) to enable interrupts. the procedure for setting the dtp/external interrupt circuit registers must start with disabling the output of external interrupt requests (enir: en7 to en0 = 0). before the output of external interrupt requests can be enabled (enir: en7 to en0 = 1), the corresponding interrupt request flag bits must be cleared (eirr: er7 to er0 = 0). this is in order to avoid interrupt requests from being generated accidentally while the registers are being set. icr08 / icr07 ics3 bit7 bit0 ics2 ics1 ics0 ise il2 il1 il0 bit6 bit5 bit4 bit3 bit2 bit1 ics3 bit15 bit8 ics2 ics1 ics0 ise il2 il1 il0 bit14 bit13 bit12 bit11 bit10 bit9 en7 en6 en5 en4 en3 en2 en1 en0 er7 er6 er5 er4 er3 er2 er1 er0 eirr / enir for the external interrupt function : : : : : 1 used set the bit to "1" when this is used. 0 for the dtp function lb3 la3 lb2 la2 lb1 la1 lb0 la0 lb7 la7 lb6 la6 lb5 la5 lb4 la4 elvr p16 p15 p14 p13 p12 p11 p10 p63 ddr6/1 set the bit to "0" when this is used. specifies "0". specifies "1".
MB90560 series chapter 14 dtp/external interrupt circuit l switching between the external interrupt function and the dtp function switching between the external interrupt function and the dtp function is accomplished by the ise bit of the corresponding interrupt control register (icr). if the ise bit is 1, the extended intelligent i/o service (ei 2 os) is enabled and the circuit executes its dtp function. if it is 0, ei 2 os is disabled and the circuit executes the its external interrupt function. if multiple interrupt requests are assigned to a single icr register, the interrupt level (il2 to il0) is common to all of the interrupt requests. as a rule, when one interrupt request uses ei 2 os, the other interrupt requests cannot use it. n operation of the dtp/external interrupt circuit table 14.5-1 shows the control bits and interrupt causes of the dtp/external interrupt circuit. table 14.5-1 control bit and interrupt cause of the dtp/external interrupt circuit when dtp/external input requests are set, an interrupt request will be generated to the interrupt controller whenever an interrupt cause indicated in the request level setting register (elvr) is received at the corresponding pin. if the ise bit is 0, the interrupt processing microprogram is executed. if it is 1, the extended intelligent i/o service handling (dtp handling) microprogram is executed. dtp/external interrupt circuit interrupt request flag bit eirr: er7 to er0 interrupt request enable bit enir: en7 to en0 interrupt cause input of an effective edge or level to pin int7 to int0
416 chapter 14 dtp/external interrupt circuit MB90560 series figure 14.5-2 shows the operation of the dtp/external interrupt circuit. figure 14.5-2 operation of the dtp/external interrupt circuit elvr cause another request interrupt controller cpu interrupt processing microprogram dtp/external interrupt circuit eirr enrr icr yy icr xx cmp cmp dtp handling routine (ei 2 os is started) transfer data between memory and peripheral update descriptor descriptor data counter interrupt processing routine set again or stop return to cpu processing 1 0 0 1 icr: ise start interrupt processing microprogram 0 accepted by cpu? accepted by interrupt controller? generation of dtp/ external interrupt request start external interrupt flag. processing. clear interrupt flag. return from external interrupt return from dtp handling routine il ilm
14.5 operation of the dtp/external interrupt circuit MB90560 series chapter 14 dtp/external interrupt circuit 417 14.5.1 external interrupt function the dtp/external interrupt circuit has an external interrupt function that generates an interrupt request when a selected signal level is input to a dtp/external interrupt pin. n external interrupt function if the edge or level selected for a dtp/external interrupt pin by the request level setting register (elvr) is detected at that pin, the corresponding external interrupt flag bit of the dtp/interrupt cause register (eirr:er7 to er0) is set to 1. if, in this state, the corresponding interrupt request enable bit of the dtp/interrupt enable register is set to 1 to enable interrupts (enir: en7 to en0 = 1), the interrupt cause is reported to the interrupt controller. the interrupt controller checks the value of the interrupt level (icr: il2 to il0) in relation to those of the interrupt requests from other peripheral functions, the interrupt priority, etc. the cpu checks the value of the interrupt level mask register (ps: ilm2 to ilm0) and the interrupt level, the interrupt enable bit (ps: ccr: 1), etc. when the interrupt request is accepted by the cpu, the cpu executes an internal interrupt processing routine (microprogram) and branches to the interrupt processing routine. in the interrupt processing routine, 0 must be written to the corresponding interrupt request flag bit to clear the interrupt request. ? an er bit is set to 1 if a dtp/external interrupt cause is generated, regardless of the state of the corresponding en bit. ? when the interrupt routine is activated, the er bit that caused the routine to be activated must be cleared. if the er bit is kept at 1, control cannot return from the interrupt. only clear the flag bit that caused the interrupt; do not clear the other bits without reason.
418 chapter 14 dtp/external interrupt circuit MB90560 series 14.5 operation of the dtp/external interrupt circuit 14.5.2 dtp function the dtp/external interrupt circuit has a dtp function that detects a signal supplied to a dtp/external interrupt pin from an external peripheral and activates the extended intelligent i/o service. n operation of the dtp function the dtp function detects a data transfer request signal from an external peripheral to automatically transfer data between memory and the peripheral. the extended intelligent i/o service (ei 2 os) is activated by the external interrupt function using level detection. the operation of the dtp function is the same as that of the external interrupt function up to the point that the cpu accepts an interrupt request. if the operation of ei 2 os is enabled (icr: ise = 1), ei 2 os is activated to start data transfer when an interrupt request is accepted. when the transfer of one data unit ends, the descriptor is updated and the interrupt request flag bit is cleared to wait for the next request from the pin. when the entire transfer using ei 2 os is completed, control is transferred to the interrupt processing routine. the external peripheral signal must be removed only the level of the data transfer request signal (dtp external interrupt cause) within three cycles of the first transfer. figure 14.5-3 example of interfacing to the external peripheral h-level request (elvr: lb0, la0 = 01 b ) input to the int0 pin (dtp external interrupt cause) internal operation of the cpu (microprogram) descriptor selection and reading descriptor updating address bus pin data bus pin read signal write signal read address read data write address write data external peripheral (external memory) external peripheral register data transfer request data, address bus dtp external internal data bus read operation(*1) dtp/external interrupt circuit interrupt request write operation (*3) internal memory *1, *2 must be removed within three machine cycles of transfer. *3 if the extended intelligent i/o service is in periphera ? memory transfer mode. interrupt cause (*2)
MB90560 series chapter 14 dtp/external interrupt circuit memo
420 chapter 14 dtp/external interrupt circuit MB90560 series 14.6 usage notes on the dtp/external interrupt circuit notes on the signal to be input to the dtp/external interrupt circuit, release from standby mode, and interrupts are given below. n usage notes on the dtp/external interrupt circuit l conditions for external peripherals using the dtp function to support the dtp function, external peripherals must be able to clear data transfer requests automatically in response to transfer operations. if a transfer request is not removed within three machine cycles of the start of transfer, the dtp/external interrupt circuit interprets the request as another transfer request. l input polarities of external interrupts ? if the request level setting register (elvr) is set so that an edge is detected, the pulse width must be at least three machine cycles for the edge to be detected. ? if the register is set for level detection, and the level to be detected as an interrupt cause is input, cause f/f in the dtp/interrupt cause register (eirr) is set to 1 to store the cause, as shown in figure 14.6-1. even if the cause is removed, the request to the interrupt controller remains active provided the output of interrupt requests is enabled. thus, to cancel the request to the interrupt controller, clear the external interrupt request flag bit and cause f/f, as shown in figure 14.6-2. figure 14.6-1 clearing the cause retention circuit when a level is specified figure 14.6-2 dtp/external interrupt cause and interrupt request when the output of interrupt requests is enabled dtp/external interrupt cause to the interrupt controller (interrupt request) dtp/interrupt input detection circuit cause f/f (in the eirr register) enable gate the cause is stored until the register is cleared. dtp/external interrupt cause (when the h level is detected) interrupt request to the interrupt controller removal of the interrupt cause becomes inactive by clearing cause f/f.
MB90560 series chapter 14 dtp/external interrupt circuit l notes about interrupts when the external interrupt function is used, control cannot return from the interrupt processing routine if the external interrupt request flag bit is 1 and the output of interrupt requests is enabled. in the interrupt processing routine, the external interrupt request flag bit must be cleared. (when the dtp function is used, ei 2 os automatically clears the bit.) for level detection, the external interrupt request flag bit is set again as soon as it is cleared if the level assumed as an interrupt cause continues to be input. either disable the output of interrupt requests or remove the interrupt cause, if required.
422 chapter 14 dtp/external interrupt circuit MB90560 series 14.7 sample programs for the dtp/external interrupt circuit this section contains sample programs for the external interrupt function and the dtp function. n sample program for the external interrupt function l processing ? the rising edge of the pulse input to the int0 pin is detected, and an external interrupt is generate. l coding example icr07 equ 0000b6h ; interrupt control register for the dtp/external ; interrupt circuit ddr1 equ 000011h ; port 1 direction register enir equ 000030h ; dtp/interrupt enable register eirr equ 000031h ; dtp/interrupt cause register elvrl equ 000032h ; request level setting register elvrh equ 000033h ; request level setting register er0 equ eirr:0 ; int0 interrupt flag bit en0 equ enir:0 ; int0 interrupt enable bit ;-------main program------------------------------------------------------------------------------------------------------ code cseg start: ; : ; assumes that stack pointer (sp) has already been ; initialized. mov i:ddr1,#00000000b ; sets ddr1 as an input port. and ccr,#0bfh ; disables interrupts. mov i:icr07,#00h ; interrupt level: 0 (highest). disables ei 2 os. clrb en0 ; disables int0, using enir. mov i:elvr,#00000010b ; selects the rising edge for int0. clrb i:er0 ; clears the cause for int0 using eirr. setb i:en0 ; enables int0 using enir. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h bra loop ;-------interrupt program------------------------------------------------------------------------------------------------- wari clrb erp ; clears the interrupt request flag. ; : ; user processing ; : reti ; returns from interrupt. code ends
MB90560 series chapter 14 dtp/external interrupt circuit ;-------vector setting----------------------------------------------------------------------------------------------------- vect cseg abs=0ffh org 0ff98h ; sets vector for interrupt #25 (19h). dsl wari org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start n sample program for the dtp function l processing ? the h level of the signal input to the int0 pin is detected, and channel 0 of the extended intelligent i/o service (ei 2 os) is activated. ? data is output from ram to port 0 by dtp processing (ei 2 os). l coding example icr07 equ 0000b6h ; interrupt control register for the dtp/external ; interrupt circuit ddr0 equ 000010h ; port 0 direction register ddr1 equ 000011h ; port 1 direction register enir equ 000030h ; dtp/interrupt enable register eirr equ 000031h ; dtp/interrupt cause register elvrl equ 000032h ; request level setting register elvrh equ 000033h ; request level setting register er0 equ eirr:0 ; int0 interrupt flag bit en0 equ enir:0 ; int0 interrupt enable bit bapl equ 000100h ; buffer address pointer, lower bapm equ 000101h ; buffer address pointer, middle baph equ 000102h ; buffer address pointer, upper iscs equ 000103h ; ei 2 os status register ioal equ 000104h ; i/o address register, lower ioah equ 000105h ; i/o address register, upper dctl equ 000106h ; data counter, lower dcth equ 000107h ; data counter, upper ;-------main program------------------------------------------------------------------------------------------------------ ---------- code cseg start: ; : ; assumes that stack pointer (sp) has already been initialized. mov i:ddr0,#11111111b ; sets ddr0 as an output port. mov i:ddr1,#00000000b ; sets ddr1 as an input port. and ccr,#0bfh ; disables interrupts. mov i:icr07,#08h ; interrupt level: 0 (highest) ; enables ei 2 os. channel 0
424 chapter 14 dtp/external interrupt circuit MB90560 series mov bapl,#00h ; sets the address of the output data mov bapm,#06h ; mov baph,#00h ; mov iscs,#12h ; byte transfer. i/o address fixed. buffer address + 1. transfer from memory to i/o mov ioal,#00h ; specifies port 0 (pdr0) as the transfer destination mov ioah,#00h ; address pointer. mov dctl,#0ah ; number of transfers: 10 mov dcth,#00h ; clrb i:en0 ; disables int0 using enir. mov i:elvr,#00000001b ; selects h level for int0. clrb i:er0 ; clears the cause of int0 using eirr. setb i:en0 ; enables int0 using enir. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h ; bra loop ; ;-------interrupt program------------------------------------------------------------------------------------------------- wari: clrb i:er0 ; clears the interrupt request flag. ; : ; ; switches the channel and changes the transfer address, if required. ; user processing ; specifies processing again, such as the termination of ei 2 os. to terminate the processing, interrupts must be disabled. ; : reti ; returns from the interrupt. code ends ;-------vector setting------------------------------------------------------------------------------------------------------ vect cseg abs=0ffh org 0ff98h ; sets vector for interrupt #11 (0b h ). dsl wari org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
MB90560 series chapter 14 dtp/external interrupt circuit 425 memo

chapter 15 delayed interrupt generator module this chapter describes the functions and operation of the MB90560 series delayed interrupt generator module. 15.1 overview of the delayed interrupt generator module .................. 428 15.2 operation of the delayed interrupt generator module ................. 429
428 chapter 15 delayed interrupt generator module mb90620 series 15.1 overview of the delayed interrupt generator module the delayed interrupt generator module generates interrupts for task switching. by using this module, software can issue and cancel interrupt requests for the f2mc-16lx cpu. n block diagram of the delayed interrupt generator module figure 15.1-1 shows the block diagram of the delayed interrupt generator module. figure 15.1-1 block diagram of the delayed interrupt generator module n delayed interrupt generator module register the configuration of the delayed interrupt generator module (delayed interrupt request register [dirr]) is as follows: the dirr controls the generation or clearing of a delayed interrupt request. writing 1 to this register generates a delayed interrupt request. writing 0 to this register clears the delayed interrupt request. the cause is cleared at reset. both 0 and 1 may be written to the reserved bit area. however, the set bit and clear bit instructions should be used to access this register to prepare for future expansion. f mc-16 bus delayed interrupt request register/ interrupt cause latch 2 dirr address :00009f h bit 15 14 13 12 11 10 9 8 --- --- -r0 0 r r/w initial value the cause is cleared at reset.
mb90620 series chapter 15 delayed interrupt generator module 429 15.2 operation of the delayed interrupt generator module when software causes the cpu to write 1 to the relevant bit of dirr, the request latch in the delayed interrupt generator module is set and an interrupt request is generated to the interrupt controller. n operation of the delayed interrupt generator module when software causes the cpu to write 1 to the relevant bit of dirr, the request latch in the delayed interrupt generator module is set and an interrupt request is generated to the interrupt controller. if the priority of other interrupt requests is lower than that of this interrupt or no other interrupt request is generated, the interrupt controller generates an interrupt request to the f2mc-16lx cpu. the f2mc-16lx cpu compares the ilm bit of the internal ccr register and the interrupt request. when the request level is higher than that of the ilm bit, the cpu starts the hardware interrupt processing microprogram immediately after execution of the current instruction ends. as a result, the interrupt processing routine for this interrupt is executed. this interrupt cause is cleared and task switching is done by writing 0 to the relevant bit of dirr in the interrupt processing routine. figure 15.2-1 shows the operation of the delayed interrupt generator module. figure 15.2-1 operation of the delayed interrupt generator module n note on using the delayed interrupt generator module l delayed interrupt request latch this latch is set by writing 1 to the relevant bit of dirr and cleared by writing 0 to the same bit. note that interrupt processing is restarted the moment control returns from interrupt processing unless software is created to clear the cause in the interrupt processing routine. f mc-16lx cpu delayed interrupt generator module delayed interrupt controller write other request ddir icr vv cmp icr xx icr vv cmp nta icr xx 2

chapter 16 8/10-bit a/d converter this chapter describes the functions and operation of the 8/10-bit a/d converter. 16.1 overview of the 8/10-bit a/d converter.............................................. 432 16.2 configuration of the 8/10-bit a/d converter ....................................... 434 16.3 8/10-bit a/d converter pins................................................................ 436 16.4 8/10-bit a/d converter registers ....................................................... 438 16.5 8/10-bit a/d converter interrupts ....................................................... 446 16.6 operation of the 8/10-bit a/d converter............................................. 447 16.7 usage notes on the 8/10-bit a/d converter....................................... 454 16.8 sample program 1 for single conversion mode using ei2os ........... 456 16.9 sample program 2 for continuous conversion mode using ei2os ... 458 16.10 sample program 3 for stop conversion mode using ei2os .............. 461
432 chapter 16 8/10-bit a/d converter MB90560 series 16.1 overview of the 8/10-bit a/d converter using the rc-type successive approximation conversion method, the 8/10-bit a/d converter converts an analog input voltage into a 10-bit or 8-bit digital value. an input signal is selected from eight channels for analog input pins. the conversion can be activated by software, an internal clock, and 16-bit free-running timer zero detection. n functions of the 8/10-bit a/d converter the converter converts the analog voltage at an analog input pin (input voltage) to a digital value. the converter has the following features: ? the minimum conversion time is 6.13 s (for a machine clock of 16 mhz; includes the sampling time). ? the minimum sampling time is 3.75 s (for a machine clock of 16 mhz). ? the converter uses the rc-type successive approximation conversion method with a sample hold circuit. ? a resolution of 10 bits or 8 bits can be selected. ? up to eight channels for analog input pins can be selected by a program. ? at the end of a/d conversion, an interrupt request can be generated and ei2os can be activated. ? in the interrupt-enabled state, the conversion data protection function prevents any part of the data from being lost through continuous conversion. ? the conversion can be activated by software, 16-bit reload timer 1 (rising edge), and 16-bit free-running timer zero detection edge. table 16.1-1 lists three types of conversion modes. table 16.1-1 8/10-bit a/d converter conversion modes single conversion scan conversion single conversion mode converts the input of a specified channel (single channel) just once. converts the inputs of two or more consecutive channels (up to eight channels) just once. continuous conversion mode converts the input of a specified channel (single channel) repeatedly. converts the inputs of two or more consecutive channels (up to eight channels) repeatedly. stop conversion mode converts the input of a specified channel (single channel), after which it is on standby for the next activation. converts the inputs of two or more consecutive channels (up to eight channels). when a channel has been con- verted, the converter is put on standby for the next activation.
MB90560 series chapter 16 8/10-bit a/d converter 433 n 8/10-bit a/d converter interrupts and ei2os table 16.1-2 8/10-bit a/d converter interrupts and ei2os o: available interrupt no. interrupt control register vector table address ei2os register name address lower upper bank #11 (0b h ) icr00 0000b0 h ffffd0 h ffffd1 h ffffd2 h o
434 chapter 16 8/10-bit a/d converter MB90560 series 16.2 configuration of the 8/10-bit a/d converter the 8/10-bit a/d converter has nine blocks: ? a/d control status register (adcs1, 2) ? a/d data register (adcr1, 2) ? clock selector (input clock selector for activating a/d conversion) ? decoder ? analog channel selector ? sample hold circuit ? d/a converter ? comparator ? control circuit n block diagram of the 8/10-bit a/d converter figure 16.2-1 block diagram of the 8/10-bit a/d converter f 2 m c C 1 6 l x b u s av cc av r avss + an3 an5 an0 an7 an6 an4 an2 an1 adcr1,2 data register adcs1,2 mpx input circuit d/a converter comparator sequential comparison register sample hold circuit a/d control register 1 a/d control register 1 16-bit reload timer 1 16-bit free-running timer zero detection prescaler operating clock decoder
MB90560 series chapter 16 8/10-bit a/d converter 435 l a/d control status register (adcs1, 2) this register selects activation by software or another activation trigger, the conversion mode, and the a/d conversion channel. it also enables or disables interrupt requests, checks the interrupt request status, and indicates whether the conversion has halted or is in progress. l a/d data register (adcr1,2) this register holds the result of a/d conversion and selects the resolution for a/d conversion. l clock selector the clock selector selects the clock for activating a/d conversion. either 16-bit reload timer channel 1 output or 16-bit free-running timer zero detection can be used as the activation clock. l decoder this circuit selects the analog input pin to be used based on the settings of the ane0 to ane2 bits and ans0 to ans2 bits of the a/d control status register (adcs1). l analog channel selector this circuit selects the pin to be used from eight analog input pins. l sample hold circuit this circuit holds the input voltage of the channel selected by the analog channel selector. it samples and holds the input voltage obtained immediately after the activation of a/d conversion. this circuit protects the a/d conversion from any variations in the input voltage during approximation. l d/a converter this circuit generates a reference voltage for comparison with the input voltage maintained by the sample hold circuit. l comparator this circuit compares the input voltage held by the sample hold circuit with the output voltage of the d/a converter to determine which is greater. l control circuit this circuit determines the a/d conversion value based on the decision signal generated by the comparator. when the a/d conversion has been completed, the circuit sets the conversion result in the a/d data register (adcr1, 2) and generates an interrupt request.
436 chapter 16 8/10-bit a/d converter MB90560 series 16.3 8/10-bit a/d converter pins this section describes the 8/10-bit a/d converter pins and provides pin block diagrams. n 8/10-bit a/d converter pins the a/d converter pins are also used as general ports. table 16.3-1 lists the pin functions, i/o formats, and settings required to use the 8/10-bit a/d converter. table 16.3-1 8/10-bit a/d converter pins function pin name pin function input-output signal type pull-up option standby control i/o port setting for using the pin channel 0 p50/an0 port 5 input-out- put or analog input cmos out- put/cmos hysteresis input or analog input not selectable not selectable set port 5 as an input port (ddr5: bits 0 to 7 = 0). set port 5 as an analog input port (ader: bits 0 to 7 = 1) channel 1 p51/an1 channel 2 p52/an2 channel 3 p53/an3 channel 4 p54/an4 channel 5 p55/an5 channel 6 p56/an6 channel 7 p57/an7
MB90560 series chapter 16 8/10-bit a/d converter 437 n block diagrams of the 8/10-bit a/d converter pins figure 16.3-1 block diagram of the p50/an0 to p57/an7 pins ? to use a pin as an input port, set the corresponding bit of the ddr5 register to 0, then add a pull-up resistor to the external pin. set the corresponding bit of the ader register to 0. ? to use the pin as an analog input pin, set the corresponding bit of the ader register to 1. the value read from the pdr5 register is 0. internal data bus ader pdr read pdr write output latch ddr read ddr write direction latch port data direction register (ddr) pin standby control (spl = 1) port data register (pdr) analog input
438 chapter 16 8/10-bit a/d converter MB90560 series 16.4 8/10-bit a/d converter registers this section lists the 8/10-bit a/d converter registers. n 8/10-bit a/d converter registers figure 16.4-1 8/10-bit a/d converter registers 0017h 0035h 15 14 13 12 11 10 9 8 ader 7 6 5 4 3 2 1 0 adcs1 adcs0 0037h adcr1 adcr0
16.4 8/10-bit a/d converter registers MB90560 series chapter 16 8/10-bit a/d converter 16.4.1 a/d control status register 1 (adcs1) a/d control status register 1 (adcs1) selects activation by software or activation trigger, enables or disables interrupt requests, and indicates interrupt request status and whether conversion is halted or in progress. n upper bits of the a/d control status register (adcs1) figure 16.4-2 a/d control status register 1 (adcs1) paus (adcs0) sts1 strt resv sts0 inte 0 1 interrupt request enable bit disables interrupt request output. enables interrupt request output. busy int inte int interrupt request flag bit busy bit a/d conversion has not been completed. a/d conversion has been completed. a/d conveision is halted. a/d conversion is in progress. clears this bit. no change,no effect on other bits. stops the a/d conversion. no change,no effect on other bits. 0 1 reading writing reading writing busy 0 1 strt a/d conversion activation bit ( valid only when activated by software (adc2: ext= 0)) reserved bit resv always write 0 to this bit. r/w r/w r/w r/w r/w r/w r/w w sts1 sts0 a/d activation select bit 0 0 1 1 0 1 0 1 activation by software. activation by external trigger or software. activation by timer or software. activation by external trigger, timer, or software. does not activate the a/d conversion. activate the a/d conversion function. 0 1 paus halt flag bit (valid only when ei 2 os is used) a/d conversion is not halted. a/d conversion is halted. 0 1 000035 h 00000000 b r/w w - : read/write : write only : undefined : initial value bit15 address initial value bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit0
440 chapter 16 8/10-bit a/d converter MB90560 series table 16.4-1 function description of each bit of a/d control status register 1 (adcs1) bit name function bit15 busy: busy bit this bit indicates the operating status of the a/d converter. if the value read from this bit is 0, a/d conversion has halted. if the read value is 1, a/d conversion is in progress. writing 0 to this bit forces the a/d conversion to stop. writing 1 to this bit does not change the bit value and has no effect on other bits. never select forced stop (busy = 0) and software activation (strt = 1) simultaneously. bit14 int: interrupt request flag bit when a/d conversion data is stored in the a/d data register, this bit is set to 1. when both this bit and the interrupt request enable bit (adcs: inte) are 1, an interrupt request is generated. if ei2os has been enabled, it is activated. writing 0 to this bit clears the bit. writing 1 to this bit does not change the bit value and has no effect on other bits. when ei2os is activated, this bit is cleared. when clearing this bit by writing 0 it, do so only while the a/d converter is not operating. bit13 inte: interrupt request enable bit this bit enables or disables interrupt output to the cpu. when both this bit and the interrupt request flag bit (adcs: int) are set to 1, an interrupt request is generated. when ei2os is used, set this bit to 1. bit12 paus: halt flag bit when a/d conversion stops temporarily, this bit is set to 1. this a/d converter has just one a/d data register. in continuous conversion mode, if a conversion result were written before the previous conversion result was read by the cpu, the previous result would be lost. when continuous conversion mode is selected, the program must be written so that the conversion result is automatically transferred to memory by ei2os each time a conversion is completed. this bit also protects against multiple interrupts preventing the completion of conversion data transfer before the next conversion . when a conversion is completed, this bit is set to 1. this status is maintained until ei2os finishes transferring the contents of the data register. meanwhile, the a/d conversion is halted so that no conversion data can be stored. when ei2os completes the transfer, the a/d converter automati- cally resumes the conversion. this bit is valid only when ei2os is used.
MB90560 series chapter 16 8/10-bit a/d converter 441 ( continued ) bit name function bit11 bit10 sts1, sts0: a/d activation select bit these bits select how a/d conversion is to be activated. when two or more activation causes are shared, activation is the result of the cause that occurs first. change the setting during a/d conversion only while there is no corresponding activation cause, since the change becomes effec- tive immediately. bit9 strt: a/d conversion acti- vation bit this bit allows software to start a/d conversion. writing 1 to this bit activates a/d conversion. in stop conversion mode, conversion cannot be reactivated with this bit. never select forced stop (busy = 0) and software activation (strt = 1) simultaneously. bit8 resv: reserved bit always write 0 to this bit.
442 chapter 16 8/10-bit a/d converter MB90560 series 16.4 8/10-bit a/d converter registers 16.4.2 a/d control status register 0 (adcs0) a/d control status register 0 (adcs0) selects the conversion mode and a/d conversion channel. n a/d control status register 0 (adcs0) figure 16.4-3 a/d control status register 0 (adcs0) address 000034 h initial value 00000000 b md1 md0 ans2 ans1 ans0 ane2 ane1 ane0 (adcs: h) bit15 r/w r/w r/w r/w r/w r/w r/w r/w bit8 bit6 bit7 bit5 bit4 bit3 bit2 bit1 bit0 an0 pin an1 pin an2 pin an3 pin an4 pin an5 pin an6 pin an7 pin ane2 00 0 1 00 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 1 1 1 ane1 ane0 a/d conversion end channel select bit an0 pin an1 pin an2 pin an3 pin an4 pin an5 pin an6 pin an7 pin ans2 00 0 1 halt the current conversion channel number the last conversion channel number read during conversion read during a pause in stop conversion mode 00 1 1 1 0 0 0 0 1 0 0 1 1 1 1 0 1 1 1 ans1 ans0 a/d conversion start channel select bit md1 md0 a/d conversion mode select bit 00 01 10 11 single conversion mode 1 (reactivation allowed during operation) single conversion mode 2 (reactivation not allowed during operation) continuous conversion mode (reactivation not allowed during operation) stop conversion mode (reactivation not allowed during operation) r/w: read/write : initial value
MB90560 series chapter 16 8/10-bit a/d converter 443 table 16.4-2 function description of each bit of a/d control status register 0 (adcs0) bit name function bit7 bit6 md1, md0: a/d conversion mode select bit these bits select the conversion mode of the a/d conversion function. the two-bit value of the md1 and md0 bits determines the mode that is selected from among four modes: single conversion mode 1, single conversion mode 2, continuous conversion mode, and stop conversion mode. the operation in each mode is described below: single conversion mode 1: just a single a/d conversion from the channel set by ans2 to ans0 to the channel specified by ane2 to ane0 is performed. reactivation during operation is allowed. single conversion mode 2: just a single a/d conversion from the channel set by ans2 to ans0 to the channel specified by ane2 to ane0 is performed. reactivation during operation is not allowed. continuous conversion mode: a/d conversion from the channel set by ans2 to ans0 to the channel specified by ane2 to ane0 is performed repeatedly. the repeated conversion continues until it is stopped by the busy bit. reactivation during operation is not allowed. stop conversion mode: a/d conversion from the channel set by ans2 to ans0 to the channel specified by ane2 to ane0 is performed repeatedly with a pause after the conversion of each channel. the repeated conversion continues until it is stopped by the busy bit. reactivation during operation is not allowed. in the pause state, the conversion is reactivated when an activation cause selected by the sts1 and sts0 bits of adcs1 is generated. in the single conversion modes, continuous conversion mode, and stop conversion mode, no reactivation by a timer, external trigger, or software is allowed. bit5 bit4 bit3 ans2, ans1, ans0: a/d conversion start channel select bit these bits set the a/d conversion start channel and indicate the number of the current conversion channel. when activated, a/d conversion starts from the channel specified by these bits. during a/d conversion, the bits indicate the number of the current conversion channel. during a pause in stop conversion mode, the bits indicate the number of the last conversion channel. bit2 bit1 bit0 ane2, ane1, ane0: a/d conversion end channel select bit these bits set the a/d conversion end channel. when activated, a/d conversion is performed up to the channel specified by these bits. when these bits specify the channel specified by ans2 to ans0, just that channel is converted. in continuous or stop conversion mode, the start channel specified by ans2 to ans0 is converted after the channel specified by these bits. if the start channel is greater than the end channel, the start channel to an7 and an0 to the end channel are converted in that order in a single series of conversions.
444 chapter 16 8/10-bit a/d converter MB90560 series 16.4 8/10-bit a/d converter registers 16.4.3 a/d data register (adcr0, 1) the a/d data register (adcr0, 1) holds the result of a/d conversion and selects the resolution of a/d conversion. n a/d data register (adcr0,1) figure 16.4-4 a/d data register (adcr0, 1) d0 to d9 ct1 ct0 sampling time setting bit conversion data st1 st0 44 machine cycles (5.50s@8mhz) 66 machine cycles (4.12s@16mhz) 88 machine cycles (5.50s@16mhz) 176 machine cycles (11.0s@16mhz) 20 machine cycles (2.5s@8mhz) 32 machine cycles (2.0s@16mhz) 48 machine cycles (3.0s@16mhz) 128 machine cycles (8.0s@16mhz) 10-bit resolution mode (d9 to d0) 8-bit resolution mode (d7 to d0) s10 ad data bit ad data bit comparison time setting bit 0 1 0 0 1 1 0 1 0 1 0 0 1 1 0 1 0 1 000037h s10 st1 st0 ct1 ct0 - d8 d9 d7 d6 d5 d4 d3 d2 d0 d1 bit15 bit14 bit13 bit12 bit1 bit0 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 r/w w w w w - r r r r r r r r r r 00101 initial value -xx xxxxxxxx b - : not used r : read only w : write only x : undefined : initial value
MB90560 series chapter 16 8/10-bit a/d converter 445 table 16.4-3 function description of each bit of a/d control status register 0 (adcs0) ? to rewrite the s10 bit, do so while the a/d is in a pause before conversion. if the bit is rewritten after the conversion, the contents of adcr become undefined. ? to read the contents of the adcr register in 10-bit mode, use a word transfer instruction (movw a, 002eh, etc.). bit name function bit15 s10: a/d conversion resolution selection bit this bit selects an a/d conversion resolution. writing 0 to this bit selects a resolution of 10 bits, and writing 1 to this bit selects a resolution of 8 bits. the data bit to be used depends on the resolution. bit14 bit13 st1, st0: sampling time setting bit these bits select the sampling time for a/d conversion. when a/d conversion is activated, analog input is fetched during the time set in this bit. setting these bits to 00 b (for 8 mhz) during 16-mhz operation may not be obtain normal fetching of the analog voltage. bit12 bit11 ct1, ct0: compari- son time setting bit these bits select the comparison time for a/d conversion. after analog input is fetched (i.e., sampling time elapses), conver- sion result data is defined and stored in bits 9 to 0 of this register after the time set in these bits. setting these bits to 00 b (for 8 mhz) during 16-mhz operation may not be obtain normal acquisition of the analog conversion value. bit10 free bit bit9 ~ bit0 ane2, ane1, ane0: a/d conversion end channel selection bit the a/d conversion results are stored and the register is rewritten each time conversion ends. usually, the last conversion value is stored. the initial value of this register is undefined. the conversion data protection function is provided. (see section 16.6, "operation of the 8/10-bit a/d converter.") do not write data to these bits during a/d conversion.
446 chapter 16 8/10-bit a/d converter MB90560 series 16.5 8/10-bit a/d converter interrupts the 8/10-bit a/d converter can generate an interrupt request when the data for the a/d conversion is stored in the a/d data register. this function supports the extended intelligent i/o service (ei2os). n 8/10-bit a/d converter interrupts table 16.5-1 indicates the interrupt control bits of the 8/10-bit a/d converter and the interrupt cause. table 16.5-1 interrupt control bits of the 8/10-bit a/d converter and the interrupt cause when a/d conversion is performed and its result is stored in the a/d data register (adcr), the int bit of the a/d control status register (adcs1) is set to 1. if the interrupt request is enabled (adcs1: inte = 1), an interrupt request is output to the interrupt controller. n 8/10-bit a/d converter interrupts and ei2os table 16.5-2 8/10-bit a/d converter interrupts and ei2os o: available n ei2os function of the 8/10-bit a/d converter using the ei2os function, the 10-bit a/d converter can transfer the a/d conversion result to memory. when the transfer is performed, a conversion data protection function halts the a/d conversion until the a/d conversion data is transferred to memory, and clears the int bit. the function prevents any part of the data from being lost. 8/10-bit a/d converter interrupt request flag bit adcs: int interrupt request enable bit adcs: inte interrupt cause writing the a/d conversion result to the a/d data register interrupt no. interrupt control register vector table address ei2os register name address lower upper bank #11 (0b h ) icr00 0000b0 h ffffd0 h ffffd1 h ffffd2 h o
MB90560 series chapter 16 8/10-bit a/d converter 447 16.6 operation of the 8/10-bit a/d converter the 8/10-bit a/d converter has three conversion modes: single conversion mode, continuous conversion mode, and stop conversion mode. this section describes operation in each mode. n operation in single conversion mode in single conversion mode, the analog inputs from the channel specified by the ans bits to the channel specified by the ane bits are sequentially converted. when the channels up to the end channel specified by the ane bits have been converted, a/d conversion stops. if the start and end channels are the same (ans = ane), just the channel specified by the ans bits is converted. figure 16.6-1 shows the settings required for operation in single conversion mode. figure 16.6-1 settings for single conversion mode the following are sample conversion sequences in single conversion mode: ans = 000 b , ane = 011 b :an0 ? an1 ? an2 ? an3 ? end ans = 110 b , ane = 010 b :an6 ? an7 ? an0 ? an1 ? an2 ? end ans = 011 b , ane = 011 b :an3 ? end adcs busy int inte paus sts1 sts0 resv strt md1 md0 ans2 ans1 ans0 ane2 ane0 ane1 bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 s10 st1 st0 ct1 ct0 - adcr holds the conversion data. : used : set to 1 the bit corresponding to the pin used. 0 : set 0. ader
448 chapter 16 8/10-bit a/d converter MB90560 series n operation in continuous conversion mode in continuous conversion mode, the analog inputs from the channel specified by the ans bits to the channel specified by the ane bits are sequentially converted. when the end channel specified by the ane bits has been processed, a/d conversion starts again from the channel specified by the ans bits. if the start and end channels are the same (ans = ane), the conversion of the channel specified by the ans bits is repeated. figure 16.6-2 shows the settings required for operation in continuous conversion mode. figure 16.6-2 settings for continuous conversion mode the following are sample conversion sequences in continuous conversion mode: ans = 000 b , ane = 011 b :an0 ? an1 ? an2 ? an3 ? an0 ? repeat ans = 110 b , ane = 010 b :an6 ? an7 ? an0 ? an1 ? an2 ? an6 ? repeat ans = 011 b , ane = 011 b :an3 ? an3 ? repeat adcs busy int inte paus sts1 sts0 strt resv md1 md0 ans2 ans1 ans0 ane2 ane0 ane1 - s10 st1 st0 ct1 ct0 adcr ader bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 holds the conversion data. : used : set to 1 the bit corresponding to the pin used. 1 : set 1. 0 : set 0.
MB90560 series chapter 16 8/10-bit a/d converter 449 n operation in stop conversion mode in stop conversion mode, the analog inputs from the channel specified by the ans bits to the channel specified by the ane bits are sequentially converted with a pause after the conversion of each channel. when the end channel specified by the ane bits has been processed, a/d conversion, with pauses, starts again with the channel specified by the ans bits. if the start and end channels are the same (ans = ane), the conversion of the channel specified by the ans bits is repeated. to reactivate conversion during a pause, generate the activation cause specified by the sts1 and sts0 bits. figure 16.6-3 shows the settings required for operation in stop conversion mode. figure 16.6-3 settings for stop conversion mode the following are sample conversion sequences in stop conversion mode: ans = 000b b , ane = 011 b : an0 ? pause ? an1 ? pause ? an2 ? pause ? an0 ? repeat ans = 110 b , ane = 001 b : an6 ? pause ? an7 ? pause ? an0 ? pause ? an1 ? an6 ? repeat ans = 011 b , ane = 011 b : an3 ? pause ? an3 ? pause ? repeat adcs busy int inte paus sts1 sts0 strt md1 md0 ans2 ans1 ans0 ane2 ane0 ane1 s10 st1 st0 ct1 ct0 - adcr ader bit15 bit14 bit13 bit12 bit11 bit10 bit9 bit8 bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0 holds the conversion data. : used : set to 1 the bit corresponding to the pin used. 1 : set 1. 0 : set 0. resv
450 chapter 16 8/10-bit a/d converter MB90560 series 16.6 operation of the 8/10-bit a/d converter 16.6.1 conversion using ei2os the 8/10-bit a/d converter can use ei2os transfer the a/d conversion result to memory. n conversion using ei2os figure 16.6-4 shows the operation flow when ei2os is used. figure 16.6-4 sample operation flowchart when ei2os is used when ei2os is used, the conversion data protection function prevents any part of the data from being lost even in continuous conversion. multiple data items can be safely transferred to memory. start a/d conversion sample and hold conversion end conversion generate an interrupt transfer data ei 2 os started interrupt cleared no yes *1 the number of times is determined by an ei 2 os setting. interrupt processing has the data transfer been repeated for the specified number of times? (*1)
MB90560 series chapter 16 8/10-bit a/d converter 451 memo
452 chapter 16 8/10-bit a/d converter MB90560 series 16.6 operation of the 8/10-bit a/d converter 16.6.2 a/d conversion data protection function when a/d conversion is performed in the interrupt enabled state, the conversion data protection function operates. n a/d conversion data protection function the a/d converter has just one data register that holds conversion data. when a single a/d conversion is completed, the data in the data register is rewritten. if the conversion data were not transferred to memory before the next conversion data was stored, part of the conversion data would be lost. the data protection function operates in the interrupt enabled state (inte = 1), as described below, to prevent loss of data. l data protection function when ei2os is not used when conversion data is stored in the a/d data register (adcr), the int bit of the a/d control status register 1 (adcs1) is set to 1. while the int bit is 1, a/d conversion is halted. halt status is released when the int bit is cleared after data in the a/d data register (adcr) has been transferred to memory by the interrupt routine. l data protection function when ei2os is used in continuous conversion using ei2os, the paus bit of the a/d control status register1 (adcs1) is kept at 1 when a conversion ends. this status continues until ei2os finishes transferring the conversion data from the data register to memory. in the meantime, the a/d conversion is halted, and the next conversion data is not stored. when the data transfer to memory is completed, the paus bit is cleared to 0, conversion and conversion resumes. figure 16.6-5 shows the operation flow of the data protection function when ei2os is used.
MB90560 series chapter 16 8/10-bit a/d converter 453 figure 16.6-5 operation flowchart of the data protection function when ei2os is used ? the conversion data protection function operates only in the interrupt enabled state (adcs1: inte = 1). ? if interrupts are disabled during a pause in a/d conversion while ei2os is operating, a/d conversion may start again. this will cause new data to be written before the old data is transferred. reactivation attempted during a pause will cause the old data to be destroyed. ? reactivation attempted during a pause will destroy the standby data. set ei 2 os start continuous a/d conversion end first conversion store data in the data register end second conversion has ei 2 os ended? store data in the data register third conversion terminate all conversions store data in the data register activate ei 2 os halt a/d activate ei 2 os activate ei 2 os initialize or stop a/d end no interrupt processing routine yes the steps while the a/d converter is halted are omitted. continue continue
454 chapter 16 8/10-bit a/d converter MB90560 series 16.7 usage notes on the 8/10-bit a/d converter notes on using the 8/10-bit a/d converter. n usage notes on the 8/10-bit a/d converter l analog input pin the a/d input pins are also used as the i/o pins of port 5. the port 5 data register (ddr5) and analog input enable register (ader) determine which pin is used for which purpose. to use a pin as analog input, write 0 to the corresponding bit of ddr5 and change the port setting to input. then, set the analog input mode (adex = 1) in the ader register and determine the input gate of the port. if an intermediate-level signal is input in the port input mode (adex = 0), a leakage current flows through the gate. l note on using an internal timer to start the a/d converter with an internal timer, set the sts1 and sts0 bits of a/d control status register 1 (adcs1) accordingly. set the input value of the internal timer at the inactive level (l for the internal timer). otherwise, operation may start concurrently with writing to the adcs register. l sequence of turning on the a/d converter and analog input do not turn on power to the a/d converter (avcc, avr+, avr-) and to the analog inputs (an0 to an7) before the digital power supply (vcc) has been turned on. do not turn off the digital power supply (vcc) before power to the a/d converter and the analog inputs has been turned off. l supply voltage to the a/d converter the supply voltage to the a/d converter (avcc) must not exceed the digital power supply (vcc); otherwise, latchup may occur.
MB90560 series chapter 16 8/10-bit a/d converter 455 memo
456 chapter 16 8/10-bit a/d converter MB90560 series 16.8 sample program 1 for single conversion mode using ei2os this section contains a sample program for a/d conversion in single conversion mode using ei2os. n sample program for single conversion mode using ei2os l processing ? analog inputs an1 to an3 are converted once. ? the conversion data is sequentially transferred to addresses 200 h to 205 h . ? a resolution of 10 bits is selected. ? the conversion is activated by software. figure 16.8-1 shows a flowchart of the program using ei2os (single conversion mode). figure 16.8-1 flowchart of program using ei2os (single conversion mode) l coding example bapl equ 000100h ; lower buffer address pointer bapm equ 000101h ; intermediate buffer address pointer baph equ 000102h ; upper buffer address pointer iscs equ 000103h ; ei2os status register ioal equ 000104h ; lower i/o address register ioah equ 000105h ; upper i/o address register dctl equ 000106h ; lower data counter dcth equ 000107h ; upper data counter ddr5 equ 000015h ; port 5 direction register ader equ 000017h ; analog input enable register icr00 equ 0000b0h ; interrupt control register for a/dc adcs0 equ 000034h ; a/d control status register adcs1 equ 000035h ; adcr0 equ 000036h ; a/d data register adcr1 equ 000037h ; an1 interrupt transfer by ei 2 os interrupt transfer by ei 2 os interrupt interrupt sequence transfer by ei 2 os an1 an1 end parallel processing start conversion
MB90560 series chapter 16 8/10-bit a/d converter 457 ;-------main program----------------------------------------------------------------------------------------------------------- ---- code cseg start: ; assumes that the stack pointer (sp) has already been initialized. and ccr,#0bfh ; disables interrupts. mov icr00,#00h ; interrupt level: 0 (highest priority) mov bapl,#00h ; sets the address to which the conversion data is transferred and stored. mov bapm,#02h ; (uses 200h to 205h.) mov baph,#00h ; mov iscs,#18h ; transfers word data, adds 1 to the address, then transfers the data from i/o to memory. mov ioal,#36h ; sets the address of the analog data register as the mov ioah,#00h ; transfer source address pointer. mov dctl,#03h ; sets the ei2os transfer count to three, which is the same value as the conversion count. mov ddr5,#11110001b ; sets p51 to p53 as input. mov ader,#00001110b ; sets p51/an1 to p53/an3 as analog inputs. mov cth,#00h ; mov adcs0,#0bh ; single activation. converts an1 to an3. mov adcs1,#0a2h ; software activation. begins a/d conversion. enables interrupts. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h bra loop ;-------interrupt program------------------------------------------------------------------------------------------------------ ---- ed_int1: mov i:adcs1,#00h ; stops a/d conversion. clears and disables the interrupt flag. reti ; returns from interrupt. code ends ;-------vector setting--------------------------------------------------------------------------------------------------------- ------ vect cseg abs=0ffh org 0ffd0h ; sets vector for interrupt #31 (1fh) dsl ed_int1 org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
458 chapter 16 8/10-bit a/d converter MB90560 series 16.9 sample program 2 for continuous conversion mode using ei2os this section contains a sample program for a/d conversion in continuous conversion mode using ei2os. n sample program for continuous conversion mode using ei2os l processing ? analog inputs an3 to an5 are converted twice. two conversion data items are obtained for each channel. ? the conversion data is sequentially transferred to addresses 600 h to 60b h . ? a resolution of 10 bits is selected. ? the conversion is activated by 16-bit reload timer 1. figure 16.9-1 shows a flowchart of the program using ei2os (continuous conversion mode). figure 16.9-1 flowchart of program using ei2os (continuous conversion mode) l coding example bapl equ 000100h ; lower buffer address pointer bapm equ 000101h ; middle buffer address pointer baph equ 000102h ; upper buffer address pointer iscs equ 000103h ; ei2os status register ioal equ 000104h ; lower i/o address register ioah equ 000105h ; upper i/o address register dctl equ 000106h ; lower data counter dcth equ 000107h ; upper data counter ddr5 equ 000015h ; port 5 direction register ader equ 000017h ; analog input enable register icr00 equ 0000b0h ; interrupt control register for a/dc adcs0 equ 000034h ; a/d control status register adcs1 equ 000035h ; adcr0 equ 000036h ; a/d data register adcr1 equ 000037h ; tmcrl1 equ 000086h ;lower control status register 1 an3 interrupt transfer by ei 2 os interrupt transfer by ei 2 os interrupt after a total of six transfers interrupt sequence end transfer by ei 2 os an4 an5 start conversion
MB90560 series chapter 16 8/10-bit a/d converter 459 tmcrh1 equ 000087h ; rldrl1 equ 000088h ;16-bit reload register rldrh1 equ 000089h ; ;-------main program------------------------------------------------------------------------------------------------ --------- code cseg start: ; assumes that the stack pointer (sp) has already been initialized. and ccr,#0bfh ; disables interrupts. mov icr10,#08h ; interrupt level; 0 (highest priority). enables interrupts. mov bapl,#00h ; sets the address to which conversion data is stored. mov bapm,#06h ; (uses 600h to 60bh.) mov baph,#00h ; mov iscs,#18h ; transfers word data, adds 1 to the address, then ; transfers from i/o to memory. mov ioal,#36h ; sets the address of the analog data register as the mov ioah,#00h ; transfer source address pointer. mov dctl,#06h ; six transfers by ei2os (two transfers each for three channels) mov ddr5,#00000000b ; sets p50 to p57 as input. mov ader,#00111000b ; sets p53/an3 to p55/an5 as analog input. mov dcth,#00h ; mov adcs0,#9dh ; continuous conversion mode. converts an3 to an5 ch. mov adcs1,#0a8h ; activates the 16-bit timer, starts a/d conversion, and enables interrupts. movw tmrlr1,#0320h ; sets the timer value to 800 (320h), 100 s. mov tmcrh1,#00h ; sets the clock source to 125 ns and disables external trigger. mov tmcrl1,#12h ; disables timer output, disables interrupts, and enables reload. mov tmcrl1,#13h ; activates the 16-bit timer. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h bra loop ;-------interrupt program------------------------------------------------------------------------------------------------------ ---- ed_int1: mov i:adcs1,#80h ; does not stop a/d conversion. clears and disables the interrupt flag. reti ; returns from interrupt. code ends ;-------vector setting--------------------------------------------------------------------------------------------------------- -------
460 chapter 16 8/10-bit a/d converter MB90560 series vect cseg abs=0ffh org 0ffd0h ; sets vector for interrupt #11 (0bh). dsl ed_int1 org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
MB90560 series chapter 16 8/10-bit a/d converter 461 16.10 sample program 3 for stop conversion mode using ei2os this section contains a sample program for a/d conversion in stop conversion mode using ei2os. n sample program for stop conversion mode using ei2os l processing ? analog input an3 is converted 12 times at regular intervals. ? the conversion data is sequentially transferred to addresses 600 h to 617 h . ? a resolution of 10 bits is selected. ? the conversion is activated by 16-bit reload timer. figure 16.10-1 shows a flowchart of the program using ei2os (stop conversion mode). figure 16.10-1 flowchart of program using ei2os (stop conversion mode) l coding example bapl equ 000100h ; lower buffer address pointer bapm equ 000101h ; middle buffer address pointer baph equ 000102h ; upper buffer address pointer iscs equ 000103h ; ei2os status register ioal equ 000104h ; lower i/o address register ioah equ 000105h ; upper i/o address register dctl equ 000106h ; lower data counter dcth equ 000107h ; upper data counter ddr5 equ 000015h ; port 5 direction register ader equ 000017h ; analog input enable register icr00 equ 0000b0h ; interrupt control register for a/dc adcs0 equ 000034h ; a/d control status register adcs1 equ 000035h ; adcr0 equ 000036h ; a/d data register adcr1 equ 000037h ; tmcrl1 equ 000086h ;lower control status register 1 tmcrh1 equ 000087h ; rldrl1 equ 000088h ;16-bit reload register rldrh1 equ 000089h ; ;-------main program------------------------------------------------------------------------------------------------ an3 interrupt transfer by ei 2 os after 12 transfers interrupt sequence end stop activation by 16-bit reload timer 1 start conversion
462 chapter 16 8/10-bit a/d converter MB90560 series --------- code cseg start: ; assumes that the stack pointer (sp) has already been initialized. and ccr,#0bfh ; disables interrupts. mov icr00,#08h ; interrupt level: 0 (highest priority). mov bapl,#00h ; sets the address to which conversion data is stored. mov bapm,#06h ; (uses 600h to 617h.) mov baph,#00h ; mov iscs,#19h ; transfers word data, adds 1 to the address, ; transfers from i/o to memory, then ends by a ; resource request. mov ioal,#36h ; sets the address of the analog data register as the mov ioah,#00h ; transfer source address pointer. mov dctl,#0ch ; transfers only channel 3 twelve times by ei2os mov ddr5,#00000000b ; sets p50 to p57 as input. mov ader,#00001000b ; sets p53/an3 as analog input. mov adcs0,#0dbh ; stop conversion mode. converts an3 ch. mov adcs1,#0a8h ; activates the 16-bit timer, starts a/d conversion, and enables interrupts. movw tmrlr1,#0320h ; sets the timer value to 800 (320h), 100 s. mov tmcrh1,#00h ; sets the clock source to 125 ns and disables external trigger. mov tmcrl1,#12h ; disables timer output, disables interrupts, and enables reload. mov tmcrl1,#13h ; activates the 16-bit timer. mov ilm,#07h ; sets ilm in ps to level 7. or ccr,#40h ; enables interrupts. loop: mov a,#00h ; endless loop mov a,#01h bra loop ;-------interrupt program------------------------------------------------------------------------------------------------------ ---- ed_int1: mov i:adcs1,#80h ; does not stop a/d conversion. clears and disables the interrupt flag. reti ; returns from interrupt. code ends ;-------vector setting--------------------------------------------------------------------------------------------------------- ------- vect cseg abs=0ffh org 0ffd0h ; sets vector for interrupt #11 (0bh). dsl ed_int1 org 0ffdch ; sets reset vector. dsl start db 00h ; sets single-chip mode. vect ends end start
MB90560 series chapter 16 8/10-bit a/d converter 463 memo

chapter 17 address match detection function this chapter explains the address match detection function and operation of the mb90506 series. 17.1 overview of the address match detection function..................... 466 17.2 example of using the address match detection function............ 469
466 chapter 17 address match detection function MB90560 series 17.1 overview of the address match detection function an instruction code to be read by the cpu is replaced forcibly with an int9 instruction code (01 h ) when the corresponding address is equal to the value set in an address detection register. therefore, the cpu executes the int9 instruction when executing the set instruction. a program patch application function can be implemented by processing with the int #9 interrupt routine.there are two address detection registers, of which each is provided with an interrupt enable bit and interrupt flag. when the address is equal to the value set in the address detection register, and the interrupt enable bit is 1, assume the following: the interrupt flag is set to 1, and the instruction code to be read by the cpu is replaced forcibly with the int9 instruction code. the interrupt flag is cleared to 0 by writing 0 to it using an instruction. n registers n block diagram figure 17.1-1 block diagram bit no. 0 0 0 0 0 0 0 0 b r/w 76543210 r/w r/w r/w - - - - initial value byte byte byte initial value r/w undefined r/w undefined padr0 address :1fe2 h / 1fe1 h / 1fe0 h padr1 address :1fe5 h / 1fe4 h / 1fe3 h :00009e h pacsr address access ad1f ad1f ad1d ad0d reserved reserved reserved reserved reset set f 2 mc-16lx cpu core address latch enable bit detection bit address detection f 2 mc-16lx bus compare
MB90560 series chapter 17 address match detection function 467 n register details l program address detect register 0/1: padr0/padr1: the value written to each register is compared with a target address. if the value matches the address, and the corresponding interrupt enable bit of the pacsr register is 1, the corresponding interrupt bit is set to 1 to request the cpu to generate an int9 instruction. if the corresponding interrupt enable bit is 0, no operation is performed. the following lists the correspondence between the program address detection register and pacsr: l program address detect control or status register: pacsr this register controls the operation of the address detection function and indicates its status. [bit 7 to bit 4]: reserved bits reserved bits. be sure to write 0 to these bits. [bit 3]: address detect register 1 enable (ad1e) adr1 operation enable bit. when this bit is 1, the value set in the padr1 register is compared with the address. if the two values are equal, an int9 instruction is generated and the ad1d bit is set to 1. [bit 2]: address detect register1's is detected (ad1d) adr1 address match detection bit. this bit is set to 1 to indicate that the value set in the padr1 register matches the address. it is cleared to 0 by writing 0 to it. it is left unchanged by writing 1 to it. [bit 1]: address detect register 0 enable (ad0e) adr0 operation enable bit. when this bit is 1, the value set in the padr0 register is compared to the address. if they match, an int9 instruction is generated, and the ad0d bit is set to 1. address detection register interrupt enable bit interrupt bit padr0 ad0e ad0d padr1 ad1e ad1d padr0 address :1ff2 h /1ff1 h /1ff0 h padr1 address :1ff5 h /1ff4 h /1ff3 h b y te byte byte access initial value r/w indefinite r/w indefinite 0 0 0 0 0 0 0 r/w pacsr address:00009e h 76543210 r/w r/w r/w - - - - initial value reserved reserved reserved reserved ad1e ad1d ad0e ad0d bit no.
468 chapter 17 address match detection function MB90560 series [bit0]: address detect register0's is detected (ad0d) adr0 address match detection bit. this bit is set to 1 to indicate that the value set in the padr0 register is equal to the address. it is cleared to 0 by writing 0 to it. it is left unchanged by writing 1 to it. n operation of the address match detection function an instruction code to be read by the cpu is replaced forcibly with an int9 instruction code (01 h ) when the corresponding address is equal to the value set in an address detection register. therefore, the cpu executes the int9 instruction when executing the set instruction. a program patch application function can be implemented by processing with the int #9 interrupt routine. there are two address detection registers, of which each is provided with an interrupt enable bit and interrupt flag. when the address is equal to the value set in the address detection register, and the interrupt enable bit is 1, assume the following: the interrupt flag is set to 1, and the instruction code to be read by the cpu is replaced forcibly with the int9 instruction code. the interrupt flag is cleared to 0 by writing 0 to it using an instruction. n notes on the address match detection function the address match detection function fails if an address later than the first byte of the instruction is set in the address detection register. the value in the set address is replaced with 01 h so a wrong instruction is executed or an invalid address is accessed. before changing the value set in the address detection register, set the interrupt enable bit to 0. if data is written while the interrupt enable bit is 1, the address may be wrongly detected during writing, causing a malfunction.
MB90560 series chapter 17 address match detection function 469 17.2 example of using the address match detection function this section contains example of using the address match detection function. n system configuration figure 17.2-1 system configuration example n eeprom memory map n initial state the contents of eeprom are all 0s. n if a program error occurs the original of a patch program and its address are transferred to the mcu via the connector (uart). the mcu writes the information to eeprom. address meaning 0000h number of bytes of patch program no. 0 (0 for no program error) 0001h bit 7 to bit 0 of program address no. 0 0002h bit 15 to bit 8 of program address no. 0 0003h bit 24 to bit 26 of program address no. 0 0004h number of bytes of patch program no. 1 (0 for no program error) 0005h bit 7 to bit 0 of program address no. 1 0006h bit 15 to bit 8 of program address no. 1 0007h bit 24 to bit 16 of program address no. 1 0010h+ number of bytes of patch program no. 0 original of patch program no. 0 mcu f mc-16lx sin e 2 2 prom connector (uart) pull-up resistor
470 chapter 17 address match detection function MB90560 series n reset sequence after the reset sequence is completed, the mcu reads the value of eeprom. if the number of bytes of the patch program is not 0, the mcu reads the original patch program and writes it to ram. then, the mcu sets the program address to padr0 or adr1 and enables the program to run. the first address of the program written to ram is saved in ram as specified for each address detection register. n int9 interrupt during execution of an interrupt routine, control checks the interrupt flag for an address in which an interrupt was enabled, and branches to the corresponding program. the information stacked by the interrupt is deleted. the interrupt flag is also cleared. figure 17.2-2 system configuration example rom ram 000000h abnormal program register set for program patch modification program MB90560 interrupt-generated address -number of program bytes -interrupt-generated address 2 data transfer using uart external e prom - modification program ddress pc = generated address
MB90560 series chapter 17 address match detection function 471 figure 17.2-3 flowchart of program patch processing 2 read address 0001h 0003h (e 2 prom ) mov 2 read patch program 0010h 0090h ( e 2 prom ) mov enable patch processing executes the normal program clear interrupt program to patch program int9 int9 yes yes no no pc-pad0 execute patch program end patch program reset read 00b of e prom 000h( e prom)=0 patch program lower program address: 00 medium program address: 00 upper program address: 00 number of bytes of patch program: 80 stack area ram area patch program ram/register area i/o area e 2 prom abnormal program ffffh 0090h 0010h 0002h 0003h 0001h 0000h 000000h 000100h 000400h 000480h 000900h mb90562 ffffffh ff0000h ffc000h ffc050h ram rom

chapter 18 rom mirroring function selection module this chapter explains the function and operation of the MB90560 series rom mirroring function selection module. 18.1 overview of the rom mirroring function selection module......... 474
474 chapter 18 rom mirroring function selection module MB90560 series 18.1 overview of the rom mirroring function selection module the rom mirroring function selection module can access bank ff located in rom from bank 00 by setting the register. n registers n block diagram figure 18.1-1 block diagram n register details l romm (rom mirroring function selection register) do not access this register while the system is active in an address from 004000 h to 00ffff h . [bit 8]: mi when 1 has been written to this bit, the rom data in bank ff can be read from bank 00. when 0 has been written to this bit, the function is disabled in bank 00. this bit is a write- only bit. bit 15 14 13 12 11 10 9 8 initial value romm address -- -- - -- mi w ------- 1 b :00006f h address area rom f 2 mc-16lx bus rom mirroring function selection bank 00 bank ff bit 15 14 13 12 11 10 9 8 initial value romm address -- -- - -- mi w ------- 1 b :00006f h
MB90560 series chapter 18 rom mirroring function selection module 475 bank 00 accesses ff4000 h to ffffff h from 004000 h to 00ffff h . therefore, fff000 h to ff3fff h cannot be accessed even by selecting the rom mirroring function. figure 18.1-2 memory space rom area rom area rom area ram area ram area internal area i/o area i/o area ffffffh address 1 address 2 0000c0h 000000h when mi=1 when mi=0 000100h 010000h 004000h mb90561 mb90562 mb90f562 mb90v560 address 1 ff8000h ff0000h ff0000f ff0000h address 2 000500h 000900h 000900h 001100h

appendix the appendixes contain an i/o map and other information and describe instructions. appendix a i/o map ......................................................................... 479 appendix b instructions............................................................ 485 appendix c 512k-bit flash memory.......................................... 545 appendix d example of f2mc-16lx mb90f562 connection for serial writing................................................. 551
478
appendix a i/o map table a lists the addresses assigned to the registers for peripheral functions in the MB90560 series. n i/o map table a i/o map address abbreviation register access resource name initial value 000000 h pdr0 port 0 data register r/w port 0 xxxxxxxx b 000001 h pdr1 port 1 data register r/w port 1 xxxxxxxx b 000002 h pdr2 port 2 data register r/w port 2 xxxxxxxx b 000003 h pdr3 port 3 data register r/w port 3 xxxxxxxx b 000004 h pdr4 port 4 data register r/w port 4 *xxxxxxx b 000005 h pdr5 port 5 data register r/w port 5 xxxxxxxx b 000006 h pdr6 port 6 data register r/w port 6 ****xxxx b 000007 h ~0f h prohibited area 000010 h ddr0 port 0 direction register r/w port 0 00000000 b 000011 h ddr1 port 1 direction register r/w port 1 00000000 b 000012 h ddr2 port 2 direction register r/w port 2 00000000 b 000013 h ddr3 port 3 direction register r/w port 3 00000000 b 000014 h ddr4 port 4 direction register r/w port 4 *0000000 b 000015 h ddr5 analog input enable register r/w port 5 00000000 b 000016 h ddr6 port 6 direction register r/w port 6 ****0000 b 000017 h ader analog input enable register r/w port 5, a/d 11111111 b 000018 h ~1f h prohibited area 000020 h smr0 serial mode control register 0 r/w uart0 00000000 b 000021 h scr0 serial control register 0 r/w 00000100 b 000022 h sidr0/ sodr0 serial input data register 0/ serial output data register 0 r/w xxxxxxxx b 000023 h ssr0 serial status register 0 r/w 00001000 b 000024 h smr1 serial mode control register 1 r/w uart1 00000000 b 000025 h scr1 serial control register 1 r/w 00000100 b 000026 h sidr1 sodr1 serial input data register 1/ serial output data register 1 r/w xxxxxxxx b 000027 h ssr1 status register 1 r/w 00001000 b 000028 h prohibited area
480 appendix a i/o map MB90560 series table a i/o map (continued) address abbreviation register access resource name initial value 000029 h odcr0 communication prescaler control register 0 r/w communication prescaler (uart0) 0***0000 b 00002a h prohibited area 00002b h cdcr1 co0mmunication prescaler control register 1 r/w communication prescaler (uart1) 0***0000 b 00002c h ~2f h prohibited area 000030 h enir interrupt/dtp enable register r/w dtp/external interrupt 00000000 b 000031 h enrr interrupt/dtp cause register r/w 00000000 b 000032 h elvr request level setting register r/w 00000000 b 000033 h r/w 00000000 b 000034 h adcs0 a/d control status register r/w 00000000 b 000035 h adcs1 r/w 00000000 b 000036 h adcr0 a/d data register r xxxxxxxx b 000037 h adcr1 r or w 00101*xx b 000038 h prll0 ppg0 reload register r/w 8-/16-bit ppg timer (ch0, ch1) xxxxxxxx b 000039 h prlh0 r/w xxxxxxxx b 00003a h prll1 ppg1 reload register r/w xxxxxxxx b 00003b h prlh0 r/w xxxxxxxx b 00003c h ppgc0 ppg0 operation mode register r/w 00000001 b 00003d h ppgc1 ppg1 operation mode register r/w 00000001 b 00003e h pcs01 ppg0/ppg1 clock control register r/w 000000** b 00003f h prohibited area 000040 h prll2 ppg2 reload register r/w 8-/16-bit ppg timer (ch2, ch3) xxxxxxxx b 000041 h prlh2 r/w xxxxxxxx b 000042 h prll3 ppg3 reload register r/w xxxxxxxx b 000043 h prlh3 r/w xxxxxxxx b 000044 h ppgc2 ippg2 operation mode register r/w 00000001 b 000045 h ppgc3 ppg3 operation mode register r/w 00000001 b 000046 h pcs23 ppg2/ppg3 clock control register r/w 000000** b 000047 h prohibited area
MB90560 series appendix a i/o map 481 table a i/o map (continued) address abbreviation register access resource name initial value 000048 h prll4 ppg4 reload register r/w 8-/16-bit ppg timer (ch4, ch5) xxxxxxxx b 000049 h prlh4 r/w xxxxxxxx b 00004a h prll5 ppg5 reload register r/w xxxxxxxx b 00004b h prlh5 r/w xxxxxxxx b 00004c h ppgc4 ppg4 operation mode register r/w 00000001 b 00004d h ppgc5 ppg5 operation mode register r/w 00000001 b 00004e h pcs45 ppg4/ppg5 clock control register r/w 000000** b 00004f h prohibited area 000050 h tmrr0 8-bit reload register ch0 r/w waveform generator xxxxxxxx b 000051 h dtcr0 8-bit timer control register ch0 r/w 00000000 b 000052 h tmrr1 8-bit reload register ch1 r/w xxxxxxxx b 000053 h dtcr1 8-bit timer control register ch1 r/w 00000000 b 000054 h tmrr2 8-bit reload register ch2 r/w xxxxxxxx b 000055 h dtcr2 8-bit timer control register ch2 r/w 00000000 b 000056 h sigcr waveform control register r/w 00000000 b 000057 h prohibited area 000058 h cpclr compare clear register (lower) r/w 16-bit free- running timer xxxxxxxx b 000059 h compare clear register (upper) r/w xxxxxxxx b 00005a h tcdt timer data register (lower) r/w 00000000 b 00005b h timer data register (upper) r/w 00000000 b 00005c h tccs timer control status register (lower) r/w 0**00000 b 00005d h timer control status register (upper) r/w 00000000 b 00005e h prohibited area 00005f h 000060 h ipcp0 input capture data register ch0 r 16-bit input capture (ch00 to ch3) xxxxxxxx b 000061 h input capture data register ch0 r xxxxxxxx b 000062 h ipcp1 input capture data register ch1 r xxxxxxxx b 000063 h input capture data register ch1 r xxxxxxxx b 000064 h ipcp2 input capture data register ch2 r xxxxxxxx b 000065 h input capture data register ch2 r xxxxxxxx b 000066 h ipcp3 input capture data register ch3 r xxxxxxxx b 000067 h input capture data register ch4 r xxxxxxxx b 000068 h ics01 input capture control register 01 r/w 00000000 b 000069 h ics23 input capture control register 23 r/w 00000000 b
482 appendix a i/o map MB90560 series table a i/o map (continued) address abbreviation register access resource name initial value 00006a h ~6e h prohibited area 00006f h romm rom mirroring function selection register r/w rom mirroring function *******1 b 000070 h occp0 compare register ch0 (lower) r/w output compare ch0 to ch5 xxxxxxxx b 000071 h compare register ch0 (upper) r/w xxxxxxxx b 000072 h occp1 compare register ch1 (lower) r/w xxxxxxxx b 000073 h compare register ch1 (upper) r/w xxxxxxxx b 000074 h occp2 compare register ch2 (lower) r/w xxxxxxxx b 000075 h compare register ch2 (upper) r/w xxxxxxxx b 000076 h occp3 compare register ch3 (lower) r/w xxxxxxxx b 000077 h compare register ch3 (upper) r/w xxxxxxxx b 000078 h occp4 compare register ch4 (lower) r/w xxxxxxxx b 000079 h compare register ch4 (upper) r/w xxxxxxxx b 00007a h occp5 compare register ch5 (lower) r/w xxxxxxxx b 00007b h compare register ch5 (upper) r/w xxxxxxxx b 00007c h ocs0 compare control register ch0 r/w 0000**00 b 00007d h ocs1 compare control register ch1 r/w ***00000 b 00007e h ocs2 compare control register ch2 r/w 0000**00 b 00007f h ocs3 compare control register ch3 r/w ***00000 b 000080 h ocs4 compare control register ch4 r/w 0000**00 b 000081 h ocs5 compare control register ch5 r/w ***00000 b 000082 h tmcr0:l timer control status register ch0 (lower) r/w 16-bit reload timer ch0 00000000 b 000083 h tmcr0:h timer control status register ch0 (upper) r/w ****0000 b 000084 h tmr0:l/ tmrlr0:l 16-bit timer register ch0 (lower)/ 16-bit reload register ch0 (lower) r/w xxxxxxxx b 000085 h tmr0:h tmrlr0:h 16-bit timer register ch0 (upper)/ 16-bit reload register ch0 (upper) r/w xxxxxxxx b 000086 h tmcr1:l timer control status register ch1 (lower) r/w 16-bit reload timer ch1 00000000 b 000087 h tmcr1:h timer control status register ch1 (upper) r/w ****0000 b 000088 h tmr1:l/ tmrlr1:l 16-bit timer register ch1 (lower)/ 16-bit reload register ch1 (lower) r/w xxxxxxxx b 000089 h tmr1:h tmrlr1:h 16-bit timer register ch1 (upper)/ 16-bit reload register ch1 (upper) r/w xxxxxxxx b 00008a h ~8b h prohibited area
MB90560 series appendix a i/o map 483 table a i/o map (continued) address abbreviation register access resource name initial value 00008c h rdr0 port 0 pull-up resistor setting register r/w port 0 00000000 b 00008d h rdr1 port 1 pull-up resistor setting register r/w port 1 00000000 b 00008e h ~ 9d h prohibited area 00009e h pacsr program address detect control or status register r/w address match detection 11000000 b 00009f h dirr delayed interrupt cause/clear register r/w delayed interrupt *******0 b 0000a0 h lpmcr low-power consumption mode register r/w low-power consumption control register 00011000 b 0000a1 h ckscr clock selection register r/w 11111100 b 0000a2 h ~ a7 h prohibited area 0000a8 h wdtc watchdog control register r/w watchdog timer *****111 b 0000a9 h tbtc timebase timer control register r/w timebase timer 1**00100 b 0000aa h ~ad prohibited area 0000ae h fmcs flash memory control status register r/w flash memory interface circuit 000x0xx0 b 0000af h prohibited area 0000b0 h icr00 interrupt control register 00 r/w interrupt controller 00000111 b 0000b1 h icr01 interrupt control register 01 r/w 00000111 b 0000b2 h icr02 interrupt control register 02 r/w 00000111 b 0000b3 h icr03 interrupt control register 03 r/w 00000111 b 0000b4 h icr04 interrupt control register 04 r/w 00000111 b 0000b5 h icr05 interrupt control register 05 r/w 00000111 b 0000b6 h icr06 interrupt control register 06 r/w 00000111 b 0000b7 h icr07 interrupt control register 07 r/w 00000111 b 0000b8 h icr08 interrupt control register 08 r/w 00000111 b 0000b9 h icr09 interrupt control register 09 r/w 00000111 b 0000ba h icr10 interrupt control register 10 r/w 00000111 b 0000bb h icr11 interrupt control register 11 r/w 00000111 b 0000bc h icr12 interrupt control register 12 r/w 00000111 b 0000bd h icr13 interrupt control register 13 r/w 00000111 b 0000be h icr14 interrupt control register 14 r/w 00000111 b 0000bf h icr15 interrupt control register 15 r/w 00000111 b 0000c0 h ~ ff h unused area
484 appendix a i/o map MB90560 series table a i/o map (continued) l meaning of abbreviations used for reading and writing r/w: read and write enabled r: read only w: write only l explanation of initial values 0: the bit is initialized to 0. 1: the bit is initialized to 1. x: the initial value of the bit is undefined. *: the bit is not used. its initial value is undefined. address abbreviation register access resource name initial value 000100 h ~ # h ram area # h ~ 001fef h reserved area 001ff0 h padr0 program address detection register 0 r/w address match detection xxxxxxxx b 001ff1 h program address detection register 1 r/w xxxxxxxx b 001ff2 h program address detection register 2 r/w xxxxxxxx b 001ff3 h padr1 program address detection register 3 r/w xxxxxxxx b 001ff4 h program address detection register 4 r/w xxxxxxxx b 001ff5 h program address detection register 5 r/w xxxxxxxx b 001ff6 h ~ 1fff h unused area
appendix b instructions this appendix describes the instructions used by the f 2 mc-16lx. b.1 instructions ..................................................................................... 486 b.2 addressing ..................................................................................... 488 b.3 direct addressing ........................................................................... 490 b.4 indirect addressing......................................................................... 496 b.5 number of execution cycles .......................................................... 503 b.6 effective-address field .................................................................... 506 b.7 reading the instruction list............................................................ 507 b.8 list of f2mc-16lx instructions ...................................................... 510 b.9 instruction maps ............................................................................. 523
486 appendix b instructions MB90560 series b.1 instructions the f2mc-16lx uses the 351 instructions listed below. addresses must be specified in the effective address field of an instruction or by an instruction code. n overview of instructions the f 2 mc-16l uses the 351 instructions listed below. ? transfer (byte): 41 instructions ? transfer (word, long-word): 38 instructions ? addition/subtraction (byte, word, long-word): 42 instructions ? increment/decrement (byte, word, long-word): 12 instructions ? comparison (byte, word, long-word): 11 instructions ? unsigned multiplication/division (word, long-word) 11 instructions ? signed multiplication/division (word, long-word) 11 instructions ? logical operation (byte, word): 39 instructions ? logical operation (long-word): 6 instructions ? sign inversion (byte, word): 6 instructions ? normalization (long-word): 1 instruction ? shift (byte, word, long-word,): 18 instructions ? branching: 50 instructions ? accumulator operation (byte, word): 6 instructions ? other types of control (byte, word, long-word): 28 instructions ? bit operation: 21 instructions ? string: 10 instructions
MB90560 series appendix b instructions 487 memo
488 appendix b instructions MB90560 series b.2 addressing the f 2 mc-16lx determines the address format according to the instruction's effective- address field or from the instruction code (the address format is implied). when the address format is determined from the instruction code, the address format that matches the instruction code is used. more than one type of address format can be specified for some instructions. n addressing the f 2 mc-16lx uses the following 23 types of addressing: ? immediate (#imm) ? register direct ? direct branch (addr16) ? physical direct branch (addr24) ? i/o direct (io) ? condensed direct (dir) ? direct (addr16) ? i/o direct bit (io:bp) ? condensed direct bit (dir:bp) ? direct bit (addr16:bp) ? vector (#vct) ? register indirect (@rwj j = 0 to 3) ? register indirect with post-incrementing ? (@rwj+ j = 0 to 3) ? register indirect with displacement (@rwi+disp8 i = 0 to 7, @rwj+disp16 j = 0 to 3) ? long-word register indirect with displacement (@rli+disp8 i = 0 to 3) ? program counter indirect with displacement (@pc+disp16) ? register indirect with base index (@rw0+rw7, @rw1+rw7) ? program counter relative branch (rel) ? register list (rlst) ? accumulator indirect (@a) ? accumulator indirect branch (@a) ? indirect designation branch (@ear) ? indirect designation branch (@eam)
MB90560 series appendix b instructions 489 n effective-address field table b.2-1 lists the address formats specified by the effective-address field. table b.2-1 effective-address field code notation address format default bank 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rll1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word formats in order from the left. none 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect dtb dtb adb spb 0c 0d 0e 0f @rw0+ @rw1+ @rw2+ @rw3+ register indirect with post-incrementing dtb dtb adb spb 10 11 12 13 @rw0+disp8 @rw1+disp8 @rw2+disp8 @rw3+disp8 register indirect with 8-bit displacement dtb dtb adb spb 14 15 16 17 @rw4+disp8 @rw5+disp8 @rw6+disp8 @rw7+disp8 register indirect with 8-bit displacement dtb dtb adb spb 18 19 1a 1b @rw0+disp16 @rw1+disp16 @rw2+disp16 @rw3+disp16 register indirect with 16-bit displace- ment dtb dtb adb spb 1c 1d 1e 1f wrw0+rw7 @rw1+rw7 @pc+disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address dtb dtb spb adb
490 appendix b instructions MB90560 series b.3 direct addressing in direct addressing, operand values, registers, and addresses are specified directly. n direct addressing l immediate addressing (#imm) operand values are specified directly (#imm4/#imm8/#imm16/#imm32). figure b.3-1 shows an example. figure b.3-1 example of immediate addressing (#imm) l register direct addressing operand values specify registers directly. the following registers can be specified: *1 the sp register functions as a user stack pointer (usp) or system stack pointer (ssp) depending on the s flag bit value indicated in the condition code register (ccr). for branching instructions, the program counter (pc) is not specified as an operand, but is implicitly specified. figure b.3-2 shows an example. general-purpose register byte r0, r1, r2, r3, r4, r5, r6, r7 word rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 long-word rl0, rl1, rl2, rl3 dedicated registers accumulator a, al pointer sp ( *1) bank pcb, dtb, usb, ssb, adb page dpr control ps, ccr, rp, ilm movw a, #01212h (instruction that stores the operand value in a) before execution after execution (some instructions transfer data from al to ah.)
MB90560 series appendix b instructions 491 figure b.3-2 example of register direct addressing l direct branch addressing (addr16) branch destination addresses are specified directly by displacement. the displacement is 16 bits and is used to specify a branch destination within the logical space. this method is used for unconditional branching instructions, subroutine call instructions, and software interrupt instructions. address bits 16 to 23 are specified by the program bank register (pcb). figure b.3-3 shows an example of direct branch addressing (addr16). figure b.3-3 example of direct branch addressing (addr16) l physical direct branch addressing (addr24) branch destination addresses are specified directly by displacement. the displacement is 24 bits. this method is used for unconditional branching instructions, subroutine call instructions, and software interrupt instructions. figure b.3-4 shows an example of physical direct branch addressing (addr24). mov r0, a (instruction that transfers lower 8 bits of a to general-purpose register r0) before execution after execution memory space memory space jmp 3b20h (unconditional branch instruction with direct branch address specified in the bank) before execution memory space after execution next instruction
492 appendix b instructions MB90560 series figure b.3-4 example of physical direct branch addressing (addr24) l i/o direct addressing (io) this method specifies memory addresses of the operand directly using an 8-bit displacement. regardless of the values of the data bank register (dtb) and direct page register (dpr), the i/o space at physical addresses 000000h to 0000ffh is accessed. prefix instructions designating banks specified before instructions using this addressing method are invalid. figure b.3-5 shows an example of i/o direct addressing (io). figure b.3-5 example of i/o direct addressing (io) l condensed direct addressing (dir) this method uses the operand to specify the lower eight bits of a memory address directly. address bits 8 to 15 are specified by the dpr register. address bits 16 to 23 are specified by the dtb register. figure b.3-6 shows an example of condensed direct addressing (dir). figure b.3-6 example of condensed direct addressing (dir) jmpp 333b20h (unconditional branch instruction with 24-bit direct branch address specified) before execution after execution next instruction memory space movw a, i:0c0h (instruction that reads data by i/o direct addressing and stores it in a) before execution after execution memory space after execution before execution memory space memory space mov s:20h, a (instruction that writes the lower eight bits of a by condensed direct addressing)
MB90560 series appendix b instructions 493 l direct addressing (addr16) operand values specify lower 16 bits of an memory address directly. address bits 16 to 23 are specified by the dtb register. prefixed instructions that specify the access space are invalid for this type of addressing. figure b.3-7 shows an example of direct addressing (addr16). figure b.3-7 example of direct addressing (addr16) l i/o direct bit addressing (io:bp) this method directly specifies bits within the physical address range from 000000h to 0000ffh. the bit location is expressed as :bp, with higher values representing a more significant bit (msb) and lower values representing a less significant bit (lsb). figure b.3-8 shows an example of i/o direct bit addressing (io:bp). figure b.3-8 example of i/o direct bit addressing (io:bp) l condensed direct bit addressing (dir:bp) this method uses the operand to specify the lower eight bits of the memory address. address bits 8 to 15 are specified by the dpr register and address bits 16 to 23 are specified by the dtb register. the bit location is expressed as :bp, with a higher value representing an msb and a lower value representing a, lsb. figure b.3-9 shows an example of condensed direct bit addressing (dir:bd). after execution before execution memory space memory space setb i:0c1h:0 (instruction that sets a bit using i/o direct bit addressing)
494 appendix b instructions MB90560 series figure b.3-9 example of condensed direct bit addressing (dir:bp) l direct bit addressing (addr16:bp) this method directly specifies any bit within the 64-kilobyte area. address bits 16 to 23 are specified by the dtb register. the bit location is expressed as :bp, with a higher value representing an msb and a lower value representing an lsb. figure b.3-10 shows an example of direct bit addressing (addr16:bp). figure b.3-10 example of direct bit addressing (addr16:bp) l vector addressing (#vct) in this method, the contents of the specified vector indicates the branch destination address. the data length of the vector number may be either four bits or eight bits. this method is used for subroutine call instructions and software interrupt instructions. figure b.3-11 shows an example of vector addressing (#vct). figure b.3-11 example of vector addressing (#vct) after execution before execution memory space memory space setb s:10h:0 (instruction that sets a bit using condensed direct bit addressing) after execution before execution memory space memory space setb 2222h:0 (instruction sets a bit using direct bit addressing) after execution before execution memory space callv #15 (instruction that branches to the address specified by the interrupt vector specified by the operand)
MB90560 series appendix b instructions 495 table b.3-1 callv vectors xx indicates a pcb register value. note that the vector area is shared with int #vct8 (#0 to #7) when the pcb register value is ffh (see table b.2). instruction vector address (low) vector address (high) callv #0 xxfffe h xxffff h callv #1 xxfffc h xxfffd h callv #2 xxfffa h xxfffb h callv #3 xxfff8 h xxfff9 h callv #4 xxfff6 h xxfff7 h callv #5 xxfff4 h xxfff5 h callv #6 xxfff2 h xxfff3 h callv #7 xxfff0 h xxfff1 h callv #8 xxffee h xxffef h callv #9 xxffec h xxffed h callv #10 xxffea h xxffeb h callv #11 xxffe8 h xxffe9 h callv #12 xxffe6 h xxffe7 h callv #13 xxffe4 h xxffe5 h callv #14 xxffe2 h xxffe3 h callv #15 xxffe0 h xxffe1 h
496 appendix b instructions MB90560 series b.4 indirect addressing in indirect addressing, the operand specifies indirectly the address of the data. n indirect addressing l register indirect addressing (@rwj j = 0 to 3) this type of addressing accesses memory at the address indicated by the contents of general- purpose register rwj. address bits 16 to 23 are specified by the dtb register if rw0 or rw1 is used, by the system stack bank register (ssb) or user stack bank register (usb) if rw3 is used, and by the additional data bank register (adb) if rw2 is used. figure b.4-1 shows an example of register indirect addressing (@rwj, j= 0 to 3). figure b.4-1 example of register indirect addressing (@rwj j = 0 to 3) l register indirect addressing with post-incrementing (@rwj+ j = 0 to 3) this type of addressing accesses memory at the address indicated by the contents of general- purpose register rwj. after the operand has been operated on, register rwj is incremented by the length of the operand data (one for byte length, two for word length, four for long-word length). address bits 16 to 23 are specified by the dtb register if rw0 or rw1 is used, by the ssb or usb register if rw3 is used, and by the adb register if rw2 is used. note that if the results of post-incrementing are the address of the same register that specified the increment, the value to be referenced after incrementing will be the incremented value. also, if a write instruction is used, the write operation will have priority, so that the register that is supposed to be incremented receives the write data. figure b.4-2 shows an example of register indirect addressing with post-incrementing (@rwj+, j = 0 to 3). figure b.4-2 example of register indirect addressing with post-incrementing (@rwj+ j = 0 to 3) after execution before execution movw a, @rw1 (instruction that reads data using register indirect addressing and stores it in a) memory space after execution before execution movw a, @rw1+ (instruction that reads data by register indirect addressing with post-incrementing and stores it in a) memory space
MB90560 series appendix b instructions 497 l register indirect addressing with displacement (@rwi+disp8 i = 0 to 7, @rwj+disp16 j = 0 to 3) this type of addressing accesses memory at an address derived from the contents of the general-purpose register rwj with a displacement added. displacements may be either byte or word length, and are added as signed numerical values. address bits 16 to 23 are specified by the dtb register if rw0, rw1, rw4, or rw5 is used, by the ssb or usb register if rw3 or rw7 is used, and by the adb register if rw2 or rw6 is used. figure b.4-3 shows an example of register indirect addressing with displacement (@rwi+disp8, i = 0 to 7; @rwj+disp16, j = 0 to 3). figure b.4-3 example of register indirect addressing with displacement (@rwi+disp8 i = 0 to 7, @rwj+disp16 j = 0 to 3) l long-register indirect addressing with displacement (@rli+disp8 i = 0 to 3) this type of addressing accesses memory at an address derived by using the lower 24 bits of the sum of the contents of general-purpose register rli plus a displacement. the displacement is 8 bits, and is added as a signed numerical value to the rli contents. figure b.4-4 shows an example of long-register indirect addressing with displacement (@rli+disp8, i = 0 to 3). figure b.4-4 example of long-word register indirect addressing with displacement(@rli+disp8 i = 0 to 3) after execution before execution movw a, @rw1+10h (instruction that reads data by register indirect addressing with displacement and stores it in a) memory space after execution before execution movw a, @rl2+25h (instruction that reads data by long-word register indirect addressing with displacement and stores it in a) memory space
498 appendix b instructions MB90560 series l program counter indirect addressing with displacement (@pc+disp16) this type of addressing accesses memory at an address determined by the formula (instruction address+4+disp16). the displacement is word-length data. address bits 16 to 23 are specified by the pcb register. note that the operand addresses of the following instructions are not considered to be (next instruction address+disp16): ? dbnz eam,rel ? dwbnz eam,rel ? cbne eam,#imm8,rel ? cwbne eam,#imm16,rel ? mov eam,#imm8 ? movw eam,#imm16 figure b.4-5 shows an example of program counter indirect addressing with displacement (@pc+disp16). figure b.4-5 example of program counter indirect addressing with displacement (@pc+disp16) after execution before execution memory space movw a, @pc+20h (instruction that reads data with pc indirect addressing with displacement and stores it in a)
MB90560 series appendix b instructions 499 l register indirect addressing with base index (@rw0+rw7, @rw1+rw7) this type of addressing accesses memory at an address determined by adding the contents of general-purpose register rw7 to rw0 or rw1. address bits 16 to 23 are specified by the dtb register. figure b.4-6 shows an example of register indirect addressing with a base index (@rw0+rw7, @rw1+rw7). figure b.4-6 example of register indirect addressing with base index (@rw0+rw7, @rw1+rw7) l program counter relative branch addressing (rel) a branch destination address is represented as the program counter (pc) value plus an 8-bit displacement. because the bank register is not incremented or decremented and overflow is ignored if the result is over 16 bits, the result is an address within the 64-kilobyte bank. this addressing method is used for unconditional and conditional branch instructions. address bits 16 to 23 are specified by the pcb register. figure b.4-7 shows an example of program counter relative branch addressing (rel). figure b.4-7 example of program counter relative branch addressing (rel) after execution before execution memory space movw a, @rw1+rw7 (instruction that reads data by register indirect addressing with base index and stores it in a) next instruction after execution before execution memory space bra 3b20h (unconditional relative branch instruction)
500 appendix b instructions MB90560 series l register list (rlst) this addressing method specifies registers that are used by push/pop instructions for stack operations. figure b.3h shows the register list configuration. figure b.4-8 shows the register list configuration. figure b.4-9 shows an example of the register list (list). figure b.4-8 register list configuration figure b.4-9 example of register list (rlst) l accumulator indirect addressing (@a) this addressing method accesses memory at the address indicated by the contents (16 bits) of the lower bytes of the accumulator (al). address bits 16 to 23 are specified by the dtb register as mnemonics. figure b.4-10 shows an example of accumulator indirect addressing (@a). figure b.4-10 example of accumulator indirect addressing (@a) selected when the corresponding bit is set to 1 and not selected when it is set to 0. after execution before execution memory space memory space popw rw0, rw4 (instruction that transfers data at the memory locations specified by the sp to the word registers in the register list) after execution before execution memory space movw a, @a (instruction that reads data by accumulator indirect addressing and stores it in a)
MB90560 series appendix b instructions 501 l accumulator indirect branch addressing (@a) the 16-bit contents of the lower bytes of the accumulator (al) indicate the branch destination address, which specifies a branch destination within the bank space. address bits 16 to 23 are specified by the pcb register. if the jump context (jctx) instruction is used, address bits 16 to 23 are specified by the dtb register. this addressing method is used for unconditional branching instructions. figure b.4-11 shows an example of accumulator indirect branch addressing (@a). figure b.4-11 example of accumulator indirect branch addressing (@a) l indirect designation branch addressing (@ear) in this type of addressing, the branch destination address is the word data at the address specified by the ear parameter. figure b.4-12 shows an example of indirect designation branch addressing (@ear). figure b.4-12 example of indirect designation branch addressing (@ear) after execution before execution next instruction memory space jmp @a (unconditional branch instruction that uses accumulator indirect branch addressing) after execution before execution jmp @rw0 (unconditional branch instruction that uses register indirect addressing)
502 appendix b instructions MB90560 series l indirect designation branch addressing (@eam) in this type of addressing, the branch destination address is the word data at the address specified by the eam parameter. figure b.4-13 shows an example of indirect designation branch addressing (@eam). figure b.4-13 example of indirect designation branch addressing (@eam) before execution after execution jmp @@rw0 (unconditional branch instruction that uses register indirect addressing)
MB90560 series appendix b instructions 503 b.5 number of execution cycles the number of cycles required to execute an instruction is obtained by adding the number of cycles for the instruction, the compensation value determined by conditions, and the number of cycles for program fetch. n number of execution cycles the number of cycles required to execute an instruction is obtained by adding the number of cycles for the instruction, the compensation value determined by conditions, and the number of cycles for program fetch. because a program in memory connected to the 16-bit bus to the built-in rom is fetched each time an executing instruction exceeds the word boundary, the number of execution cycles increases if data access is interfered with. because a program in memory connected to the 8-bit external data bus is fetched for each byte of the instruction being executed, the number of execution cycles increases if data access is interfered with. if general-purpose registers, built-in rom, built-in ram, built-in i/o, and external data buses are accessed during intermittent operation of the cpu, clocks supplied to the cpu stop for the number of cycles specified by the cg0 and cg1 bits of the low-power consumption mode control register. to calculate the number of cycles needed to execute an instruction during intermittent operation of the cpu, add as a compensation value to the normal number of execution cycles the product of the number of accesses and the number of cycles for the temporary stop. n calculation of the number of execution cycles tables b.5-1~ b.5-3 list the number of execution cycles for each instruction and compensation values. table b.5-1 number of execution cycles for each type of addressing code operand (a) (*1) number of register accesses for type of addressing number of execution cycles for type of addressing 00 | 07 ri rwi rli shown in instruction list. shown in instruction list. 08 | 0b @rwj 2 1 0c | 0f @rwj+ 4 2 10 | 17 @rwj+disp8 2 1
504 appendix b instructions MB90560 series table b.5-1 number of execution cycles for each type of addressing (continued) *1 (a) is used for ~ (number of cycles) and b (compensation value) in section b.7, "reading the instruction list." table b.5-2 compensation values for calculating the number of execution cycles *1 (b), (c), and (d) are used for ~ (number of cycles) and b (compensation value) in section b.7, "reading the instruction list." *2 when the external data bus is used, the number of cycles for waiting due to ready input and automatic ready should be added. code operand (a) (*1) number of register accesses for type of addressing number of execution cycles for type of addressing 18 | 1b @rwi+disp16 2 1 1c 1d 1e 1f @rw0+rw7 @rw1+rw7 @pc+disp16 addr16 4 4 2 1 2 2 0 0 operand (b) byte (*1) (c) word (*1) (d) long-word (*1) number of cycles number of accesses number of cycles number of accesses number of cycles number of accesses internal register +0 1 +0 1 +0 2 internal memory, even address +01+01+02 internal memory, odd address +01+22+44 external data bus 16-bit even address +11+11+22 external data bus 16-bit odd address +11+42+84 external data bus (*2) 8 bits +11+42+84
MB90560 series appendix b instructions 505 table b.5-3 compensation values for calculating number of cycles for program fetch 1. when the external data bus is used, the number of cycles for waiting due to ready input and automatic ready should be added. 2 not all program fetches delay instruction execution during actual operation. use the compensation values for calculating values for worst-case situations. instruction byte boundary word boundary internal memory - +2 external data bus 16 bits - +3 external data bus 8 bits +3 -
506 appendix b instructions MB90560 series b.6 effective-address field table b.6-1 lists the effective-address field for each code. n effective-address field table b.6-1 effective-address field *1 the number of bytes in the address expansion part is used for "+" in the # (number of bytes) column in section b.7, "reading the instruction list." code notation address format number of bytes in address expansion part (*1) 00 01 02 03 04 05 06 07 r0 r1 r2 r3 r4 r5 r6 r7 rw0 rw1 rw2 rw3 rw4 rw5 rw6 rw7 rl0 (rl0) rl1 (rll1) rl2 (rl2) rl3 (rl3) register direct ea corresponds to byte, word, and long-word formats in order from the left. - 08 09 0a 0b @rw0 @rw1 @rw2 @rw3 register indirect 0 0c 0d 0e 0f @rw0+ @rw1+ @rw2+ @rw3+ register indirect with post-increment- ing 0 10 11 12 13 14 15 16 17 @rw0+disp8 @rw1+disp8 @rw2+disp8 @rw3+disp8 @rw4+disp8 @rw5+disp8 @rw6+disp8 @rw7+disp8 register indirect with 8-bit displace- ment 1 18 19 1a 1b @rw0+disp16 @rw1+disp16 @rw2+disp16 @rw3+disp16 register indirect with 16-bit displace- ment 2 1c 1d 1e 1f @rw0+rw7 @rw1+rw7 @pc+disp16 addr16 register indirect with index register indirect with index pc indirect with 16-bit displacement direct address 0 0 2 2
MB90560 series appendix b instructions 507 b.7 reading the instruction list this section explains the items (table b.7-1) and codes (table b.7-2) that appear in section b.7, "list of f 2 mc-16l instructions." n explanation of items covered and instruction codes table b.7-1 items covered in instruction list item description mnemonic uppercase alphabetic characters, symbols: shown as they appear in assembler. lowercase alphabetic characters: placeholders for assembler. numerics following lowercase alphabetic characters: indicates the bit length of instruc- tions. # indicates the number of bytes. ~ indicates the number of cycles. for alphabetic characters in the items, see table b.3-1. rg indicates the number of register accesses during instruction execution. used for calculating compensation values during intermittent operation of the cpu. b indicates compensation values for calculating the actual number of cycles during instruc- tion execution. the actual number of cycles is the sum of the values in the ? column. operation describes how the instruction operates. lh indicates special operations with respect to accumulator bits 08 to 15. z: transfers zero. x: transfers using sign extension. -: no transfer ah indicates special operations with respect to the upper 16 bits of the accumulator. *: transfers from al to ah. -: no transfer z: transfers 00 to ah. x: using al sign extension, transfers 00h or ffh to ah. i indicates status of flags: i (interrupt enable), s (stack), t (sticky bit), n (negative), z (zero), v (overflow), c (carry). *: changed as a result of instruction execution. -: not changed. z: set by instruction execution. x: reset by instruction execution. s t n z v c
508 appendix b instructions MB90560 series table b.7-1 symbols used in the instruction list (continued) rmw indicates a read-modify-write instruction (one which reads data from memory and writes the result in memory with the i instruction). *: read-modify-write instruction -: not a read-modify-write instruction this type of instruction cannot be used with addresses with a different read/write meaning. symbol meaning a 2-bit accumulator length in bits varies with the instruction. byte: lower 8 bits of al word: 16 bits of al long-word: 32 bits of al and ah. ah al upper 16 bits of a lower 16 bits of a sp stack pointer (usp or ssp) pc program counter pcb program bank register dtb data bank register adb additional data bank register ssb system stack bank register usb user stack bank register spb current stack bank register (ssb or usb) dpr direct page register brg1 dtb, adb, ssb, usb, dpr, pcb, spb brg2 dtb, adb, ssb, usb, dpr, spb ri r0, r1, r2, r3, r4, r5, r6, r7 rwi rw0, rw1, rw2, rw3, rw4, rw5, rw6, rw7 rwj rw0, rw1, rw2, rw3 rli rl0, rl1, rl2, rl3 dir addr16 addr24 ad24 0-15 ad24 16-23 condensed direct addressing direct addressing physical direct addressing addr24 bits 0 to 15 addr24 bits 16 to 23 io i/o area (000000h to 0000ffh) item description
MB90560 series appendix b instructions 509 table b.7-1 symbols used in the instruction list (continued) #imm4 #imm8 #imm16 #imm32 ext (imm8) 8-bit immediate data 8-bit immediate data 16-bit immediate data 32-bit immediate data 48-bit immediate data extended to signed 16-bit data disp8 disp16 8-bit displacement 16-bit displacement bp bit offset value symbol meaning vct4 vct8 vector number (0 to 15) vector number (0 to 255) ( ) b bit address rel ear eam pc relative branch addressing effective address designation (codes 00 to 07) effective address designation (codes 08 to 1f) rist register list symbol meaning
510 appendix b instructions MB90560 series b.8 list of f 2 mc-16lx instructions tables b.8-1 to b.8-17 list instructions used by f 2 mc-16lx. table b.8-1 transfer instructions (byte): 41 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw mov a,dir mov a,addr16 mov a,ri mov a,ear mov a,eam mov a,io mov a,#imm8 mov a,@a mov a,@rli+disp8 movn a,#imm4 movx a,dir movx a,addr16 movx a,ri movx a,ear movx a,eam movx a,io movx a,#imm8 movx a,@a movx a,@rwi+disp8 movx a,@rli+disp8 mov dir,a mov addr16,a mov ri,a mov ear,a mov eam,a mov io,a mov @rli+disp8,a mov ri,ear mov ri,eam mov ear,ri mov eam,ri mov ri,#imm8 mov io,#imm8 mov dir,#imm8 mov ear,#imm8 mov eam,#imm8 mov @al,ah / mov @a,t xch a,ear xch a,eam xch ri,ear xch ri,eam 2 3 1 2 2+ 2 2 2 3 1 2 3 2 2 2+ 2 2 2 2 3 2 3 1 2 2+ 2 3 2 2+ 2 2+ 2 3 3 3 3+ 2 2 2+ 2 2+ 3 4 2 2 3+(a) 3 2 3 10 1 3 4 2 2 3+(a) 3 2 3 5 10 3 4 2 2 3+(a) 3 10 3 4+(a) 4 5+(a) 2 5 5 2 4+(a) 3 4 5+(a) 7 9+(a) 0 0 1 1 0 0 0 0 2 0 0 0 1 1 0 0 0 0 1 2 0 0 1 1 0 0 2 2 1 2 1 1 0 0 1 0 0 2 0 4 2 (b) (b) 0 0 (b) (b) 0 (b) (b) 0 (b) (b) 0 0 (b) (b) 0 (b) (b) (b) (b) (b) 0 0 (b) (b) (b) 0 (b) 0 (b) 0 (b) (b) 0 (b) (b) 0 2(b) 0 2(b) byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? (imm8) byte (a) ? ((a)) byte (a) ? ((rli)+disp8) byte (a) ? imm4 byte (a) ? (dir) byte (a) ? (addr16) byte (a) ? (ri) byte (a) ? (ear) byte (a) ? (eam) byte (a) ? (io) byte (a) ? (imm8) byte (a) ? ((a)) byte (a) ? ((rwi)+disp8) byte (a) ? ((rli)+disp8) byte (dir) ? (a) byte (addr16) ? (a) byte (ri) ? (a) byte (ear) ? (a) byte (eam) ? (a) byte (io) ? (a) byte ((rli)+disp8) ? (a) byte (ri) ? (ear) byte (ri) ? (eam) byte (ear) ? (ri) byte (eam) ? (ri) byte (ri) ? imm8 byte (io) ? imm8 byte (dir) ? imm8 byte (ear) ? imm8 byte (eam) ? imm8 byte ((a)) ? (ah) byte (a) ?? (ear) byte (a) ?? (eam) byte (ri) ?? (ear) byte (ri) ?? (eam) z z z z z z z z z z x x x x x x x x x x - - - - - - - - - - - - - - - - - z z - - * * * * * * * - * * * * * * * * * - * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * r * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MB90560 series appendix b instructions 511 table b.8-2 transfer instructions (word, long-word): 38 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movw a,dir movw a,addr16 movw a,sp movw a,rwi movw a,ear movw a,eam movw a,io movw a,@a movw a,#imm16 movw a,@rwi+disp8 movw a,@rli+disp8 movw dir,a movw addr16,a movw sp,a movw rwi,a movw ear,a movw eam,a movw io,a movw @rwi+disp8,a movw @rli+disp8,a movw rwi,ear movw rwi,eam movw ear,rwi movw eam,rwi movw rwi,#imm16 movw io,#imm16 movw ear,#imm16 movw eam,#imm16 movw @al,ah / movw @a,t xchw a,ear xchw a,eam xchw rwi,ear xchw rwi,eam 2 3 1 1 2 2+ 2 2 3 2 3 2 3 1 1 2 2+ 2 2 3 2 2+ 2 2+ 3 4 4 4+ 2 2 2+ 2 2+ 3 4 1 2 2 3+(a) 3 3 2 5 10 3 4 1 2 2 3+(a) 3 5 10 3 4+(a) 4 5+(a) 2 5 2 4+(a) 3 4 5+(a) 7 9+(a) 0 0 0 1 1 0 0 0 0 1 2 0 0 0 1 1 0 0 1 2 2 1 2 1 1 0 1 0 0 2 0 4 2 (c) (c) 0 0 0 (c) (c) (c) 0 (c) (c) (c) (c) 0 0 0 (c) (c) (c) (c) 0 (c) 0 (c) 0 (c) 0 (c) (c) 0 2(c) 0 2(c) word (a) ? (dir) word (a) ? (addr16) word (a) ? (sp) word (a) ? (rwi) word (a) ? (ear) word (a) ? (eam) word (a) ? (io) word (a) ? ((a)) word (a) ? imm16 word (a) ? ((rwi)+disp8) word (a) ? ((rli)+disp8) word (dir) ? (a) word (addr16) ? (a) word (sp) ? (a) word (rwi) ? (a) word (ear) ? (a) word (eam) ? (a) word (io) ? (a) word ((rwi)+disp8) ? (a) word ((rli)+disp8) ? (a) word (rwi) ? (ear) word (rwi) ? (eam) word (ear) ? (rwi) word (eam) ? (rwi) word (rwi) ? imm16 word (io) ? imm16 word (ear) ? imm16 word (eam) ? imm16 word ((a)) ? (ah) word (a) ?? (ear) word (a) ?? (eam) word (rwi) ?? (ear) word (rwi) ?? (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - * * * * * * * * * * * * * * * * * * * * * * * * * - * - * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - movl a,ear movl a,eam movl a,#imm32 movl ear,a movl eam,a 2 2+ 5 2 2+ 4 5+(a) 3 4 5+(a) 2 0 0 2 0 0 (d) 0 0 (d) long (a) ? (ear) long (a) ? (eam) long (a) ? imm32 long (ear1) ? (a) long (eam1) ? (a) - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * - - - - - - - - - - - - - - -
512 appendix b instructions MB90560 series table b.8-3 addition/subtraction (byte, word, long-word): 42 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw add a,#imm8 add a,dir add a,ear add a,eam add ear,a add eam,a addc a addc a,ear addc a,eam adddc a sub a,#imm8 sub a,dir sub a,ear sub a,eam sub ear,a sub eam,a subc a subc a,ear subc a,eam subdc a 2 2 2 2+ 2 2+ 1 2 2+ 1 2 2 2 2+ 2 2+ 1 2 2+ 1 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 2 5 3 4+(a) 3 5+(a) 2 3 4+(a) 3 0 0 1 0 2 0 0 1 0 0 0 0 1 0 2 0 0 1 0 0 0 (b) 0 (b) 0 2(b) 0 0 (b) 0 0 (b) 0 (b) 0 2(b) 0 0 (b) 0 byte (a) ? (a) + imm8 byte (a) ? (a) + (dir) byte (a) ? (a) + (ear) byte (a) ? (a) + (eam) byte (ear) ? (ear) + (a) byte (eam) ? (eam) + (a) byte (a) ? (ah) + (al) + (c) byte (a) ? (a) + (ear) + (c) byte (a) ? (a) + (eam) + (c) byte (a) ? (ah) + (al) + (c) (hexadecimal) byte (a) ? (a) - imm8 byte (a) ? (a) - (dir) byte (a) ? (a) - (ear) byte (a) ? (a) - (eam) byte (ear) ? (ear) - (a) byte (eam) ? (eam) - (a) byte (a) ? (ah) - (al) - (c) byte (a) ? (a) - (ear) - (c) byte (a) ? (a) - (eam) - (c) byte (a) ? (ah) - (al) - (c) (hexadecimal) z z z z - z z z z z z z z z - - z z z z - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - - - * - - - - addw a addw a,ear addw a,eam addw a,#imm16 addw ear,a addw eam,a addcw a,ear addcw a,eam subw a subw a,ear subw a,eam subw a,#imm16 subw ear,a subw eam,a subcw a,ear subcw a,eam 1 2 2+ 3 2 2+ 2 2+ 1 2 2+ 3 2 2+ 2 2+ 2 3 4+(a) 2 3 5+(a) 3 4+(a) 2 3 4+(a) 2 3 5+(a) 3 4+(a) 0 1 0 0 2 0 1 0 0 1 0 0 2 0 1 0 0 0 (c) 0 0 2(c) 0 (c) 0 0 (c) 0 0 2(c) 0 (c) word (a) ? (ah) + (al) word (a) ? (a) + (ear) word (a) ? (a) + (eam) word (a) ? (a) + imm16 word (ear) ? (ear) + (a) word (eam) ? (eam) + (a) word (a) ? (a) + (ear) + (c) word (a) ? (a) + (eam) + (c) word (a) ? (ah) - (al) word (a) ? (a) - (ear) word (a) ? (a) - (eam) word (a) ? (a) - imm16 word (ear) ? (ear) - (a) word (eam) ? (eam) - (a) word (a) ? (a) - (ear) - (c) word (a) ? (a) - (eam) - (c) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * - - - - - * - - - - - - - * - - addl a,ear addl a,eam addl a,#imm32 subl a,ear subl a,eam subl a,#imm32 2 2+ 5 2 2+ 5 6 7+(a) 4 6 7+(a) 4 2 0 0 2 0 0 0 (d) 0 0 (d) 0 long (a) ? (a) + (ear) long (a) ? (a) + (eam) long (a) ? (a) + imm32 long (a) ? (a) - (ear) long (a) ? (a) - (eam) long (a) ? (a) - imm32 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * - - - - - -
MB90560 series appendix b instructions 513 table b.8-4 increment/decrement (byte, word, long-word): 12 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. table b.8-5 comparison (byte, word, long-word): 11 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw inc ear inc eam dec ear dec eam 2 2+ 2 2+ 3 5+(a) 3 5+(a) 2 0 2 0 0 2(b) 0 2(b) byte (ear) ? (ear) + 1 byte (eam) ? (eam) + 1 byte (ear) ? (ear) - 1 byte (eam) ? (eam) - 1 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - - - * - * incw ear incw eam decw ear decw eam 2 2+ 2 2+ 3 5+(a) 3 5+(a) 2 0 2 0 0 2(c) 0 2(c) word (ear) ? (ear) + 1 word (eam) ? (eam) + 1 word (ear) ? (ear) - 1 word (eam) ? (eam) - 1 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - - - * - * incl ear incl eam decl ear decl eam 2 2+ 2 2+ 7 9+(a) 7 9+(a) 4 0 4 0 0 2(d) 0 2(d) long (ear) ? (ear) + 1 long (eam) ? (eam) + 1 long (ear) ? (ear) - 1 long (eam) ? (eam) - 1 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * - - - - - * - * mnemonic # ~ rg b operation lh ah i s t n z v c rmw cmp a cmp a,ear cmp a,eam cmp a,#imm8 1 2 2+ 2 1 2 3+(a) 2 0 1 0 0 0 0 (b) 0 byte (ah) - (al) byte (a) - (ear) byte (a) - (eam) byte (a) - imm8 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - cmpw a cmpw a,ear cmpw a,eam cmpw a,#imm16 1 2 2+ 3 1 2 3+(a) 2 0 1 0 0 0 0 (c) 0 word (ah) - (al) word (a) - (ear) word (a) - (eam) word (a) - imm16 - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * - - - - cmpl a,ear cmpl a,eam cmpl a,#imm32 2 2+ 5 6 7+(a) 3 2 0 0 0 (d) 0 long (a) - (ear) long (a) - (eam) long (a) - imm32 - - - - - - - - - - - - - - - * * * * * * * * * * * * - - -
514 appendix b instructions MB90560 series table b.8-6 unsigned multiplication/division (word, long-word): 11 instructions *1 3 for division by zero, 7 for overflow, normally 15 *2 4 for division by zero, 8 for overflow, normally 16 *3 6 + (a) for division by zero, 9 + (a) for overflow, normally 19 + (a) *4 4 for division by zero, 7 for overflow, normally 22 *5 6 + (a) for division by zero, 8 + (a) for overflow, normally 26 + (a) *6 (b) for division by zero or overflow, normally 2 x (b) *7 (c) for division by zero or overflow, normally 2 x (c) *8 3 when byte(ah) is zero, 7 otherwise *9 4 when byte(ear) is zero, 8 otherwise *10 5 + (a) when byte(eam) is zero, 9 + (a) otherwise *11 3 when word(ah) is zero, 11 otherwise *12 4 when word(ear) is zero, 12 otherwise *13 5 + (a) when word(eam) is zero, 13 + (a) otherwise see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw divu a divu a,ear divu a,eam divuw a,ear divuw a,eam mulu a mulu a,ear mulu a,eam muluw a muluw a,ear muluw a,eam 1 2 2+ 2 2+ 1 2 2+ 1 2 2+ *1 *2 *3 *4 *5 *8 *9 *10 *11 *12 *13 0 1 0 1 0 0 1 0 0 1 0 0 0 *6 0 *7 0 0 (b) 0 0 (c) word (ah) / byte (al) quotient ? byte (al) remainder ? byte (ah) word (a) / byte (ear) quotient ? byte (a) remainder ? byte (ear) word (a) / byte (eam) quotient ? byte (a) remainder ? byte (ear) long (a) / word (ear) quotient ? word (a) remainder ? word (ear) long (a) / word (eam) quotient ? word (a) remainder ? word (eam) byte (ah) * byte (al) ? word (a) byte (a) * byte (ear) ? word (a) byte (a) * byte (eam) ? word (a) word (ah) * word (al) ? long (a) word (a) * word (ear) ? long (a) word (a) * word (eam) ? long (a) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * - - - - - - * * * * * - - - - - - - - - - - - - - - - -
MB90560 series appendix b instructions 515 table b.8-7 logical 1 (byte, word): 39 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw and a,#imm8 and a,ear and a,eam and ear,a and eam,a or a,#imm8 or a,ear or a,eam or ear,a or eam,a xor a,#imm8 xor a,ear xor a,eam xor ear,a xor eam,a not a not ear not eam 2 2 2+ 2 2+ 2 2 2+ 2 2+ 2 2 2+ 2 2+ 1 2 2+ 2 3 4+(a) 3 5+(a) 2 3 4+(a) 3 5+(a) 2 3 4+(a) 3 5+(a) 2 3 5+(a) 0 1 0 2 0 0 1 0 2 0 0 1 0 2 0 0 2 0 0 0 (b) 0 2(b) 0 0 (b) 0 2(b) 0 0 (b) 0 2(b) 0 0 2(b) byte (a) ? (a) and imm8 byte (a) ? (a) and (ear) byte (a) ? (a) and (eam) byte (ear) ? (ear) and (a) byte (eam) ? (eam) and (a) byte (a) ? (a) or imm8 byte (a) ? (a) or (ear) byte (a) ? (a) or (eam) byte (ear) ? (ear) or (a) byte (eam) ? (eam) or (a) byte (a) ? (a) xor imm8 byte (a) ? (a) xor (ear) byte (a) ? (a) xor (eam) byte (ear) ? (ear) xor (a) byte (eam) ? (eam) xor (a) byte (a) ? not (a) byte (ear) ? not (ear) byte (eam) ? not (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r - - - - - - - - - - - - - - - - - - - - - - * - - - - * - - - - * - - * andw a andw a,#imm16 andw a,ear andw a,eam andw ear,a andw eam,a orw a orw a,#imm16 orw a,ear orw a,eam orw ear,a orw eam,a xorw a xorw a,#imm16 xorw a,ear xorw a,eam xorw ear,a xorw eam,a notw a notw ear notw eam 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 3 2 2+ 2 2+ 1 2 2+ 2 2 3 4+(a) 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 2 3 4+(a) 3 5+(a) 2 3 5+(a) 0 0 1 0 2 0 0 0 1 0 2 0 0 0 1 0 2 0 0 2 0 0 0 0 (c) 0 2(c) 0 0 0 (c) 0 2(c) 0 0 0 (c) 0 2(c) 0 0 2(c) word (a) ? (ah) and (a) word (a) ? (a) and imm16 word (a) ? (a) and (ear) word (a) ? (a) and (eam) word (ear) ? (ear) and (a) word (eam) ? (eam) and (a) word (a) ? (ah) or (a) word (a) ? (a) or imm16 word (a) ? (a) or (ear) word (a) ? (a) or (eam) word (ear) ? (ear) or (a) word (eam) ? (eam) or (a) word (a) ? (ah) xor (a) word (a) ? (a) xor imm16 word (a) ? (a) xor (ear) word (a) ? (a) xor (eam) word (ear) ? (ear) xor (a) word (eam) ? (eam) xor (a) word (a) ? not (a) word (ear) ? not (ear) word (eam) ? not (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * r r r r r r r r r r r r r r r r r r r r r - - - - - - - - - - - - - - - - - - - - - - - - - - * - - - - - * - - - - - * - - *
516 appendix b instructions MB90560 series table a.2-1 logical 2 (long-word): 6 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. table b.8-9 sign inversion (byte, word): 6 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. table b.8-10 normalization (long-word): 1 instruction *1 4 when all accumulators indicate 0, 6 + (r0) otherwise see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw andl a,ear andl a,eam orl a,ear orl a,eam xorl a,ear xorl a,eam 2 2+ 2 2+ 2 2+ 6 7+(a) 6 7+(a) 6 7+(a) 2 0 2 0 2 0 0 (d) 0 (d) 0 (d) long (a) ? (a) and (ear) long (a) ? (a) and (eam) long (a) ? (a) or (ear) long (a) ? (a) or (eam) long (a) ? (a) xor (ear) long (a) ? (a) xor (eam) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * * * * r r r r r r - - - - - - - - - - - - mnemonic # ~ rg b operation lh ah i s t n z v c rmw neg a neg ear neg eam 1 2 2+ 2 3 5+(a) 0 2 0 0 0 2+(b) byte (a) ? 0 - (a) byte (ear) ? 0 - (ear) byte (eam) ? 0 - (eam) x - - - - - - - - - - - - - - * * * * * * * * * * * * - - * negw a negw ear negw eam 1 2 2+ 2 2 5+(a) 0 2 0 0 0 2+(c) word (a) ? 0 - (a) word (ear) ? 0 - (ear) word (eam) ? 0 - (eam) - - - - - - - - - - - - - - - * * * * * * * * * * * * - - * mnemonic # ~ rg b operation lh ah i s t n z v c rmw nrml a,r0 2 *1 1 0 long (a) ? shift to the position where 1 was formerly placed byte (r0) ? number of shifts at that time ------ * -- -
MB90560 series appendix b instructions 517 table b.8-11 shift instructions (byte, word, long-word): 18 instructions *1 6 when r0 is zero, 5 + (r0) otherwise *2 6 when r0 is zero, 5 + (r0) otherwise see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw rorc a rolc a rorc ear rorc eam rolc ear rolc eam asr a,ro lsr a,ro lsl a,ro 2 2 2 2+ 2 2+ 2 2 2 2 2 3 5+(a) 3 5+(a) *1 *1 *1 0 0 2 0 2 0 1 1 1 0 0 0 2(b) 0 2(b) 0 0 0 byte (a) ? right rotate with carry byte (a) ? left rotate with carry byte (ear) ? right rotate with carry byte (eam) ? right rotate with carry byte (ear) ? left rotate with carry byte (eam) ? left rotate with carry byte (a) ? arithmetic right barrel shift (a,r0) byte (a) ? logical right barrel shift (a,r0) byte (a) ? logical left barrel shift (a,r0) - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * - * * * * * * * * * * * * * * * * * * - - - - - - - - - * * * * * * * * * - - - * - * - - - asrw a lsrw a / shrw a lslw a / shlw a asrw a,r0 lsrw a,r0 lslw a,r0 1 1 1 2 2 2 2 2 2 *1 *1 *1 0 0 0 1 1 1 0 0 0 0 0 0 word (a) ? arithmetic right shift (a,1 bit) word (a) ? logical right shift (a,1 bit) word (a) ? logical left shift (a,1 bit) word (a) ? arithmetic right barrel shift (a,r0) word (a) ? logical right barrel shift (a,r0) word (a) ? logical left barrel shift (a,r0) - - - - - - - - - - - - - - - - - - - - - - - - * * - * * - * r * * * * * * * * * * - - - - - - * * * * * * - - - - - - asrl a,r0 lsrl a,r0 lsll a,r0 2 2 2 *2 *2 *2 1 1 1 0 0 0 long (a) ? arithmetic right barrel shift (a,r0) long (a) ? logical right barrel shift (a,r0) long (a) ? logical left barrel shift (a,r0) - - - - - - - - - - - - * * - * * * * * * - - - * * * - - -
518 appendix b instructions MB90560 series table b.8-12 branching instructions (1): 31 instructions *1 4 when branching occurs, 3 otherwise *2 3 x (c) + (b) *3 reads a branch destination address (word). *4 write: saves to stack (word), read: reads a branch destination address (word). *5 saves to stack (word). *6 write: saves to stack (long-word), read: reads a branch destination address (long-word). *7 saves to stack (long-word). see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw bz / beq rel bnz / bne rel bc / blo rel bnc / bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel bra rel jmp @a jmp addr16 jmp @ear jmp @eam jmpp @ear *1 jmpp @eam *1 jmpp addr24 call @ear *2 call @eam *2 call addr16 *3 callv #vct4 *3 callp @ear *4 callp @eam *4 callp addr24 *5 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 1 3 2 2+ 2 2+ 4 2 2+ 3 1 2 2+ 4 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 *1 2 3 3 4+(a) 5 6+(a) 4 6 7+(a) 6 7 10 11+(a) 10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 2 0 0 1 0 0 0 2 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) 0 (d) 0 (c) 2(c) (c) 2(c) 2(c) *2 2(c) branch when (z) = 1 branch when (z) = 0 branch when (c) = 1 branch when (c) = 0 branch when (n) = 1 branch when (n) = 0 branch when (v) = 1 branch when (v) = 0 branch when (t) = 1 branch when (t) = 0 branch when (v) xor (n) = 1 branch when (v) xor (n) = 0 branch when ((v) xor (n)) or (z) = 1 branch when ((v) xor (n)) or (z) = 0 branch when (c) or (z) = 1 branch when (c) or (z) = 0 unconditional branching word (pc) ? (a) word (pc) ? addr16 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? (ear), (pcb) ? (ear+2) word (pc) ? (eam), (pcb) ? (eam+2) word (pc) ? ad24 0-15, (pcb) ? ad24 16-23 word (pc) ? (ear) word (pc) ? (eam) word (pc) ? addr16 vector call instruction word (pc) ? (ear) 0-15, (pcb) ? (ear)16-23 word (pc) ? (eam) 0-15, (pcb) ? (eam)16-23 word (pc) ? addr0-15, (pcb) ? addr16-23 - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MB90560 series appendix b instructions 519 table b.8-13 branch instructions (2): 19 instructions *1 5 when branching occurs, 4 otherwise *2 13 when branching occurs, 12 otherwise *3 7 + (a) when branching occurs, 6 + (a) otherwise *4 8 when branching occurs, 7 otherwise *5 7 when branching occurs, 6 otherwise *6 8 + (a) when branching occurs, 7 + (a) otherwise *7 returns from stack (word) *8 returns from stack (long-word) *9 do not use the rwj + addressing mode for a cbne/cwbne instruction. see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw cbne a,#imm8,rel cwbne a,#imm16,rel cbne ear,#imm8,rel cbne eam,#imm8,rel cwbne ear,#imm16,rel cwbne eam,#imm16,rel dbnz ear,rel dbnz eam,rel dwbnz ear,rel dwbnz eam,rel int #vct8 int addr16 intp addr24 int9 reti link #imm8 unlink ret *1 retp *2 3 4 4 4+ 5 5+ 3 3+ 3 3+ 2 3 4 1 1 2 1 1 1 *1 *1 *2 *3 *4 *3 *5 *6 *5 *6 20 16 17 20 11 6 5 4 6 0 0 1 0 1 0 2 2 2 2 0 0 0 0 0 0 0 0 0 0 0 0 (b) 0 (c) 0 2(b) 0 2(c) 8(c) 6(c) 6(c) 8(c) *7 (c) (c) (c) (d) branch when byte (a) 1 imm8 branch when word (a) 1 imm16 branch when byte (ear) 1 imm8 branch when byte (eam) 1 imm8 branch when word (ear) 1 imm16 branch when word (eam) 1 imm16 branch when byte (ear)=(ear)-1, (ear) 1 0 branch when byte (eam)=(eam)-1, (eam) 1 0 branch when word (ear)=(ear)-1, (ear) 1 0 branch when word (eam)=(eam)-1, (eam) 1 0 software interrupt software interrupt software interrupt software interrupt recovery from interrupt at the entrance of function, save old frame pointers into a stack, set up new frame point- ers, reserve area for local pointers. at the exit of function, recover the old frame pointers from the stack. recover from the subroutine. recover from the subroutine. - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - r r r r * - - - - - - - - - - - - - - s s s s * - - - - - - - - - - - - - - - - - - * - - - - * * * * * * * * * * - - - - * - - - - * * * * * * * * * * - - - - * - - - - * * * * * * * * * * - - - - * - - - - * * * * * * - - - - - - - - * - - - - - - - - - - - * - * - - - - - - - - -
520 appendix b instructions MB90560 series table b.8-14 other control instructions (byte, word, long-word): 28 instructions *1 pcb,adb,ssb,usb ------------1 dtb,dpr --------------------------2 *2 7 + 3 x (pop count) + 2 x (last register number popped), 7 when rlst = 0 (no transfer register) *3 29 + 3 x (push count) - 3 x (last register number pushed), 8 when rlst = 0 (no transfer register) *4 (pop count) x (c) or (push count) x (c) *5 (pop count) or (push count) see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw pushw a pushw ah pushw ps pushw rlst popw a popw ah popw ps popw rlst jctx @a and ccr,#imm8 or ccr,#imm8 mov rp,#imm8 mov ilm,#imm8 movea rwi,ear movea rwi,eam movea a,ear movea a,eam addsp #imm8 addsp #imm16 mov a,brgl mov brg2,a nop adb dtb pcb spb ncc cmr 1 1 1 2 1 1 1 2 1 2 2 2 2 2 2+ 2 2+ 2 3 2 2 1 1 1 1 1 1 1 4 4 4 *3 3 3 4 *2 14 3 3 2 2 3 2+(a) 1 1+(a) 3 3 *1 1 1 1 1 1 1 1 1 0 0 0 +& 0 0 0 +& 0 0 0 0 0 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 (c) (c) (c) *4 (c) (c) (c) *4 6(c) 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 word (sp) ? (sp) -2, ((sp)) ? (a) word (sp) ? (sp) -2, ((sp)) ? (ah) word (sp) ? (sp) -2, ((sp)) ? (ps) (sp) ? (sp) - 2n, ((sp)) ? (rlst) word (a) ? ((sp)), (sp) ? (sp) + 2 word (ah) ? ((sp)), (sp) ? (sp) + 2 word (ps) ? ((sp)), (sp) ? (sp) + 2 (rlst) ? ((sp)), (sp) ? (sp) context switching instruction byte (ccr) ? (ccr) and imm8 byte (ccr) ? (ccr) or imm8 byte (rp) ? imm8 byte (ilm) ? imm8 word (rwi) ? ear word (rwi) ? eam word (a) ? ear word (a) ? eam word (sp) ? ext(imm8) word (sp) ? imm16 byte (a) ? (brg1) byte (brg2) ? (a) no operation prefix code for ad space access prefix code for dt space access prefix code for pc space access prefix code for sp space access prefix code for flag unchange setting prefix for common register banks - - - - - - - - - - - - - - - - - - - z - - - - - - - - - - - - * - - - - - - - - - - * * - - * - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - * * - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - * - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - -
MB90560 series appendix b instructions 521 table b.8-15 bit operation instructions: 21 instructions *1 8 when branching occurs, 7 otherwise *2 7 when branching occurs, 6 otherwise *3 10 when conditions are met, 9 otherwise *4 undefined number of cycles *5 until conditions are met table b.8-16 accumulator operation instructions (byte, word): 6 instructions see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movb a,dir:bp movb a,addr16:bp movb a,io:bp movb dir:bp,a movb addr16:bp,a movb io:bp,a setb dir:bp setb addr16:bp setb io:bp clrb dir:bp clrb addr16:bp clrb io:bp bbc dir:bp,rel bbc addr16:bp,rel bbc io:bp,rel bbs dir:bp,rel bbs addr16:bp,rel bbs io:bp,rel sbbs addr16:bp,rel wbts io:bp wbtc io:bp 3 4 3 3 4 3 3 4 3 3 4 3 4 5 4 4 5 4 5 3 3 5 5 4 7 7 6 7 7 7 7 7 7 *1 *1 *2 *1 *1 *2 *3 *4 *4 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 (b) (b) (b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) 2(b) (b) (b) (b) (b) (b) (b) 2(b) *5 *5 byte (a) ? ( dir:bp )b byte (a) ? ( addr16:bp )b byte (a) ? ( io:bp )b bit ( dir:bp )b ? (a) bit ( addr16:bp )b ? (a) bit ( io:bp )b ? (a) bit ( dir:bp )b ? 1 bit ( addr16:bp )b ? 1 bit ( io:bp )b ? 1 bit ( dir:bp )b ? 0 bit ( addr16:bp )b ? 0 bit ( io:bp )b ? 0 branch when ( dir:bp )b = 0 branch when ( addr16:bp )b = 0 branch when ( io:bp)b = 0 branch when ( dir:bp )b = 1 branch when ( addr16:bp )b = 1 branch when ( io:bp)b = 1 branch when (addr16:bp) b = 1, bit = 1 wait until (io:bp) b = 1 wait until (io:bp) b = 0 z z z - - - - - - - - - - - - - - - - - - * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * - - - - - - - - - - - - - - - * * * * * * - - - - - - * * * * * * * - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * * * * * * * - - - - - - * - - mnemonic # ~ rg b operation lh ah i s t n z v c rmw swap swapw / xchw a,t ext extw zext zextw 1 1 1 1 1 1 3 2 1 2 1 1 0 0 0 0 0 0 0 0 0 0 0 0 byte (a)0-7 ?? (a)8-15 word (ah) ?? (al) byte signed extension word signed extension byte zero extension word zero extension - - x - z - - * - x - z - - - - - - - - - - - - - - - - - - - - * * r r - - * * * * - - - - - - - - - - - - - - - - - -
522 appendix b instructions MB90560 series table b.8-17 string instructions: 10 instructions *1 5 when rw0 is zero, 4 + 7 x (rw0) when counter limit reached, 7n + 5 for a match *2 5 when rw0 is zero, 4 + 8 x (rw0) otherwise *3 (b) x (rw0) + (b) x (rw0). when source and destination access different areas, calculate item (b) separately. *4 (b) x n *5 2 x (rw0) *6 (c) x (rw0) + (c) x (rw0). when source and destination access different areas, calculate item (c) separately. *7 (c) x n *8 2 x (rw0) note: m: rw0 value (counter value) n: loop count see table b.5-1, "number of execution cycles for each type of addressing," and table b.5-2, "compensation values for calculating the number of execution cycles," for (a) to (d) in the above table. mnemonic # ~ rg b operation lh ah i s t n z v c rmw movs / movsi movsd sceq / sceqi sceqd fils / filsi 2 2 2 2 2 *2 *2 *1 *1 6m+6 +& +& +& +& +& *3 *3 *4 *4 *3 byte transfer @ah+ ? @al+, counter = rw0 byte transfer @ah- ? @al-, counter = rw0 byte search @ah+ ? al, counter = rw0 byte search @ah- ? al, counter = rw0 byte fill @ah+ ? al, counter = rw0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * - - - * * - - - - - - movsw / movswi movswd scweq / scweqi scweqd filsw / filswi 2 2 2 2 2 *2 *2 *1 *1 6m+6 +) +) +) +) +) *6 *6 *7 *7 *6 word transfer @ah+ ? @al+, counter = rw0 word transfer @ah- ? @al-, counter = rw0 word search @ah+ ? al, counter = rw0 word search @ah- ? al, counter = rw0 word fill @ah+ ? al, counter = rw0 - - - - - - - - - - - - - - - - - - - - - - - - - - - * * * - - * * * - - * * - - - * * - - - - - -
MB90560 series appendix b instructions 523 b.9 instruction maps an f 2 mc-16l instruction code consists of one or two bytes. accordingly an instruction map consists of several one-byte or two-byte pages. tables b.9-2 to b.9-20 show f 2 mc-16l instruction maps. n configuration of instruction maps figure b.9-1 configuration of instruction maps when the instruction code is a 1-byte instruction (nop instruction, etc.), the instruction code is described on the basic page map. when the instruction code is a 2-byte instruction (movs, etc.), see the basic page map and check the name of the map where the second byte of the instruction code to be referenced next is described. basic page map : 1st byte : 2nd byte bit operation instructions character string opera- tion instructions 2-byte instructions ea instructions x 9
524 appendix b instructions MB90560 series figure b.9-2 shows the relationship between the actual instruction code and instruction maps. figure b.9-2 relationship between actual instruction codes and instruction maps table b.9-1 lists instruction code examples. table b.9-1 example instruction codes instruction 1st byte (from the basic page map) 2nd byte (from the extended page map) nop 00 + 0 = 00 - and a,#8 30 + 4 = 34 - mov a,adb 60 + f = 6f 00 + 0 = 00 @rw2+d8,#8,rel 70 + 0 = 70 f0 + 2 = f2 instruction code first byte second byte operand operand may not exist for some instructions length differs according to the [basic page map] [extension page map] note ? ? ? xy uv +w +z ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? instruction note: extended page maps are provided for bit manipulation instructions, character string manipulation instructions, two-byte instructions, and ea instructions; multiple-extended-page maps exist for each type of instruction.
MB90560 series appendix b instructions 525 table b.9-2 basic page map 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + a + b + c + d + e + f nop int9 adddc neg pcb dtb adb spb link unlink mov negw lslw asrw lsrw imm#8 cmr ncc subdc jctx ext zext swap addsp addl subl mov cmpl extw zextw swapw addsp a ilm, #8 #16 add sub addc cmp and or divu mulu addw subw cbne a, cmpw andw orw xorw muluw a, dir a, dir a a ccr, #8 ccr, #8 a a a a #8, rel a a a a a add sub subc cmp and or xor not addw subw cwbne cmpw andw orw xorw notw a, #8 a, #8 a a, #8 a, #8 a, #8 a, #8 a a, #16 a, #16 a, #16, rel a, #16 a, #16 a, #16 a, #16 a mov a, dir mov dir, a mov a, #8 movx a, #8 mov dir, #8 movx a, dir movw a, sp movw sp, a movw a, dir movw dir, a movw a, #16 movl a, #32 pushw a pushw ah pushw ps pushw rlst mov a, io mov io, a mov a, addr16 mov addr 16, a mov io, #8 movx a, io movw io, #16 movx a, addr16 movw a, io movw io, a movw a, addr16 movw addr16, a popw a popw ah popw ps popw rlst bra rel jmp @a jmp addr16 jmpp addr24 call addr16 callp addr24 retp ret int #vct8 int addr16 intp addr24 reti bit string two-byte operation instructions instructions operation instructions ea instructions (1) ea ea ea ea ea ea ea ea movea rwi, ea mov ri, ea movw rwi, ea mov ea, ri movw ea, rwi xch ri, ea xcrw rwi, ea instructions (2) instructions (3) instructions (4) instructions (5) instructions (6) instructions (7) instructions (8) instructions (9) mov a, ri mov ri, a mov ri, #8 movx a, ri movx a,@rwi+d8 movn a, #4 callv #4 bz /beq rel bnz/bne rel bc /blo rel bnc/bhs rel bn rel bp rel bv rel bnv rel bt rel bnt rel blt rel bge rel ble rel bgt rel bls rel bhi rel movw a, rwi movw rwi, a movw rwi, #16 movw @rwi+db movw @rwi+db, a a a rp, #8 a @a #8 a, #32 a, #32 a a a a, #32
526 appendix b instructions MB90560 series table b.9-3 bit operation instruction map (1st byte = 6c h ) 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0 e 0f 0 + 0 + 1 + 2 + 3 + 4 + 5 + 6 + 7 + 8 + 9 + a + b +c +d + e + f movb a, io:bp movb io:bp, a clrb io:bp setb io:bp bbs io:bp, rel bbc io:bp, rel wbts io:bp wbtc io:bp movb a, dir:bp movb a, addr16:bp movb dir: bp,a movb addr16: bp, a clrb dir:bp clrb addr16:bp setb dir:bp setb addr16:bp bbc dir:bp,rel bbc ad16:bp, rel bbs ad 16:bp, rel bbs dir:bp, rel sbbs addr16:bp
MB90560 series appendix b instructions 527 table b.9-4 character string operation instruction map (1st byte = 6e h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 movsi movsd movswi movswd pcb, pcb pcb, dtb pcb, adb pcb, spb dtb, pcb dtb, dtb dtb, adb dtb, spb adb, pcb adb, dtb adb, adb adb, spb spb, pcb spb, dtb spb, adb spb, spb sceqi sceqd scweqi scweqd filsi filswi pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb pcb dtb adb spb
528 appendix b instructions MB90560 series table b.9-5 2-byte instruction map (1st byte = 6f h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 mov a, dtb mov a, adb mov a, ssb mov a, usb mov a. dpr mov a. @a mov a, pcb rolc a lslw a, r0 movw a, @a asrw a, r0 lsrw a, r0 mov dtb, a mov adb, a mov ssb, a mov usb, a mov dpr, a mov @al, ah movx a, @a rorc a lsll a, r0 movw @al, ah asrl a, r0 lsrl a, r0 movx a, @rl0 +d8 movx a, @rl1+d8 movx a, @rl2+d8 movx a, @rl3+d8 lsl a, r0 nrml a, r0 asr a, r0 lsr a, r0 mov @rl0+d8, a mov @rl1+d8, a mov @rl2+d8, a mov @rl3+d8, a mov a, @rl0+d8 mov a, @rl1+d8 mov a, @rl2+d8 mov a, @rl3+d8 movw @rl0+d8, a movw @rl1+d8, a movw @rl2+d8, a movw @rl3+d8, a movw a, @rl0+d8 movw a, @rl1+d8 movw a, @rl2+d8 movw a, @rl3+d8 mul a mulw a divu a
MB90560 series appendix b instructions 529 table b.9-6 ea instruction map (1) (1st byte = 70 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 addl a, rl0 addl a, rl0 addl a, rl1 addl a, rl1 addl a, rl2 addl a, rl2 addl a, rl3 addl a, rl3 addl a, @rw0 addl a, @rw1 addl a, @rw2 addl a, @rw3 addl a, @rw0+ addl a, @rw1+ addl a, @rw2+ addl a, @rw3+ addl a, @rw0+d8 addl a, @rw1+d8 addl a, @rw2+d8 addl a, @rw3+d8 addl a, @rw4+d8 addl a, @rw5+d8 addl a, @rw6+d8 addl a, @rw7+d8 addl a, @rw0+d16 addl a, @rw1+d16 addl a, @rw2+d16 addl a, @rw3+d16 addl a, @rw0+rw7 addl a, @rw1+rw7 addl a, @pc+d16 addl a, addr16 andl a, rl0 andl a, rl0 andl a, rl1 andl a, rl1 andl a, rl2 andl a, rl2 andl a, rl3 andl a, rl3 andl a, @rw0 andl a, @rw1 andl a, @rw2 andl a, @rw3 andl a, @rw0+ andl a, @rw1+ andl a, @rw2+ andl a, @rw3+ subl a, rl0 subl a, rl0 subl a, rl1 subl a, rl1 subl a, rl2 subl a, rl2 subl a,rl3 subl a, rl3 a, @rw0 subl a, @rw1 subl a, @rw2 subl a, @rw3 subl a, @rw0+ subl a, @rw1+ subl a, @rw2+ subl a, @rw3+ subl a, @rw0+d8 subl a, @rw1+d8 subl a, @rw2+d8 subl a, @rw3+d8 subl a, @rw4+d8 subl a, @rw5+d8 subl a, @rw6+d8 subl a, subl a, @rw0+d16 subl a, @rw1+d16 subl a, @rw2+d16 subl a, @rw3+d16 subl a, @rw0+rw7 subl a, @rw1+rw7 subl a, @pc+d16 subl a, addr16 cwbne rw0, #16, rel cwbne rw1, #16, rel cwbne rw2, #16, rel cwbne rw3, #16, rel cwbne rw4, #16, rel cwbne rw5, #16, rel cwbne rw6, #16, rel cwbne rw7, #16, rel cwbne @ rw0, #16, rel cwbne @ rw1, #16, rel cwbne @ rw2, #16, rel cwbne @ rw3, #16, rel cwbne @rw1+rw7 ,#16, rel cwbne @pc+d16, #16, rel cwbne addr16, #16, rel cwbne @rw0+d8, #16, rel cwbne @rw1+d8, #16, rel cwbne @rw2+d8, #16, rel cwbne @rw3+d8, #16, rel cwbne @rw4+d8, #16, rel cwbne @rw5+d8, #16, rel cwbne @rw6+d8, #16, rel cwbne @rw7+d8, #16, rel cwbne @rw0+d16, #16, rel cwbne @rw1, d16, #16, rel cwbne @rw2+d16, #16, rel cwbne @rw3+d16, #16, rel cwbne @rw0+rw7 ,#16, rel cmpl a, @rw0+d8 cmpl a, @rw1+d8 cmpl a, @rw2+d8 cmpl a, @rw3+d8 cmpl a, @rw4+d8 cmpl a, @rw5+d8 cmpl a, @rw6+d8 cmpl a, @rw7+d8 cmpl a, @rw0+d16 cmpl a, @rw1+d16 cmpl a, @rw2+d16 cmpl a, @rw3+d16 cmpl a, @rw0+rw7 cmpl a, @rw1+rw7 cmpl a, @pc+d16 cmpl a, addr16 cmpl a, rl0 cmpl a, rl0 cmpl a, rl1 cmpl a, rl1 cmpl a, rl2 cmpl a, rl2 cmpl a, rl3 cmpl a, rl3 cmpl a, @rw0 cmpl a, @rw1 cmpl a, @rw2 cmpl a, @rw3 cmpl a, @rw0+ cmpl a, @rw1+ cmpl a, @rw2+ cmpl a, @rw3+ andl a, @rw0+d8 andl a, @rw1+d8 andl a, @rw2+d8 andl a, @rw3+d8 andl a, @rw4+d8 andl a, @rw5+d8 andl a, @rw6+d8 andl a, @rw7+d8 andl a, @rw0+d16 andl a, @rw1+d16 andl a, @rw2+d16 andl a, @rw3+d16 andl a, @rw0+rw7 andl a, @rw1+rw7 andl a, @pc+d16 andl a, addr16 orl a, @rw0+d8 orl a, @rw1+d8 orl a, @rw2+d8 orl a, @rw3+d8 orl a, @rw4+d8 orl a, @rw5+d8 orl a, @rw6+d8 orl a, @rw7+d8 orl a, @rw0+d16 orl a, @rw1+d16 orl a, @rw2+d16 orl a, @rw3+d16 orl a, @rw0+rw7 orl a, @rw1+rw7 orl a, @pc+d16 orl a, addr16 xorl a, @rw0+d8 xorl a, @rw1+d8 xorl a, @rw2+d8 xorl a, @rw3+d8 xorl a, @rw4+d8 xorl a, @rw5+d8 xorl a, @rw6+d8 xorl a, @rw7+d8 xorl a, @rw0+d16 xorl a, @rw1+d16 xorl a, @rw2+d16 xorl a, @rw3+d16 xorl a, @rw0+rw7 xorl a, @rw1+rw7 xorl a, @pc+d16 xorl a, addr16 orl a, rl0 orl a, rl0 orl a, rl1 orl a, rl1 orl a, rl2 orl a, rl2 orl a, rl3 orl a, rl3 orl a, @rw0 orl a, @rw1 orl a, @rw2 orl a, @rw3 orl a, @rw0+ orl a, @rw1+ orl a, @rw2+ orl a, @rw3+ xorl a, rl0 xorl a, rl0 xorl a, rl1 xorl a, rl1 xorl a, rl2 xorl a, rl2 xorl a, rl3 xorl a, rl3 xorl a, @rw0 xorl a, @rw1 xorl a, @rw2 xorl a, @rw3 xorl a, @rw0+ xorl a, @rw1+ xorl a, @rw2+ xorl a, @rw3+ cbne r0, #8, rel cbne r1, #8, rel cbne r2, #8, rel cbne r3, #8, rel cbne r4, #8, rel cbne r5, #8, rel cbne r6, #8, rel cbne r7, #8, rel cbne @rw0, #8, rel cbne @rw1, #8, rel cbne @rw2, #8, rel cbne @rw3, #8, rel cbne @rw1+rw7 #8, rel cbne @pc+d16, #8, rel cbne addr16, #8, rel cbne @rw0+d8, #8, rel cbne @rw1+d8, #8, rel cbne @rw2+d8, #8, rel cbne @rw4+d8, #8, rel cbne @rw6+d8, #8, rel cbne @rw7+d8, #8, rel cbne @rw0+d16, #8, rel cbne @rw1+d16, #8, rel cbne @rw2+d16, #8, rel cbne @rw3+d16, #8, rel cbne @rw0+rw7 , #8, rel cbne @rw3+d8, #8, rel cbne @rw5+d8, #8, rel subl @rw7+d8 prohibit prohibit prohibit prohibit prohibit prohibit prohibit prohibit
530 appendix b instructions MB90560 series table b.9-7 ea instruction map (2) (1st byte = 71 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 jmpp @rl0 jmpp @rl0 jmpp @rl1 jmpp @rl1 jmpp @rl2 jmpp @rl2 jmpp @rl3 jmpp @rl3 jmpp @@rw0 jmpp @@rw1 jmpp @@rw2 jmpp @@rw3 jmpp @@rw0+ jmpp @@rw1+ jmpp @@rw2+ jmpp @@rw3+ jmpp @@rw0+d8 jmpp @@rw1+d8 jmpp @@rw2+d8 jmpp @@rw3+d8 jmpp @@rw4+d8 jmpp @@rw5+d8 jmpp @@rw6+d8 jmpp @@rw7+d8 jmpp @ @rw0+d16 jmpp @ @rw1+d16 jmpp @ @rw2+d16 jmpp @ @rw3+d16 jmpp @ @rw0+rw7 jmpp @ @rw1+rw7 jmpp @@pc+d16 jmpp @addr16 callp @rl0 callp @rl0 callp @rl1 callp @rl1 callp @rl2 callp @rl2 callp @rl3 callp @rl3 callp @@rw0 callp @@rw1 callp @@rw2 callp @@rw3 callp @@rw0+ callp @@rw1+ callp @@rw2+ callp @@rw3+ incl rl0 incl rl0 incl rl1 incl rl1 incl rl2 incl rl2 incl rl3 incl rl3 incl @rw0 incl @rw1 incl @rw2 incl @rw3 incl @rw0+ incl @rw1+ incl @rw2+ incl @rw3+ decl rl0 decl rl0 decl rl1 decl rl1 decl rl2 decl rl2 decl rl3 decl rl3 decl @rw0 decl @rw1 decl @rw2 decl @rw3 decl @rw0+ decl @rw1+ decl @rw2+ decl @rw3+ movl a, rl0 movl a, rl0 movl a, rl1 movl a, rl1 movl a, rl2 movl a, rl2 movl a, rl3 movl a, rl3 movl a, @rw0 movl a, @rw1 movl a, @rw2 movl a,@ rw3 movl a, @rw0+ movl a, @rw1+ movl a, @rw2+ movl a, @rw3+ movl rl0, a movl rl0, a movl rl1, a movl rl1, a movl rl2, a movl rl2, a movl rl3, a movl rl3, a movl @rw0, a movl @rw1, a movl @rw2, a movl @rw3, a movl @rw0+, a movl @rw1+, a movl @rw2+, a movl @rw3+, a mov r0, #8 mov r1, #8 mov r2, #8 mov r3, #8 mov r4, #8 mov r5, #8 mov r6, #8 mov r7, #8 mov @rw0, #8 mov @rw1, #8 mov @rw2, #8 mov @rw3, #8 mov @rw0+, #8 mov @rw1+, #8 mov @rw2+, #8 mov @rw3+, #8 movea a, rw0 movea a, rw1 movea a, rw2 movea a, rw3 movea a, rw4 movea a, rw5 movea a, rw6 movea a, rw7 movea a, @rw0 movea a, @rw1 movea a, @rw2 movea a, @rw3 movea a, @rw0+ movea a, @rw1+ movea a, @rw2+ movea a, @rw3+ callp @@rw0+d8 callp @@rw1+d8 callp @@rw2+d8 callp @@rw3+d8 callp @@rw4+d8 callp @@rw5+d8 callp @@rw6+d8 callp @@rw7+d8 callp @ @rw0+d16 callp @ @rw1+d16 callp @ @rw2+d16 callp @ @rw3+d16 callp @ @rw0+rw7 callp @ @rw1+rw7 callp @@pc+d16 callp @addr16 incl @rw0+d8 incl @rw1+d8 incl @rw2+d8 incl @rw3+d8 incl @rw4+d8 incl @rw5+d8 incl @rw6+d8 incl @rw7+d8 incl @rw0+d16 incl @rw1+d16 incl @rw2+d16 incl @rw3+d16 incl @rw0+rw7 incl @rw1+rw7 incl @pc+d16 incl addr16 decl @rw0+d8 decl @rw1+d8 decl @rw2+d8 decl @rw3+d8 decl @rw4+d8 decl @rw5+d8 decl @rw6+d8 decl @rw7+d8 decl @rw0+d16 decl @rw1+d16 decl @rw2+d16 decl @rw3+d16 decl @rw0+rw7 decl @rw1+rw7 decl @pc+d16 decl addr16 movl a, @rw0+d8 movl a, @rw1+d8 movl a, @rw2+d8 movl a, @rw3+d8 movl a, @rw4+d8 movl a, @rw5+d8 movl a, @rw6+d8 movl a, @rw7+d8 movl a, @rw0+d16 movl a, @rw1+d16 movl a, @rw2+d16 movl a, @rw3+d16 movl a, @rw0+rw7 movl a, @rw1+rw7 movl a, @pc+d16 movl a, addr16 movl @r w0+d8, a movl @r w1+d8, a movl @r w2+d8, a movl @r w3+d8, a movl @r w4+d8, a movl @r w5+d8, a movl @r w6+d8, a movl @r w7+d8, a movl @r w0+d16, a movl @r w1+d16, a movl @r w2+d16, a movl @r w3+d16, a movl @r w0+rw7, a movl @r w1+rw7, a movl @p c+d16, a movl addr16, a mov @r w0+d8, #8 mov @r w1+d8, #8 mov @r w2+d8, #8 mov @r w3+d8, #8 mov @r w4+d8, #8 mov @r w5+d8, #8 mov @r w6+d8, #8 mov @r w7+d8, #8 mov @r w0+d16, #8 mov @r w1+d16, #8 mov @r w2+d16, #8 mov @r w3+d16, #8 mov @r w0+rw7, #8 mov @r w1+rw7, #8 mov @p c+d16, #8 mov addr16, #8 movea a, @rw0+d8 movea a, @rw1+d8 movea a, @rw2+d8 movea a, @rw3+d8 movea a, @rw4+d8 movea a, @rw5+d8 movea a, @rw6+d8 movea a, @rw7+d8 movea a, @rw0+d16 movea a, @rw1+d16 movea a, @rw2+d16 movea a, @rw3+d16 movea a, @rw0+rw7 movea a, @rw1+rw7 movea a, @pc+d16 movea a, addr16
MB90560 series appendix b instructions 531 table b.9-8 ea instruction map (3) (1st byte = 72 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 rolc r0 rolc r1 rolc r2 rolc r3 rolc r4 rolc r5 rolc r6 rolc r7 rolc @rw0 rolc @rw1 rolc @rw2 rolc @rw3 rolc @rw0+ rolc @rw1+ rolc @rw2+ rolc @rw3+ rolc @rw0+d8 rolc @rw1+d8 rolc @rw2+d8 rolc @rw3+d8 rolc @rw4+d8 rolc @rw5+d8 rolc @rw6+d8 rolc @rw7+d8 rolc @rw0+d16 rolc @rw1+d16 rolc @rw2+d16 rolc @rw3+d16 rolc @rw0+rw7 rolc @rw1+rw7 rolc @pc+d16 rolc addr16 rorc r0 rorc r1 rorc r2 rorc r3 rorc r4 rorc r5 rorc r6 rorc r7 rorc @rw0 rorc @rw1 rorc @rw2 rorc @rw3 rorc @rw0+ rorc @rw1+ rorc @rw2+ rorc @rw3+ inc r0 inc r1 inc r2 inc r3 inc r4 inc r5 inc r6 inc r7 inc @rw0 inc @rw1 inc @rw2 inc @rw3 inc @rw0+ inc @rw1+ inc @rw2+ inc @rw3+ dec r0 dec r1 dec r2 dec r3 dec r4 dec r5 dec r6 dec r7 dec @rw0 dec @rw1 dec @rw2 dec @rw3 dec @rw0+ dec @rw1+ dec @rw2+ dec @rw3+ mov a, r0 mov a, r1 mov a, r2 mov a, r3 mov a, r4 mov a, r5 mov a, r6 mov a, r7 mov a, @rw0 mov a, @rw1 mov a, @rw2 mov a, @rw3 mov a, @rw0+ mov a, @rw1+ mov a, @rw2+ mov a, @rw3+ mov r0, a mov r1, a mov r2, a mov r3, a mov r4, a mov r5, a mov r6, a mov r7, a mov @rw0, a mov @rw1, a mov @rw2, a mov @rw3, a mov @rw0+, a mov @rw1+, a mov @rw2+, a mov @rw3+, a movx a, r0 movx a, r1 movx a, r2 movx a, r3 movx a, r4 movx a, r5 movx a, r6 movx a, r7 movx a, @rw0 movx a, @rw1 movx a, @rw2 movx a, @rw3 movx a, @rw0+ movx a, @rw1+ movx a, @rw2+ movx a, @rw3+ xch a, r0 xch a, r1 xch a, r2 xch a, r3 xch a, r4 xch a, r5 xch a, r6 xch a, r7 xch a, @rw0 xch a, @rw1 xch a, @rw2 xch a, @rw3 xch a, @rw0+ xch a, @rw1+ xch a, @rw2+ xch a, @rw3+ rorc @rw0+d8 rorc @rw1+d8 rorc @rw2+d8 rorc @rw3+d8 rorc @rw4+d8 rorc @rw5+d8 rorc @rw6+d8 rorc @rw7+d8 rorc @rw0+d16 rorc @rw1+d16 rorc @rw2+d16 rorc @rw3+d16 rorc @rw0+rw7 rorc @rw1+rw7 rorc @pc+d16 rorc addr16 inc @rw0+d8 inc @rw1+d8 inc @rw2+d8 inc @rw3+d8 inc @rw4+d8 inc @rw5+d8 inc @rw6+d8 inc @rw7+d8 inc @rw0+d16 inc @rw1+d16 inc @rw2+d16 inc @rw3+d16 inc @rw0+rw7 inc @rw1+rw7 inc @pc+d16 inc addr16 dec @rw0+d8 dec @rw1+d8 dec @rw2+d8 dec @rw3+d8 dec @rw4+d8 dec @rw5+d8 dec @rw6+d8 dec @rw7+d8 dec @rw0+d16 dec @rw1+d16 dec @rw2+d16 dec @rw3+d16 dec @rw0+rw7 dec @rw1+rw7 dec @pc+d16 dec addr16 mov a, @rw0+d8 mov a, @rw1+d8 mov a, @rw2+d8 mov a, @rw3+d8 mov a, @rw4+d8 mov a, @rw5+d8 mov a, @rw6+d8 mov a, @rw7+d8 mov a, @rw0+d16 mov a, @rw1+d16 mov a, @rw2+d16 mov a, @rw3+d16 mov a, @rw0+rw7 mov a, @rw1+rw7 mov a, @pc+d16 mov a, addr16 mov @r w0+d8, a mov @r w1+d8, a mov @r w2+d8, a mov @r w3+d8, a mov @r w4+d8, a mov @r w5+d8, a mov @r w6+d8, a mov @r w7+d8, a mov @r w0+d16, a mov @r w1+d16, a mov @r w2+d16, a mov @r w3+d16, a mov @r w0+rw7, a mov @r w1+rw7, a mov @p c+d16, a mov addr16, a movx a, @rw0+d8 movx a, @rw1+d8 movx a, @rw2+d8 movx a, @rw3+d8 movx a, @rw4+d8 movx a, @rw5+d8 movx a, @rw6+d8 movx a, @rw7+d8 movx a, @rw0+d16 movx a, @rw1+d16 movx a, @rw2+d16 movx a, @rw3+d16 movx a, @rw0+rw7 movx a, @rw1+rw7 movx a, @pc+d16 movx a, addr16 xch a, @rw0+d8 xch a, @rw1+d8 xch a, @rw2+d8 xch a, @rw3+d8 xch a, @rw4+d8 xch a, @rw5+d8 xch a, @rw6+d8 xch a, @rw7+d8 xch a, @rw0+d16 xch a, @rw1+d16 xch a, @rw2+d16 xch a, @rw3+d16 xch a, @rw0+rw7 xch a, @rw1+rw7 xch a, @pc+d16 xch a, addr16
532 appendix b instructions MB90560 series table b.9-9 ea instruction map (4) (1st byte = 73 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 jmp @rw0 jmp @rw1 jmp @rw2 jmp @rw3 jmp @rw4 jmp @rw5 jmp @rw6 jmp @rw7 jmp @@rw0 jmp @@rw1 jmp @@rw2 jmp @@rw3 jmp @@rw0+ jmp @@rw1+ jmp @@rw2+ jmp @@rw3+ jmp @@rw0+d8 jmp @@rw1+d8 jmp @@rw2+d8 jmp @@rw3+d8 jmp @@rw4+d8 jmp @@rw5+d8 jmp @@rw6+d8 jmp @@rw7+d8 jmp @@rw0+d16 jmp @@rw1+d16 jmp @@rw2+d16 jmp @@rw3+d16 jmp @@rw0+rw7 jmp @@rw1+rw7 jmp @@pc+d16 jmp @addr16 call @rw0 call @rw1 call @rw2 call @rw3 call @rw4 call @rw5 call @rw6 call @rw7 call @@rw0 call @@rw1 call @@rw2 call @@rw3 call @@rw0+ call @@rw1+ call @@rw2+ call @@rw3+ incw rw0 incw rw1 incw rw2 incw rw3 incw rw4 incw rw5 incw rw6 incw rw7 incw @rw0 incw @rw1 incw @rw2 incw @rw3 incw @rw0+ incw @rw1+ incw @rw2+ incw @rw3+ decw rw0 decw rw1 decw rw2 decw rw3 decw rw4 decw rw5 decw rw6 decw rw7 decw @rw0 decw @rw1 decw @rw2 decw @rw3 decw @rw0+ decw @rw1+ decw @rw2+ decw @rw3+ movw a, rw0 movw a, rw1 movw a, rw2 movw a, rw3 movw a, rw4 movw a, rw5 movw a, rw6 movw a, rw7 movw a, @rw0 movw a, @rw1 movw a, @rw2 movw a, @rw3 movw a, @rw0+ movw a, @rw1+ movw a, @rw2+ movw a, @rw3+ movw rw0, a movw rw1, a movw rw2, a movw rw3, a movw rw4, a movw rw5, a movw rw6, a movw rw7, a movw @rw0, a movw @rw1. a movw @rw2, a movw @rw3, a movw @rw0+, a movw @rw1+, a movw @rw2+, a movw @rw3+, a movw rw0, #16 movw rw1, #16 movw rw2, #16 movw rw3, #16 movw rw4, #16 movw rw5, #16 movw rw6, #16 movw rw7, #16 movw @rw0, #16 movw @rw1, #16 movw @rw2, #16 movw @rw3, #16 movw @ rw0+, #16 movw @ rw1+, #16 movw @ rw2+, #16 movw @ rw3+, #16 xchw a, rw0 xchw a, rw1 xchw a, rw2 xchw a, rw3 xchw a, rw4 xchw a, rw5 xchw a, rw6 xchw a, rw7 xchw a, @rw0 xchw a, @rw1 xchw a, @rw2 xchw a, @rw3 xchw a, @rw0+ xchw a, @rw1+ xchw a, @rw2+ xchw a, @rw3+ call @@rw0+d8 call @@rw1+d8 call @@rw2+d8 call @@rw3+d8 call @@rw4+d8 call @@rw5+d8 call @@rw6+d8 call @@rw7+d8 call @@rw0+d16 call @@rw1+d16 call @@rw2+d16 call @@rw3+d16 call @ @rw0+rw7 call @ @rw1+rw7 call call @addr16 incw @rw0+d8 incw @rw1+d8 incw @rw2+d8 incw @rw3+d8 incw @rw4+d8 incw @rw5+d8 incw @rw6+d8 incw @rw7+d8 incw @rw0+d16 incw @rw1+d16 incw @rw2+d16 incw @rw3+d16 incw @rw0+rw7 incw @rw1+rw7 incw @pc+d16 incw addr16 decw @rw0+d8 decw @rw1+d8 decw @rw2+d8 decw @rw3+d8 decw @rw4+d8 decw @rw5+d8 decw @rw6+d8 decw @rw7+d8 decw @rw0+d16 decw @rw1+d16 decw @rw2+d16 decw @rw3+d16 decw @rw0+rw7 decw @rw1+rw7 decw @pc+d16 decw addr16 movw a, @rw0+d8 movw a, @rw1+d8 movw a, @rw2+d8 movw a, @rw3+d8 movw a, @rw4+d8 movw a, @rw5+d8 movw a, @rw6+d8 movw a, @rw7+d8 movw a, @rw0+d16 movw a, @rw1+d16 movw a, @rw2+d16 movw a, @rw3+d16 movw a, @rw0+rw7 movw a, @rw1+rw7 movw a, @pc+d16 movw a, addr16 movw @r w0+d8, a movw @r w1+d8, a movw @r w2+d8, a movw @r w3+d8, a movw @r w4+d8, a movw @r w5+d8, a movw @r w6+d8, a movw @r w7+d8, a movw @r w0+d16, a movw @r w1+d16, a movw @r w2+d16, a movw @r w3+d16, a movw @r w0+rw7, a movw @r w1+rw7, a movw @p c+d16, a movw addr16, a movw @rw 0+d8, #16 movw @rw 1+d8, #16 movw @rw 2+d8, #16 movw @rw 3+d8, #16 movw @rw 4+d8, #16 movw @rw 5+d8, #16 movw @rw 6+d8, #16 movw @rw 7+d8, #16 movw@rw0 +d16, #16 movw@rw1 +d16, #16 movw@ rw2 +d16, #16 movw @rw3 +d16, #16 movw@rw0 +rw7, #16 movw @rw1 +rw7, #16 movw @pc +d16, #16 movw ad dr16, #16 xchw a, @rw0+d8 xchw a, @rw1+d8 xchw a, @rw2+d8 xchw a, @rw3+d8 xchw a, @rw4+d8 xchw a, @rw5+d8 xchw a, @rw6+d8 xchw a, @rw7+d8 xchw a, @rw0+d16 xchw a, @rw1+d16 xchw a, @rw2+d16 xchw a, @rw3+d16 xchw a, @rw0+rw7 xchw a, @rw1+rw7 xchw a, @pc+d16 xchw a, addr16 @@pc+d16
MB90560 series appendix b instructions 533 table b.9-10 ea instruction map (5) (1st byte = 74 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 add a, r0 add a, r1 add a, r2 add a, r3 add a, r4 add a, r5 add a, r6 add a, r7 add a, @rw0 add a, @rw1 add a, @rw2 add a, @rw3 add a, @rw0+ add a, @rw1+ add a, @rw2+ add a, @rw3+ add a, @rw0+d8 add a, @rw1+d8 add a, @rw2+d8 add a, @rw3+d8 add a, @rw4+d8 add a, @rw5+d8 add a, @rw6+d8 add a, @rw7+d8 add a, @rw0+d16 add a, @rw1+d16 add a, @rw2+d16 add a, @rw3+d16 add a, @rw0+rw7 add a, @rw1+rw7 add a, @pc+d16 add a, addr16 sub a, r0 sub a, r1 sub a, r2 sub a, r3 sub a, r4 sub a, r5 sub a, r6 sub a, r7 sub a, @rw0 sub a, @rw1 sub a, @rw2 sub a, @rw3 sub a, @rw0+ sub a, @rw1+ sub a, @rw2+ sub a, @rw3+ addc a, r0 addc a, r1 addc a, r2 addc a, r3 addc a, r4 addc a, r5 addc a, r6 addc a. r7 addc a, @rw0 addc a, @rw1 addc a, @rw2 addc a, @rw3 addc a, @rw0+ addc a, @rw1+ addc a, @rw2+ addc a, @rw3+ cmp a, r0 cmp a, r1 cmp a, r2 cmp a, r3 cmp a, r4 cmp a, r5 cmp a, r6 cmp a, r7 cmp a, @rw0 cmp a, @rw1 cmp a, @rw2 cmp a, @rw3 cmp a, @rw0+ cmp a, @rw1+ cmp a, @rw2+ cmp a, @rw3+ and a, r0 and a, r1 and a, r2 and a, r3 and a, r4 and a, r5 and a, r6 and a, r7 and a, @rw0 and a, @rw1 and a, @rw2 and a, @rw3 and a, @rw0+ and a, @rw1+ and a, @rw2+ and a, @rw3+ or a, r0 or a, r1 or a, r2 or a, r3 or a, r4 or a, r5 or a, r6 or a, r7 or a, @rw0 or a, @rw1 or a, @rw2 or a, @rw3 or a, @rw0+ or a, @rw1+ or a, @rw2+ or a, @rw3+ xor a, r0 xor a, r1 xor a, r2 xor a, r3 xor a, r4 xor a, r5 xor a, r6 xor a, r7 xor a, @rw0 xor a, @rw1 xor a, @rw2 xor a, @rw3 xor a, @rw0+ xor a, @rw1+ xor a, @rw2+ xor a, @rw3+ dbnz r0, r dbnz r1, r dbnz r2, r dbnz r3, r dbnz r4, r dbnz r5, r dbnz r6, r dbnz r7, r dbnz @rw0, r dbnz @rw1, r dbnz @rw2, r dbnz @rw3, r dbnz @rw0+, r dbnz @rw1+, r dbnz @rw2+, r dbnz @rw3+, r sub a, @rw0+d8 sub a, @rw1+d8 sub a, @rw2+d8 sub a, @rw3+d8 sub a, @rw4+d8 sub a, @rw5+d8 sub a, @rw6+d8 sub a, @rw7+d8 sub a, @rw0+d16 sub a, @rw1+d16 sub a, @rw2+d16 sub a, @rw3+d16 sub a, @rw0+rw7 sub a, @rw1+rw7 sub a, sub a, addr16 addc a, @rw0+d8 addc a, @rw1+d8 addc a, @rw2+d8 addc a, @rw3+d8 addc a, @rw4+d8 addc a, @rw5+d8 addc a, @rw6+d8 addc a, @rw7+d8 addc a, @rw0+d16 addc a, @rw1+d16 addc a, @rw2+d16 addc a, @rw3+d16 addc a, @rw0+rw7 addc a, @rw1+rw7 addc a, @pc+d16 addc a, addr16 cmp a, @rw0+d8 cmp a, @rw1+d8 cmp a, @rw2+d8 cmp a, @rw3+d8 cmp a, @rw4+d8 cmp a, @rw5+d8 cmp a, @rw6+d8 cmp a, @rw7+d8 cmp a, @rw0+d16 cmp a, @rw1+d16 cmp a, @rw2+d16 cmp a, @rw3+d16 cmp a, @rw0+rw7 cmp a, @rw1+rw7 cmp a, @pc+d16 cmp a, addr16 and a, @rw0+d8 and a, @rw1+d8 and a, @rw2+d8 and a, @rw3+d8 and a, @rw4+d8 and a, @rw5+d8 and a, @rw6+d8 and a, @rw7+d8 and a, @rw0+d16 and a, @rw1+d16 and a, @rw2+d16 and a, @rw3+d16 and a, @rw0+rw7 and a, @rw1+rw7 and a, @pc+d16 and a, addr16 or a, @rw0+d8 or a, @rw1+d8 or a, @rw2+d8 or a, @rw3+d8 or a, @rw4+d8 or a, @rw5+d8 or a, @rw6+d8 or a, @rw7+d8 or a, @rw0+d16 or a, @rw1+d16 or a, @rw2+d16 or a, @rw3+d16 or a, @rw0+rw7 or a, @rw1+rw7 or a, @ pc+d16 or a, addr16 xor a, @rw0+d8 xor a, @rw1+d8 xor a, @rw2+d8 xor a, @rw3+d8 xor a, @rw4+d8 xor a, @rw5+d8 xor a, @rw6+d8 xor a, @rw7+d8 xor a, @rw0+d16 xor a, @rw1+d16 xor a, @rw2+d16 xor a, @rw3+d16 xor a, @rw0+rw7 xor a, @rw1+rw7 xor a, @pc+d16 xor a, addr16 dbnz @ rw0+d8, r dbnz @ rw1+d8, r dbnz @ rw2+d8, r dbnz @ rw3+d8, r dbnz @ rw4+d8, r dbnz @ rw5+d8, r dbnz @ rw6+d8, r dbnz @ rw7+d8, r dbnz rw0+d16, r dbnz rw1+d16, r dbnz rw2+d16, r dbnz rw3+d16, r dbnz rw0+rw7, r dbnz rw1+rw7, r dbnz @ pc+d16, r dbnz @ addr16, r @pc+d16
534 appendix b instructions MB90560 series table b.9-11 ea instruction map (6) (1st byte = 75 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 add r0, a add r1, a add r2, a add r3, a add r4, a add r5, a add r6, a add r7, a add @rw0, a add @rw1, a add @rw2, a add @rw3, a add @rw0+, a add @rw1+, a add @rw2+, a add @rw3+, a w0+d8, a w1+d8, a w2+d8, a w3+d8, a w4+d8, a w5+d8, a w6+d8, a w7+d8, a w0+d16, a w1+d16, a rw2+d16, a rw3+d16, a add @r w0+rw7, a add @r w1+rw7, a c+d16, a add addr16, a sub r0, a sub r1, a sub r2, a sub r3, a sub r4, a sub r5, a sub r6, a sub r7, a sub @rw0, a sub @rw1, a sub @rw2, a sub @rw3, a sub @rw0+, a sub @rw1+, a sub @rw2+, a sub @rw3+, a subc a, r0 subc a, r1 subc a, r2 subc a, r3 subc a, r4 subc a, r5 subc a, r6 subc a, r7 subc a, @rw0 subc a, @rw1 subc a, @rw2 subc a, @rw3 subc a, @rw0+ subc a, @rw1+ subc a, @rw2+ subc a, @rw3+ neg r0 neg r1 neg r2 neg r3 neg r4 neg r5 neg r6 neg r7 neg @rw0 neg @rw1 neg @rw2 neg @rw3 neg @rw0+ neg @rw1+ neg @rw2+ neg @rw3+ and r0, a and r1, a and r2, a and r3, a and r4, a and r5, a and r6, a and r7, a and @rw0, a and @rw1, a and @rw2, a and @rw3, a and @rw0+, a and @rw1+, a and @rw2+, a and @rw3+, a or r0, a or r1, a or r2, a or r3, a or r4, a or r5, a or r6, a or r7, a or @rw0, a or @rw1, a or @rw2, a or @rw3, a or @rw0+, a or @rw1+, a or @rw2+, a or @rw3+, a xor r0, a xor r1, a xor r2, a xor r3, a xor r4, a xor r5, a xor r6, a xor r7, a xor @rw0, a xor @rw1, a xor @rw2, a xor @rw3, a xor @rw0+, a xor @rw1+, a xor @rw2+, a xor @rw3+, a not r0 not r1 not r2 not r3 not r4 not r5 not r6 not r7 not @rw0 not @rw1 not @rw2 not @rw3 not @rw0+ not @rw1+ not @rw2+ not @rw3+ sub @r w0+d8, a sub @r w1+d8, a sub @r w2+d8, a sub @r w3+d8, a sub @r w4+d8, a sub @r w5+d8, a sub @r w6+d8, a sub @r w7+d8, a sub @r w0+d16, a sub @r w1+d16, a sub @r w2+d16, a sub @r w3+d16, a sub @r w0+rw7, a sub @r w1+rw7, a sub @p sub addr16, a subc a, @rw0+d8 subc a, @rw1+d8 subc a, @rw2+d8 subc a, @rw3+d8 subc a, @rw4+d8 subc a, @rw5+d8 subc a, @rw6+d8 subc a, @rw7+d8 subc a, @rw0+d16 subc a, @rw1+d16 subc a, @rw2+d16 subc a, @rw3+d16 subc a, @rw0+rw7 subc a, @rw1+rw7 subc a, @pc+d16 subc a, addr16 neg @rw0+d8 neg @rw1+d8 neg @rw2+d8 neg @rw3+d8 neg @rw4+d8 neg @rw5+d8 neg @rw6+d8 neg @rw7+d8 neg @rw0+d16 neg @rw1+d16 neg @rw2+d16 neg @rw3+d16 neg @rw0+rw7 neg @rw1+rw7 neg @pc+d16 neg addr16 and @r w0+d8, a and @r w1+d8, a and @r w2+d8, a and @r w3+d8, a and @r w4+d8, a and @r w5+d8, a and @r w6+d8, a and @r w7+d8, a and @r w0+d16, a and @r w1+d16, a and @r w2+d16, a and @r w3+d16, a and @r w0+rw7, a and @r w1+rw7, a and @p c+d16, a and addr16, a or @rw0+d8, a or @rw1+d8, a or @rw2+d8, a or @rw3+d8, a or @rw4+d8, a or @rw5+d8, a or @rw6+d8, a or @rw7+d8, a or @rw0+d16, a or @rw1+d16, a or @rw2+d16, a or @rw3+d16, a or @r w0+rw7, a or @r w1+rw7, a or @pc+d16, a or addr16, a w0+d8, a w1+d8, a w2+d8, a w3+d8, a w4+d8, a w5+d8, a w6+d8, a w7+d8, a w0+d16, a w1+d16, a w2+d16, a w3+d16, a xor @r w0+rw7, a xor @r w1+rw7, a c+d16, a xor addr16, a not @rw0+d8 not @rw1+d8 not @rw2+d8 not @rw3+d8 not @rw4+d8 not @rw5+d8 not @rw6+d8 not @rw7+d8 not @rw0+d16 not @rw1+d16 not @rw2+d16 not @rw3+d16 not @rw0+rw7 not @rw1+rw7 not @pc+d16 not addr16 c+d16, a add @r add @r add @r add @r add @r add @r add @r add @r add @r add @r add @r add @r add @p xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @r xor @p
MB90560 series appendix b instructions 535 table b.9-12 ea instruction map (7) (1st byte = 76 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 addw a, rw0 addw a, rw1 addw a, rw2 addw a, rw3 addw a, rw4 addw a, rw5 addw a, rw6 addw a, rw7 addw a, @rw0 addw a, @rw1 addw a, @rw2 addw a, @rw3 addw a, @rw0+ addw a, @rw1+ addw a, @rw2+ addw a, @rw3+ addw a, @rw0+d8 addw a, @rw1+d8 addw a, @rw2+d8 addw a, @rw3+d8 addw a, @rw4+d8 addw a, @rw5+d8 addw a, @rw6+d8 addw a, @rw7+d8 addw a, @rw0+d16 addw a, @rw1+d16 addw a, @rw2+d16 addw a, @rw3+d16 addw a, @rw0+rw7 addw a, @rw1+rw7 addw a, @pc+d16 addw a, addr16 subw a, rw0 subw a, rw1 subw a, rw2 subw a, rw3 subw a, rw4 subw a, rw5 subw a, rw6 subw a, rw7 subw a, @rw0 subw a, @rw1 subw a, @rw2 subw a, @rw3 subw a, @rw0+ subw a, @rw1+ subw a, @rw2+ subw a, @rw3+ addcw a, rw0 addcw a, rw1 addcw a, rw2 addcw a, rw3 addcw a, rw4 addcw a, rw5 addcw a, rw6 addcw a, rw7 addcw a, @rw0 addcw a, @rw1 addcw a, @rw2 addcw a, @rw3 addcw a, @rw0+ addcw a, @rw1+ addcw a, @rw2+ addcw a, @rw3+ cmpw a, rw0 cmpw a, rw1 cmpw a, rw2 cmpw a, rw3 cmpw a, rw4 cmpw a, rw5 cmpw a, rw6 cmpw a, rw7 cmpw a, @rw0 cmpw a, @rw1 cmpw a, @rw2 cmpw a, @rw3 cmpw a, @rw0+ cmpw a, @rw1+ cmpw a, @rw2+ cmpw a, @rw3+ andw a, rw0 andw a, rw1 andw a, rw2 andw a, rw3 andw a, rw4 andw a, rw5 andw a, rw6 andw a, rw7 andw a, @rw0 andw a, @rw1 andw a, @rw2 andw a, @rw3 andw a, @rw0+ andw a, @rw1+ andw a, @rw2+ andw a, @rw3+ orw a, rw0 orw a, rw1 orw a, rw2 orw a, rw3 orw a, rw4 orw a, rw5 orw a, rw6 orw a, rw7 orw a, @rw0 orw a, @rw1 orw a, @rw2 orw a, @rw3 orw a, @rw0+ orw a, @rw1+ orw a, @rw2+ orw a, @rw3+ xorw a, rw0 xorw a, rw1 xorw a, rw2 xorw a, rw3 xorw a, rw4 xorw a, rw5 xorw a, rw6 xorw a, rw7 xorw a, @rw0 xorw a, @rw1 xorw a, @rw2 xorw a, @rw3 xorw a, @rw0+ xorw a, @rw1+ xorw a, @rw2+ xorw a, @rw3+ dwbnz rw0, r dwbnz rw1, r dwbnz rw2, r dwbnz rw3, r dwbnz rw4, r dwbnz rw5, r dwbnz rw6, r dwbnz rw7, r dwbnz @rw0, r dwbnz @rw1, r dwbnz @rw2, r dwbnz @rw3, r dwbnz @rw0+, r dwbnz @rw1+, r dwbnz @rw2+, r dwbnz @rw3+, r subw a, @rw0+d8 subw a, @rw1+d8 subw a, @rw2+d8 subw a, @rw3+d8 subw a, @rw4+d8 subw a, @rw5+d8 subw a, @rw6+d8 subw a, @rw7+d8 subw a, @rw0+d16 subw a, @rw1+d16 subw a, @rw2+d16 subw a, @rw3+d16 subw a, @rw0+rw7 subw a, @rw1+rw7 subw a, subw a, addr16 addcw a, @rw0+d8 addcw a, @rw1+d8 addcw a, @rw2+d8 addcw a, @rw3+d8 addcw a, @rw4+d8 addcw a, @rw5+d8 addcw a, @rw6+d8 addcw a, @rw7+d8 addcw a, @rw0+d16 addcw a, @rw1+d16 addcw a, @rw2+d16 addcw a, @rw3+d16 addcw a, @rw0+rw7 addcw a, @rw1+rw7 addcw a, @pc+d16 addcw a, addr16 cmpw a, @rw0+d8 cmpw a, @rw1+d8 cmpw a, @rw2+d8 cmpw a, @rw3+d8 cmpw a, @rw4+d8 cmpw a, @rw5+d8 cmpw a, @rw6+d8 cmpw a, @rw7+d8 cmpw a, @rw0+d16 cmpw a, @rw1+d16 cmpw a, @rw2+d16 cmpw a, @rw3+d16 cmpw a, @rw0+rw7 cmpw a, @rw1+rw7 cmpw a, @pc+d16 cmpw a, addr16 andw a, @rw0+d8 andw a, @rw1+d8 andw a, @rw2+d8 andw a, @rw3+d8 andw a, @rw4+d8 andw a, @rw5+d8 andw a, @rw6+d8 andw a, @rw7+d8 andw a, @rw0+d16 andw a, @rw1+d16 andw a, @rw2+d16 andw a, @rw3+d16 andw a, @rw0+rw7 andw a, @rw1+rw7 andw a, @pc+d16 andw a, addr16 orw a, @rw0+d8 orw a, @rw1+d8 orw a, @rw2+d8 orw a, @rw3+d8 orw a, @rw4+d8 orw a, @rw5+d8 orw a, @rw6+d8 orw a, @rw7+d8 orw a, @rw0+d16 orw a, @rw1+d16 orw a, @rw2+d16 orw a, @rw3+d16 orw a, @rw0+rw7 orw a, @rw1+rw7 orw a, @ pc+d16 orw a, addr16 xorw a, @rw0+d8 xorw a, @rw1+d8 xorw a, @rw2+d8 xorw a, @rw3+d8 xorw a, @rw4+d8 xorw a, @rw5+d8 xorw a, @rw6+d8 xorw a, @rw7+d8 xorw a, @rw0+d16 xorw a, @rw1+d16 xorw a, @rw2+d16 xorw a, @rw3+d16 xorw a, @rw0+rw7 xorw a, @rw1+rw7 xorw a, @pc+d16 xorw a, addr16 dwbnz @ rw0+d8, r dwbnz @ rw1+d8, r dwbnz @ rw2+d8, r dwbnz @ rw3+d8, r dwbnz @ rw4+d8, r dwbnz @ rw5+d8, r dwbnz @ rw6+d8, r dwbnz @ rw7+d8, r dwbnz @r w0+d16, r dwbnz @r w1+d16, r dwbnz @r w2+d16, r dwbnz @r w3+d16, r dwbnz @r w0+rw7, r dwbnz @r w1+rw7, r dwbnz @ pc+d16, r dwbnz addr16, r @pc+d16
536 appendix b instructions MB90560 series table b.9-13 ea instruction map (8) (1st byte = 77 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 addw rw0, a addw rw1, a addw rw2, a addw rw3, a addw rw4, a addw rw5, a addw rw6, a addw rw7, a addw @rw0, a addw @rw1, a addw @rw2, a addw @rw3, a addw @rw0+, a addw @rw1+, a addw @rw2+, a addw @rw3+, a addw @r w0+d8, a addw @r w1+d8, a addw @r w2+d8, a addw @r w3+d8, a addw @r w4+d8, a addw @r w5+d8, a addw @r w6+d8, a addw @r w7+d8, a addw @r w0+d16, a addw @r w1+d16, a addw @r w2+d16, a addw @r w3+d16, a addw @r w0+rw7 addw @r w1+rw7 addw @p c+d16, a addw addr16, a subw rw0, a subw rw1, a subw rw2, a subw rw3, a subw rw4, a subw rw5, a subw rw6, a subw rw7, a subw @rw0, a subw @rw1, a subw @rw2, a subw @rw3, a subw @rw0+, a subw @rw1+, a subw @rw2+, a subw @rw3+, a subcw a, rw0 subcw a, rw1 subcw a, rw2 subcw a, rw3 subcw a, rw4 subcw a, rw5 subcw a, rw6 subcw a,rw7 subcw a, @rw0 subcw a, @rw1 subcw a, @rw2 subcw a, @rw3 subcw a, @rw0+ subcw a, @rw1+ subcw a, @rw2+ subcw a, @rw3+ negw rw0 negw rw1 negw rw2 negw rw3 negw rw4 negw rw5 negw rw6 negw rw7 negw @rw0 negw @rw1 negw @rw2 negw @rw3 negw @rw0+ negw @rw1+ negw @rw2+ negw @rw3+ andw rw0, a andw rw1, a andw rw2, a andw rw3, a andw rw4, a andw rw5, a andw rw6, a andw rw7, a andw @rw0, a andw @rw1, a andw @rw2, a andw @rw3, a andw @rw0+, a andw @rw1+, a andw @rw2+, a andw @rw3+, a orw rw0, a orw rw1, a owr rw2, a orw rw3, a orw rw4, a orw rw5, a orw rw6, a orw rw7, a orw @rw0, a orw @rw1, a orw @rw2, a orw @rw3, a orw @rw0+, a orw @rw1+, a orw @rw2+, a orw @rw3+, a xorw rw0, a xorw rw1, a xorw rw2, a xorw rw3, a xorw rw4, a xorw rw5, a xorw rw6, a xorw rw7, a xorw @rw0, a xorw @rw1, a xorw @rw2, a xorw @rw3, a xorw @rw0+, a xorw @rw1+, a xorw @rw2+, a xorw @rw3+, a notw rw0 notw rw1 notw rw2 notw rw3 notw rw4 notw rw5 notw rw6 notw rw7 notw @rw0 notw @rw1 notw @rw2 notw @rw3 notw @rw0+ notw @rw1+ notw @rw2+ notw @rw3+ subw @r w0+d8, a subw @r w1+d8, a subw @r w2+d8, a subw @r w3+d8, a subw @r w4+d8, a subw @r w5+d8, a subw @r w6+d8, a subw @r w7+d8, a subw @r w0+d16, a subw @r w1+d16, a subw @r w2+d16, a subw @r w3+d16, a subw @r w0+rw7, a subw @r w1+rw7, a subw subw addr16, a subcw a, @rw0+d8 subcw a, @rw1+d8 subcw a, @rw2+d8 subcw a, @rw3+d8 subcw a, @rw4+d8 subcw a, @rw5+d8 subcw a, @rw6+d8 subcw a, @rw7+d8 subcw a, @rw0+d16 subcw a, @rw1+d16 subcw a, @rw2+d16 subcw a, @rw3+d16 subcw a, @rw0+rw7 subcw a, @rw1+rw7 subcw a, @pc+d16 subcw a, addr16 negw @rw0+d8 negw @rw1+d8 negw @rw2+d8 negw @rw3+d8 negw @rw4+d8 negw @rw5+d8 negw @rw6+d8 negw @rw7+d8 negw @rw0+d16 negw @rw1+d16 negw @rw2+d16 negw @rw3+d16 negw @rw0+rw7 negw @rw1+rw7 negw @pc+d16 negw addr16 andw @r w0+d8, a andw @r w1+d8, a andw @r w2+d8, a andw @r w3+d8, a andw @r w4+d8, a andw @r w5+d8, a andw @r w6+d8, a andw @r w7+d8, a andw @r w0+d16, a andw @r w1+d16, a andw @r w2+d16, a andw @r w3+d16, a andw @r w0+rw7, a andw @r w1+rw7, a andw @p c+d16, a andw addr16, a orw @r w0+d8, a orw @r w1+d8, a orw @r w2+d8, a orw @r w3+d8, a orw @r w4+d8, a orw @r w5+d8, a orw @r w6+d8, a orw @r w7+d8, a orw @r w0+d16, a orw @r w1+d16, a orw @r w2+d16, a orw @r w3+d16, a orw @r w0+rw7, a orw @r w1+rw7, a c+d16, a orw addr16, a xorw @r w0+d8, a xorw @r w1+d8, a xorw @r w2+d8, a xorw @r w3+d8, a xorw @r w4+d8, a xorw @r w5+d8, a xorw @r w6+d8, a xorw @r w7+d8, a xorw @r w0+d16, a xorw @r w1+d16, a xorw @r w2+d16, a xorw @r w3+d16, a xorw @r w0+rw7, a xorw @r w1+rw7, a xorw @p c+d16, a xorw addr16, a notw @rw0+d8 notw @rw1+d8 notw @rw2+d8 notw @rw3+d8 notw @rw4+d8 notw @rw5+d8 notw @rw6+d8 notw @rw7+d8 notw @rw0+d16 notw @rw1+d16 notw @rw2+d16 notw @rw3+d16 notw @rw0+rw7 notw @rw1+rw7 notw @pc+d16 notw addr16 @pc+d16, a orw @p
MB90560 series appendix b instructions 537 table b.9-14 ea instruction map (9) (1st byte = 78 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 mulu a, r0 mulu a, r1 mulu a, r2 mulu a, r3 mulu a, r4 mulu a, r5 mulu a, r6 mulu a, r7 mulu a, @rw0 mulu a, @rw1 mulu a, @rw2 mulu a, @rw3 mulu a, @rw0+ mulu a, @rw1+ mulu a, @rw2+ mulu a, @rw3+ mulu a, @rw0+d8 mulu a, @rw1+d8 mulu a, @rw2+d8 mulu a, @rw3+d8 mulu a, @rw4+d8 mulu a, @rw5+d8 mulu a, @rw6+d8 mulu a, @rw7+d8 mulu a, @rw0+d16 mulu a, @rw1+d16 mulu a, @rw2+d16 mulu a, @rw3+d16 mulu a, @rw0+rw7 mulu a, @rw1+rw7 mulu a, @pc+d16 mulu a, addr16 muluw a, rw0 muluw a, rw1 muluw a, rw2 muluw a, rw3 muluw a, rw4 muluw a, rw5 muluw a, rw6 muluw a, rw7 muluw a, @rw0 muluw a, @rw1 muluw a, @rw2 muluw a, @rw3 muluw a, @rw0+ muluw a, @rw1+ muluw a, @rw2+ muluw a, @rw3+ divu a, r0 divu a, r1 divu a, r2 divu a, r3 divu a, r4 divu a, r5 divu a, r6 divu a, r7 divu a, @rw0 divu a, @rw1 divu a, @rw2 divu a, @rw3 divu a, @rw0+ divu a, @rw1+ divu a, @rw2+ divu a, @rw3+ divuw a, rw0 divuw a, rw1 divuw a, rw2 divuw a, rw3 divuw a, rw4 divuw a, rw5 divuw a, rw6 divuw a, rw7 divuw a, @rw0 divuw a, @rw1 divuw a, @rw2 divuw a, @rw3 divuw a, @rw0+ divuw a, @rw1+ divuw a, @rw2+ divuw a, @rw3+ muluw a, @rw0+d8 muluw a, @rw1+d8 muluw a, @rw2+d8 muluw a, @rw3+d8 muluw a, @rw4+d8 muluw a, @rw5+d8 muluw a, @rw6+d8 muluw a, @rw7+d8 muluw a, @rw0+d16 muluw a, @rw1+d16 muluw a, @rw2+d16 muluw a, @rw3+d16 muluw a, @rw0+rw7 muluw a, @rw1+rw7 muluw a, muluw a, addr16 divu a, @rw0+d8 divu a, @rw1+d8 divu a, @rw2+d8 divu a, @rw3+d8 divu a, @rw4+d8 divu a, @rw5+d8 divu a, @rw6+d8 divu a, @rw7+d8 divu a, @rw0+d16 divu a, @rw1+d16 divu a, @rw2+d16 divu a, @rw3+d16 divu a, @rw0+rw7 divu a, @rw1+rw7 divu a, @pc+d16 divu a, addr16 divuw a, @rw0+d8 divuw a, @rw1+d8 divuw a, @rw2+d8 divuw a, @rw3+d8 divuw a, @rw4+d8 divuw a, @rw5+d8 divuw a, @rw6+d8 divuw a, @rw7+d8 divuw a, @rw0+d16 divuw a, @rw1+d16 divuw a, @rw2+d16 divuw a, @rw3+d16 divuw a, @rw0+rw7 divuw a, @rw1+rw7 divuw a, @ pc+d16 divuw a, addr16 @pc+d16 mul a, r0 mul a, r1 mul a, r2 mul a, r3 mul a, r4 mul a, r5 mul a, r6 mul a, r7 mul a, @rw0 mul a, @rw1 mul a, @rw2 mul a, @rw3 mul a, @rw0+ mul a, @rw1+ mul a, @rw2+ mul a, @rw3+ mul a, @rw0+d8 mul a, @rw1+d8 mul a, @rw2+d8 mul a, @rw3+d8 mul a, @rw4+d8 mul a, @rw5+d8 mul a, @rw6+d8 mul a, @rw7+d8 mul a, @rw0+d16 mul a, @rw1+d16 mul a, @rw2+d16 mul a, @rw3+d16 mul a, @rw0+rw7 mul a, @rw1+rw7 mul a, @pc+d16 mul a, addr16 mulw a, rw0 mulw a, rw1 mulw a, rw2 mulw a, rw3 mulw a, rw4 mulw a, rw5 mulw a, rw6 mulw a, rw7 mulw a, @rw0 mulw a, @rw1 mulw a, @rw2 mulw a, @rw3 mulw a, @rw0+ mulw a, @rw1+ mulw a, @rw2+ mulw a, @rw3+ mulw a, @rw0+d8 mulw a, @rw1+d8 mulw a, @rw2+d8 mulw a, @rw3+d8 mulw a, @rw4+d8 mulw a, @rw5+d8 mulw a, @rw6+d8 mulw a, @rw7+d8 mulw a, @rw0+d16 mulw a, @rw1+d16 mulw a, @rw2+d16 mulw a, @rw3+d16 mulw a, @rw0+rw7 mulw a, @rw1+rw7 mulw a, mulw a, addr16 @pc+d16 div a, r0 div a, r1 div a, r2 div a, r3 div a, r4 div a, r5 div a, r6 div a, r7 div a, @rw0 div a, @rw1 div a, @rw2 div a, @rw3 div a, @rw0+ div a, @rw1+ div a, @rw2+ div a, @rw3+ div a, @rw0+d8 div a, @rw1+d8 div a, @rw2+d8 div a, @rw3+d8 div a, @rw4+d8 div a, @rw5+d8 div a, @rw6+d8 div a, @rw7+d8 div a, @rw0+d16 div a, @rw1+d16 div a, @rw2+d16 div a, @rw3+d16 div a, @rw0+rw7 div a, @rw1+rw7 div a, @pc+d16 div a, addr16 divw a, rw0 divw a, rw1 divw a, rw2 divw a, rw3 divw a, rw4 divw a, rw5 divw a, rw6 divw a, rw7 divw a, @rw0 divw a, @rw1 divw a, @rw2 divw a, @rw3 divw a, @rw0+ divw a, @rw1+ divw a, @rw2+ divw a, @rw3+ divw a, @rw0+d8 divw a, @rw1+d8 divw a, @rw2+d8 divw a, @rw3+d8 divw a, @rw4+d8 divw a, @rw5+d8 divw a, @rw6+d8 divw a, @rw7+d8 divw a, @rw0+d16 divw a, @rw1+d16 divw a, @rw2+d16 divw a, @rw3+d16 divw a, @rw0+rw7 divw a, @rw1+rw7 divw a, @ pc+d16 divw a, addr16
538 appendix b instructions MB90560 series table b.9-15 movea rwi,ea instruction map (1st byte = 79 h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 movea rw0, rw0 movea rw0, rw1 movea rw0, rw2 movea rw0, rw3 movea rw0, rw4 movea rw0, rw5 movea rw0, rw6 movea rw0, rw7 movea rw0, @rw0 movea rw0, @rw1 movea rw0, @rw2 movea rw0, @rw3 movea r w0, @rw0+ movea r w0, @rw1+ movea r w0, @rw2+ movea r w0, @rw3+ movea rw0, @rw0+d8 movea rw0, @rw1+d8 movea rw0, @rw2+d8 movea rw0, @rw3+d8 movea rw0, @rw4+d8 movea rw0, @rw5+d8 movea rw0, @rw6+d8 movea rw0, @rw7+d8 movea rw0, @rw0+d16 movea rw0, @rw1+d16 movea rw0, @rw2+d16 movea rw0, @rw3+d16 movea rw0, @rw0+rw7 movea rw0, @rw1+rw7 movea rw0, @pc+d16 movea rw0, addr16 movea rw1, rw0 movea rw1, rw1 movea rw1, rw2 movea rw1, rw3 movea rw1, rw4 movea rw1, rw5 movea rw1, rw6 movea rw1, rw7 movea rw1, @rw0 movea rw1, @rw1 movea rw1, @rw2 movea rw1, @rw3 movea r w1, @rw0+ movea r w1, @rw1+ movea r w1, @rw2+ movea r w1, @rw3+ movea rw2, rw0 movea rw2, rw1 movea rw2, rw2 movea rw2, rw3 movea rw2, rw4 movea rw2, rw5 movea rw2, rw6 movea rw2, rw7 movea rw2, @rw0 movea rw2, @rw1 movea rw2, @rw2 movea rw2, @rw3 movea r w2, @rw0+ movea r w2, @rw1+ movea r w2, @rw2+ movea r w2, @rw3+ movea rw3, rw0 movea rw3, rw1 movea rw3, rw2 movea rw3, rw3 movea rw3, rw4 movea rw3, rw5 movea rw3, rw6 movea rw3, rw7 movea rw3, @rw0 movea rw3, @rw1 movea rw3, @rw2 movea rw3, @rw3 movea r w3, @rw0+ movea r w3, @rw1+ movea r w3, @rw2+ movea r w3, @rw3+ movea rw4, rw0 movea rw4, rw1 movea rw4, rw2 movea rw4, rw3 movea rw4, rw4 movea rw4, rw5 movea rw4, rw6 movea rw4, rw7 movea rw4, @rw0 movea rw4, @rw1 movea rw4, @rw2 movea rw4, @rw3 movea r w4, @rw0+ movea r w4, @rw1+ movea r w4, @rw2+ movea r w4, @rw3+ movea rw5, rw0 movea rw5, rw1 movea rw5, rw2 movea rw5, rw3 movea rw5, rw4 movea rw5, rw5 movea rw5, rw6 movea rw5, rw7 movea rw5, @rw0 movea rw5, @rw1 movea rw5, @rw2 movea rw5, @rw3 movea r w5, @rw0+ movea r w5, @rw1+ movea r w5, @rw2+ movea r w5, @rw3+ movea rw6, rw0 movea rw6, rw1 movea rw6, rw2 movea rw6, rw3 movea rw6, rw4 movea rw6, rw5 movea rw6, rw6 movea rw6, rw7 movea rw6, @rw0 movea rw6, @rw1 movea rw6, @rw2 movea rw6, @rw3 movea r w6, @rw0+ movea r w6, @rw1+ movea r w6, @rw2+ movea w6, @rw3+ movea rw7, rw0 movea rw7, rw1 movea rw7, rw2 movea rw7, rw3 movea rw7, rw4 movea rw7, rw5 movea rw7, rw6 movea rw7, rw7 movea rw7, @rw0 movea rw7, @rw1 movea rw7, @rw2 movea rw7, @rw3 movea r w7, @rw0+ movea r w7, @rw1+ movea r w7, @rw2+ movea r w7, @rw3+ movea rw1, @rw0+d8 movea rw1, @rw1+d8 movea rw1, @rw2+d8 movea rw1, @rw3+d8 movea rw1, @rw4+d8 movea rw1, @rw5+d8 movea rw1, @rw6+d8 movea rw1, @rw7+d8 movea rw1, @rw0+d16 movea rw1, @rw1+d16 movea rw1, @rw2+d16 movea rw1, @rw3+d16 movea rw1, @rw0+rw7 movea rw1, @rw1+rw7 movea rw1, movea rw1, addr16 movea rw2, @rw0+d8 movea rw2, @rw1+d8 movea rw2, @rw2+d8 movea rw2, @rw3+d8 movea rw2, @rw4+d8 movea rw2, @rw5+d8 movea rw2, @rw6+d8 movea rw2, @rw7+d8 movea rw2, @rw0+d16 movea rw2, @rw1+d16 movea rw2, @rw2+d16 movea rw2, @rw3+d16 movea rw2, @rw0+rw7 movea rw2, @rw1+rw7 movea rw2, @pc+d16 movea rw2, addr16 movea rw3, @rw0+d8 movea rw3, @rw1+d8 movea rw3, @rw2+d8 movea rw3, @rw3+d8 movea rw3, @rw4+d8 movea rw3, @rw5+d8 movea rw3, @rw6+d8 movea rw3, @rw7+d8 movea rw3, @rw0+d16 movea rw3, @rw1+d16 movea rw3, @rw2+d16 movea rw3, @rw3+d16 movea rw3, @rw0+rw7 movea rw3, @rw1+rw7 movea rw3, @pc+d16 movea rw3, addr16 movea rw4, @rw0+d8 movea rw4, @rw1+d8 movea rw4, @rw2+d8 movea rw4, @rw3+d8 movea rw4, @rw4+d8 movea rw4, @rw5+d8 movea rw4, @rw6+d8 movea rw4, @rw7+d8 movea rw4, @rw0+d16 movea rw4, @rw1+d16 movea rw4, @rw2+d16 movea rw4, @rw3+d16 movea rw4, @rw0+rw7 movea rw4, @rw1+rw7 movea rw4, @pc+d16 movea rw4, addr16 movea rw5, @rw0+d8 movea rw5, @rw1+d8 movea rw5, @rw2+d8 movea rw5, @rw3+d8 movea rw5, @rw4+d8 movea rw5, @rw5+d8 movea rw5, @rw6+d8 movea rw5, @rw7+d8 movea rw5, @rw0+d16 movea rw5, @rw1+d16 movea rw5, @rw2+d16 movea rw5, @rw3+d16 movea rw5, @rw0+rw7 movea rw5, @rw1+rw7 movea rw5, @pc+d16 movea rw5, addr16 movea rw6 ,@rw0+d8 movea rw6 ,@rw1+d8 movea rw6 ,@rw2+d8 movea rw6 ,@rw3+d8 movea rw6 ,@rw4+d8 movea rw6 ,@rw5+d8 movea rw6 ,@rw6+d8 movea rw6 ,@rw7+d8 movea rw6 ,@rw0+d16 movea rw6 ,@rw1+d16 movea rw6 ,@rw2+d16 movea rw6 ,@rw3+d16 movea rw6 ,@rw0+rw7 movea rw6 ,@rw1+rw7 movea rw6 ,@pc+d16 movea rw6 ,addr16 movea rw7, @rw0+d8 movea rw7, @rw1+d8 movea rw7, @rw2+d8 movea rw7, @rw3+d8 movea rw7, @rw4+d8 movea rw7, @rw5+d8 movea rw7, @rw6+d8 movea rw7, @rw7+d8 movea rw7, @rw0+d16 movea rw7, @rw1+d16 movea rw7, @rw2+d16 movea rw7, @rw3+d16 movea rw7, @rw0+rw7 movea rw7, @rw1+rw7 movea rw7, @pc+d16 movea rw7, addr16 @pc+d16
MB90560 series appendix b instructions 539 table b.9-16 mov ri,ea instruction map (1st byte = 7a h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 mov r0, r0 mov r0, r1 mov r0, r2 mov r0, r3 mov r0, r4 mov r0, r5 mov r0, r6 mov r0, r7 mov r0, @rw0 mov r0, @rw1 mov r0, @rw2 mov r0, @rw3 mov r0, @rw0+ mov r0, @rw1+ mov r0, @rw2+ mov r0, @rw3+ mov r0, @rw0+d8 mov r0, @rw1+d8 mov r0, @rw2+d8 mov r0, @rw3+d8 mov r0, @rw4+d8 mov r0, @rw5+d8 mov r0, @rw6+d8 mov r0, @rw7+d8 mov r0, @rw0+d16 mov r0, @rw1+d16 mov r0, @rw2+d16 mov r0, @rw3+d16 mov r0, @rw0+rw7 mov r0, @rw1+rw7 mov r0, @pc+d16 mov r0, @addr16 mov r1, r0 mov r1, r1 mov r1, r2 mov r1, r3 mov r1, r4 mov r1, r5 mov r1, r6 mov r1, r7 mov r1, @rw0 mov r1, @rw1 mov r1, @rw2 mov r1, @rw3 mov r1, r1, @rw0+ mov r1, r1, @rw1+ mov r1, r1, @rw2+ mov r1, r1, @rw3+ mov r2, r0 mov r2, r1 mov r2, r2 mov r2, r3 mov r2, r4 mov r2, r5 mov r2, r6 mov r2, r7 mov r2, @rw0 mov r2, @rw1 mov r2, @rw2 mov r2, @rw3 mov r2, @rw0+ mov r2, @rw1+ mov r2, @rw2+ mov r2, @rw3+ mov r3, r0 mov r3, r1 mov r3, r2 mov r3, r3 mov r3, r4 mov r3, r5 mov r3, r6 mov r3, r7 mov r3, @rw0 mov r3, @rw1 mov r3, @rw2 mov r3, @rw3 mov r3, @rw0+ mov r3, @rw1+ mov r3, @rw2+ mov r3, @rw3+ mov r4, r0 mov r4, r1 mov r4, r2 mov r4, r3 mov r4, r4 mov r4, r5 mov r4, r6 mov r4, r7 mov r4, @rw0 mov r4, @rw1 mov r4, @rw2 mov r4, @rw3 mov r4, @rw0+ mov r4, @rw1+ mov r4, @rw2+ mov r4, @rw3+ mov r5, r0 mov r5, r1 mov r5, r2 mov r5, r3 mov r5, r4 mov r5, r5 mov r5, r6 mov r5, r7 mov r5, @rw0 mov r5, @rw1 mov r5, @rw2 mov r5, @rw3 mov r5, @rw0+ mov r5, @rw1+ mov r5, @rw2+ mov r5, @rw3+ mov r6, r0 mov r6, r1 mov r6, r2 mov r6, r3 mov r6, r4 mov r6, r5 mov r6, r6 mov r6, r7 mov r6, @rw0 mov r6, @rw1 mov r6, @rw2 mov r6, @rw3 mov r6, @rw0+ mov r6, @rw1+ mov r6, @rw2+ mov r6, @rw3+ mov r7, r0 mov r7, r1 mov r7, r2 mov r7, r3 mov r7, r4 mov r7, r5 mov r7, r6 mov r7, r7 mov r7, @rw0 mov r7, @rw1 mov r7, @rw2 mov r7, @rw3 mov r7, @rw0+ mov r7, @rw1+ mov r7, @rw2+ mov r7, @rw3+ mov r1, @rw0+d8 mov r1, @rw1+d8 mov r1, @rw2+d8 mov r1, @rw3+d8 mov r1, @rw4+d8 mov r1, @rw5+d8 mov r1, @rw6+d8 mov r1, @rw7+d8 mov r1, @rw0+d16 mov r1, @rw1+d16 mov r1, @rw2+d16 mov r1, @rw3+d16 mov r1, @rw0+rw7 mov r1, @rw1+rw7 mov r1, mov r1, addr16 mov r2, @rw0+d8 mov r2, @rw1+d8 mov r2, @rw2+d8 mov r2, @rw3+d8 mov r2, @rw4+d8 mov r2, @rw5+d8 mov r2, @rw6+d8 mov r2, @rw7+d8 mov r2, @rw0+d16 mov r2, @rw1+d16 mov r2, @rw2+d16 mov r2, @rw3+d16 mov r2, @rw0+rw7 mov r2, @rw1+rw7 mov r2, @pc+d16 mov r2, addr16 mov r3, @rw0+d8 mov r3, @rw1+d8 mov r3, @rw2+d8 mov r3, @rw3+d8 mov r3, @rw4+d8 mov r3, @rw5+d8 mov r3, @rw6+d8 mov r3, @rw7+d8 mov r3, @rw0+d16 mov r3, @rw1+d16 mov r3, @rw2+d16 mov r3, @rw3+d16 mov r3, @rw0+rw7 mov r3, @rw1+rw7 mov r3, @pc+d16 mov r3, addr16 mov r4, @rw0+d8 mov r4, @rw1+d8 mov r4, @rw2+d8 mov r4, @rw3+d8 mov r4, @rw4+d8 mov r4, @rw5+d8 mov r4, @rw6+d8 mov r4, @rw7+d8 mov r4, @rw0+d16 mov r4, @rw1+d16 mov r4, @rw2+d16 mov r4, @rw3+d16 mov r4, @rw0+rw7 mov r4, @rw1+rw7 mov r4, @pc+d16 mov r4, addr16 mov r5, @rw0+d8 mov r5, @rw1+d8 mov r5, @rw2+d8 mov r5, @rw3+d8 mov r5, @rw4+d8 mov r5, @rw5+d8 mov r5, @rw6+d8 mov r5, @rw7+d8 mov r5, @rw0+d16 mov r5, @rw1+d16 mov r5, @rw2+d16 mov r5, @rw3+d16 mov r5, @rw0+rw7 mov r5, @rw1+rw7 mov r5, @pc+d16 mov r5, addr16 mov r6, @rw0+d8 mov r6, @rw1+d8 mov r6, @rw2+d8 mov r6, @rw3+d8 mov r6, @rw4+d8 mov r6, @rw5+d8 mov r6, @rw6+d8 mov r6, @rw7+d8 mov r6, @rw0+d16 mov r6, @rw1+d16 mov r6, @rw2+d16 mov r6, @rw3+d16 mov r6, @rw0+rw7 mov r6, @rw1+rw7 mov r6, @pc+d16 mov r6, addr16 mov r7, @rw0+d8 mov r7, @rw1+d8 mov r7, @rw2+d8 mov r7, @rw3+d8 mov r7, @rw4+d8 mov r7, @rw5+d8 mov r7, @rw6+d8 mov r7, @rw7+d8 mov r7, @rw0+d16 mov r7, @rw1+d16 mov r7, @rw2+d16 mov r7, @rw3+d16 mov r7, @rw0+rw7 mov r7, @rw1+rw7 mov r7, @pc+d16 mov r7, addr16 @pc+d16
540 appendix b instructions MB90560 series table b.9-17 movw rwi,ea instruction map (1st byte = 7b h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 movw rw0, rw0 movw rw0, rw1 movw rw0, rw2 movw rw0, rw3 movw rw0, rw4 movw rw0, rw5 movw rw0, rw6 movw rw0, rw7 movw rw0, @rw0 movw rw0, @rw1 movw rw0, @rw2 movw rw0, @rw3 movw r w0, @rw0+ movw r w0, @rw1+ movw r w0, @rw2+ movw r w0, @rw3+ movw rw0, @rw0+d8 movw rw0, @rw1+d8 movw rw0, @rw2+d8 movw rw0, @rw3+d8 movw rw0, @rw4+d8 movw rw0, @rw5+d8 movw rw0, @rw6+d8 movw rw0, @rw7+d8 movw rw0, @rw0+d16 movw rw0, @rw1+d16 movw rw0, @rw2+d16 movw rw0, @rw3+d16 movw rw0, @rw0+rw7 movw rw0, @rw1+rw7 movw rw0, @pc+d16 movw rw0, addr16 movw rw1, rw0 movw rw1, rw1 movw rw1, rw2 movw rw1, rw3 movw rw1, rw4 movw rw1, rw5 movw rw1, rw6 movw rw1, rw7 movw rw1, @rw0 movw rw1, @rw1 movw rw1, @rw2 movw rw1, @rw3 movw r w1, @rw0+ movw r w1, @rw1+ movw r w1, @rw2+ movw r w1, @rw3+ movw rw2, rw0 movw rw2, rw1 movw rw2, rw2 movw rw2, rw3 movw rw2, rw4 movw rw2, rw5 movw rw2, rw6 movw rw2, rw7 movw rw2, @rw0 movw rw2, @rw1 movw rw2, @rw2 movw rw2, @rw3 movw r w2, @rw0+ movw r w2, @rw1+ movw r w2, @rw2+ movw r w2, @rw3+ movw rw3, rw0 movw rw3, rw1 movw rw3, rw2 movw rw3, rw3 movw rw3, rw4 movw rw3, rw5 movw rw3, rw6 movw rw3, rw7 movw rw3, @rw0 movw rw3, @rw1 movw rw3, @rw2 movw rw3, @rw3 movw r w3, @rw0+ movw r w3, @rw1+ movw r w3, @rw2+ movw r w3, @rw3+ movw rw4, rw0 movw rw4, rw1 movw rw4, rw2 movw rw4, rw3 movw rw4, rw4 movw rw4, rw5 movw rw4, rw6 movw rw4, rw7 movw rw4, @rw0 movw rw4, @rw1 movw rw4, @rw2 movw rw4, @rw3 movw r w4, @rw0+ movw r w4, @rw1+ movw r w4, @rw2+ movw r w4, @rw3+ movw rw5, rw0 movw rw5, rw1 movw rw5, rw2 movw rw5, rw3 movw rw5, rw4 movw rw5, rw5 movw rw5, rw6 movw rw5, rw7 movw rw5, @rw0 movw rw5, @rw1 movw rw5, @rw2 movw rw5, @rw3 movw r w5, @rw0+ movw r w5, @rw1+ movw r w5, @rw2+ movw r w5, @rw3+ movw rw6, rw0 movw rw6, rw1 movw rw6, rw2 movw rw6, rw3 movw rw6, rw4 movw rw6, rw5 movw rw6, rw6 movw rw6, rw7 movw rw6, @rw0 movw rw6, @rw1 movw rw6, @rw2 movw rw6, @rw3 movw r w6, @rw0+ movw r w6, @rw1+ movw r w6, @rw2+ movw r w6, @rw3+ movw rw7, rw0 movw rw7, rw1 movw rw7, rw2 movw rw7, rw3 movw rw7, rw4 movw rw7, rw5 movw rw7, rw6 movw rw7, rw7 movw rw7, @rw0 movw rw7, @rw1 movw rw7, @rw2 movw rw7, @rw3 movw r w7, @rw0+ movw r w7, @rw1+ movw r w7, @rw2+ movw r w7, @rw3+ movw rw1, @rw0+d8 movw rw1, @rw1+d8 movw rw1, @rw2+d8 movw rw1, @rw3+d8 movw rw1, @rw4+d8 movw rw1, @rw5+d8 movw rw1, @rw6+d8 movw rw1, @rw7+d8 movw rw1, @rw0+d16 movw rw1, @rw1+d16 movw rw1, @rw2+d16 movw rw1, @rw3+d16 movw rw1, @rw0+rw7 movw rw1, @rw1+rw7 movw rw1, movw rw1, addr16 movw rw2, @rw0+d8 movw rw2, @rw1+d8 movw rw2, @rw2+d8 movw rw2, @rw3+d8 movw rw2, @rw4+d8 movw rw2, @rw5+d8 movw rw2, @rw6+d8 movw rw2, @rw7+d8 movw rw2, @rw0+d16 movw rw2, @rw1+d16 movw rw2, @rw2+d16 movw rw2, @rw3+d16 movw rw2, @rw0+rw7 movw rw2, @rw1+rw7 movw rw2, @pc+d16 movw rw2, addr16 movw rw3, @rw0+d8 movw rw3, @rw1+d8 movw rw3, @rw2+d8 movw rw3, @rw3+d8 movw rw3, @rw4+d8 movw rw3, @rw5+d8 movw rw3, @rw6+d8 movw rw3, @rw7+d8 movw rw3, @rw0+d16 movw rw3, @rw1+d16 movw rw3, @rw2+d16 movw rw3, @rw3+d16 movw rw3, @rw0+rw7 movw rw3, @rw1+rw7 movw rw3, @pc+d16 movw rw3, addr16 movw rw4, @rw0+d8 movw rw4, @rw1+d8 movw rw4, @rw2+d8 movw rw4, @rw3+d8 movw rw4, @rw4+d8 movw rw4, @rw5+d8 movw rw4, @rw6+d8 movw rw4, @rw7+d8 movw rw4, @rw0+d16 movw rw4, @rw1+d16 movw rw4, @rw2+d16 movw rw4, @rw3+d16 movw rw4, @rw0+rw7 movw rw4, @rw1+rw7 movw rw4, @pc+d16 movw rw4, addr16 movw rw5, @rw0+d8 movw rw5, @rw1+d8 movw rw5, @rw2+d8 movw rw5, @rw3+d8 movw rw5, @rw4+d8 movw rw5, @rw5+d8 movw rw5, @rw6+d8 movw rw5, @rw7+d8 movw rw5, @rw0+d16 movw rw5, @rw1+d16 movw rw5, @rw2+d16 movw rw5, @rw3+d16 movw rw5, @rw0+rw7 movw rw5, @rw1+rw7 movw rw5, @pc+d16 movw rw5, addr16 movw rw6, @rw0+d8 movw rw6, @rw1+d8 movw rw6, @rw2+d8 movw rw6, @rw3+d8 movw rw6, @rw4+d8 movw rw6, @rw5+d8 movw rw6, @rw6+d8 movw rw6, @rw7+d8 movw rw6, @rw0+d16 movw rw6, @rw1+d16 movw rw6, @rw2+d16 movw rw6, @rw3+d16 movw rw6, @rw0+rw7 movw rw6, @rw1+rw7 movw rw6, @pc+d16 movw rw6, addr16 movw rw7, @rw0+d8 movw rw7, @rw1+d8 movw rw7, @rw2+d8 movw rw7, @rw3+d8 movw rw7, @rw4+d8 movw rw7, @rw5+d8 movw rw7, @rw6+d8 movw rw7, @rw7+d8 movw rw7, @rw0+d16 movw rw7, @rw1+d16 movw rw7, @rw2+d16 movw rw7, @rw3+d16 movw rw7, @rw0+rw7 movw rw7, @rw1+rw7 movw rw7, @pc+d16 movw rw7, addr16 @pc+d16
MB90560 series appendix b instructions 541 table b.9-18 mov ea,ri instruction map (1st byte = 7c h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 mov r0, r0 mov r1, r0 mov r2, r0 mov r3, r0 mov r4, r0 mov r5, r0 mov r6, r0 mov r7, r0 mov @rw0, r0 mov @rw1, r0 mov @rw2, r0 mov @rw3, r0 mov @rw0+, r0 mov @rw1+, r0 mov @rw2+, r0 mov @rw3+, r0 mov @r w0+d8, r0 mov @r w1+d8, r0 mov @r w2+d8, r0 mov @r w3+d8, r0 mov @r w4+d8, r0 mov @r w5+d8, r0 mov @r w6+d8, r0 mov @r w7+d8, r0 mov @rw w0+d16, r0 mov @rw w1+d16, r0 mov @rw w2+d16, r0 mov @rw w3+d16, r0 mov @rw w0+rw7, r0 mov @rw w1+rw7, r0 mov pc+d16, r0 mov addr16, r0 mov r0, r1 mov r1, r1 mov r2, r1 mov r3, r1 mov r4, r1 mov r5, r1 mov r6, r1 mov r7, r1 mov @rw0, r1 mov @rw1, r1 mov @rw2, r1 mov @rw3, r1 mov @rw0+, r1 mov @rw1+, r1 mov @rw2+, r1 mov @rw3+, r1 mov r0, r2 mov r1, r2 mov r2, r2 mov r3, r2 mov r4, r2 mov r5, r2 mov r6, r2 mov r7, r2 mov @rw0, r2 mov @rw1, r2 mov @rw2, r2 mov @rw3, r2 mov @rw0+, r2 mov @rw1+, r2 mov @rw2+, r2 mov @rw3+, r2 mov r0, r3 mov r1, r3 mov r2, r3 mov r3, r3 mov r4, r3 mov r5, r3 mov r6, r3 mov r7, r3 mov @rw0, r3 mov @rw1, r3 mov @rw2, r3 mov @rw3, r3 mov @rw0+, r3 mov @rw1+, r3 mov @rw2+, r3 mov @rw3+, r3 mov r0, r4 mov r1, r4 mov r2, r4 mov r3, r4 mov r4, r4 mov r5, r4 mov r6, r4 mov r7, r4 mov @rw0, r4 mov @rw1, r4 mov @rw2, r4 mov @rw3, r4 mov @rw0+, r4 mov @rw1+, r4 mov @rw2+, r4 mov @rw3+, r4 mov r0, r5 mov r1, r5 mov r2, r5 mov r3, r5 mov r4, r5 mov r5, r5 mov r6, r5 mov r7, r5 mov @rw0, r5 mov @rw1, r5 mov @rw2, r5 mov @rw3, r5 mov @rw0+, r5 mov @rw1+, r5 mov @rw2+, r5 mov @rw3+, r5 mov r0, r6 mov r1, r6 mov r2, r6 mov r3, r6 mov r4, r6 mov r5, r6 mov r6, r6 mov r7, r6 mov @rw0, r6 mov @rw1, r6 mov @rw2, r6 mov @rw3, r6 mov @rw0+, r6 mov @rw1+, r6 mov @rw2+, r6 mov @rw3+, r6 mov r0, r7 mov r1, r7 mov r2, r7 mov r3, r7 mov r4, r7 mov r5, r7 mov r6, r7 mov r7, r7 mov @rw0, r7 mov @rw1, r7 mov @rw2, r7 mov @rw3, r7 mov @rw0+, r7 mov @rw1+, r7 mov @rw2+, r7 mov @rw3+, r7 mov @r w0+d8, r1 mov @r w1+d8, r1 mov @r w2+d8, r1 mov @r w3+d8, r1 mov @r w4+d8, r1 mov @r w5+d8, r1 mov @r w6+d8, r1 mov @r w7+d8, r1 mov @rw 0+d16, r1 mov @rw 1+d16, r1 mov @rw 2+d16, r1 mov @rw 3+d16, r1 mov @rw 0+rw7, r1 mov @rw 1+rw7, r1 mov mov addr16, r1 mov @r, w0+d8, r2 mov @r w1+d8, r2 mov @r w2+d8, r2 mov @r w3+d8, r2 mov @r w4+d8, r2 mov @r w5+d8, r2 mov @r w6+d8, r2 mov @r w7+d8, r2 mov @rw 0+d16, r2 mov @rw 1+d16, r2 mov @rw 2+d16, r2 mov @rw 3+d16, r2 mov @rw 0+rw7, r2 mov @rw 1+rw7, r2 mov pc+d16, r2 mov addr16, r2 mov @r w0+d8, r3 mov @r w1+d8, r3 mov @r w2+d8, r3 mov @r w3+d8, r3 mov @r w4+d8, r3 mov @r w5+d8, r3 mov @r w6+d8, r3 mov @r w7+d8, r3 mov @rw 0+d16, r3 mov @rw 1+d16, r3 mov @rw 2+d16, r3 mov @rw 3+d16, r3 mov @rw 0+rw7, r3 mov @rw 1+rw7, r3 mov pc+d16, r3 mov addr16, r3 mov @r w0+d8, r4 mov @r w1+d8, r4 mov @r, w2+d8, r4 mov @r, w3+d8, r4 mov @r w4+d8, r4 mov @r w5+d8, r4 mov @r w6+d8, r4 mov @r w7+d8, r4 mov @rw 0+d16, r4 mov @rw 1+d16, r4 mov @rw 2+d16, r4 mov @rw 3+d16, r4 mov @rw 0+rw7, r4 mov @rw 1+rw7, r4 mov pc+d16, r4 mov addr16, r4 mov @r w0+d8, r5 mov @r w1+d8, r5 mov @r w2+d8, r5 mov @r w3+d8, r5 mov @r w4+d8, r5 mov @r w5+d8, r5 mov @r w6+d8, r5 mov @r w7+d8, r5 mov @rw 0+d16, r5 mov @rw 1+d16, r5 mov @rw 2+d16, r5 mov @rw 3+d16, r5 mov @rw 0+rw7, r5 mov @rw 1+rw7, r5 mov pc+d16, r5 mov addr16, r5 mov @r w0+d8, r6 mov @r w1+d8, r6 mov @r w2+d8, r6 mov @r w3+d8, r6 mov @r w4+d8, r6 mov @r w5+d8, r6 mov @r w6+d8, r6 mov @r w7+d8, r6 mov @rw 0+d16, r6 mov @rw 1+d16, r6 mov @rw 2+d16, r6 mov @rw 3+d16, r6 mov @rw 0+rw7, r6 mov @rw 1+rw7,r6 mov pc+d16, r6 mov addr16, r6 mov @r w0+d8, r7 mov @r w1+d8, r7 mov @r w2+d8, r7 mov @r w3+d8, r7 mov @r w4+d8, r7 mov @r w5+d8, r7 mov @r w6+d8, r7 mov @r w7+d8, r7 mov @rw 0+d16, r7 mov @rw 1+d16, r7 mov @rw 2+d16, r7 mov @rw 3+d16, r7 mov @rw 0+rw7, r7 mov @rw 1+rw7, r7 mov pc+d16, r7 mov addr16, r7 pc+d16, r1
542 appendix b instructions MB90560 series table b.9-19 movw ea,rwi instruction map (1st byte = 7d h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 movw rw0, rw0 movw rw1, rw0 movw rw2, rw0 movw rw3, rw0 movw rw4, rw0 movw rw5, rw0 movw rw6, rw0 movw rw7, rw0 movw @rw0, rw0 movw @rw1, rw0 movw @rw2, rw0 movw @rw3, rw0 movw @rw0+, rw0 movw @rw1+, rw0 movw @rw2+, rw0 movw @rw3+, rw0 movw @rw 0+d8, rw0 movw @rw 1+d8, rw0 movw @rw 2+d8, rw0 movw @rw 3+d8, rw0 movw @rw 4+d8, rw0 movw @rw 5+d8, rw0 movw @rw 6+d8, rw0 movw @rw 7+d8, rw0 movw@rw0 +d16, rw0 movw@rw1 +d16, rw0 movw@rw2 +d16, rw0 movw@rw3 +d16, rw0 movw@rw0 +rw7, rw0 movw@rw1 +rw7, rw0 movw @pc+ d16, rw0 movw addr 16, rw0 movw rw0, rw1 movw rw1, rw1 movw rw2, rw1 movw rw3, rw1 movw rw4, rw1 movw rw5, rw1 movw rw6, rw1 movw rw7, rw1 movw @rw0, rw1 movw @rw1, rw1 movw @rw2, rw1 movw @rw3, rw1 movw @ rw0+, rw1 movw @ rw1+, rw1 movw @ rw2+, rw1 movw @ rw3+, rw1 movw @rw 0+d8, rw1 movw @r 1+d8, rw1 movw @rw 2+d8, rw1 movw @rw 3+d8, rw1 movw @rw 4+d8, rw1 movw @rw 5+d8, rw1 movw @rw 6+d8, rw1 movw @rw 7+d8, rw1 movw@rw0 +d16, rw1 movw@rw1 +d16, rw1 movw@rw2 +d16, rw1 movw@rw3 +d16, rw1 movw@rw0 +rw7, rw1 movw@rw1 +rw7, rw1 movw @pc+ d16, rw1 movw addr 16, rw1 movw rw0, rw2 movw rw1, rw2 movw rw2, rw2 movw rw3, rw2 movw rw4, rw2 movw rw5, rw2 movw rw6, rw2 movw rw7, rw2 movw @rw0, rw2 movw @rw1, rw2 movw @rw2, rw2 movw @rw3, rw2 movw @ rw0+, rw2 movw @ rw1+, rw2 movw @ rw2+, rw2 movw @ rw3+, rw2 movw @rw 0+d8, rw2 movw @r 1+d8, rw2 movw @rw 2+d8, rw2 movw @rw 3+d8, rw2 movw @rw 4+d8, rw2 movw @rw 5+d8, rw2 movw @rw 6+d8, rw2 movw @rw 7+d8, rw2 movw@rw0 +d16, rw2 movw@rw1 +d16, rw2 movw@rw2 +d16, rw2 movw@rw3 +d16, rw2 movw@rw0 +rw7, rw2 movw@rw1 +rw7, rw2 movw @pc+ d16, rw2 movw addr 16, rw2 movw rw0, rw3 movw rw1, rw3 movw rw2, rw3 movw rw3, rw3 movw rw4, rw3 movw rw5, rw3 movw rw6, rw3 movw rw7, rw3 movw @rw0, rw3 movw @rw1, rw3 movw @rw2, rw3 movw @rw3, rw3 movw @ rw0+, rw3 movw @ rw1+, rw3 movw @ rw2+, rw3 movw @ rw3+, rw3 movw @rw 0+d8, rw3 movw @rw 1+d8, rw3 movw @rw 2+d8, rw3 movw @rw 3+d8, rw3 movw @rw 4+d8, rw3 movw @rw 5+d8, rw3 movw @rw 6+d8, rw3 movw @rw 7+d8, rw3 movw@rw0 +d16, rw3 movw@rw1 +d16, rw3 movw@rw2 +d16, rw3 movw@rw3 +d16, rw3 movw@rw0 +rw7, rw3 movw@rw1 +rw7, rw3 movw @pc+ d16, rw3 movw addr 16, rw3 movw rw0, rw4 movw rw1, rw4 movw rw2, rw4 movw rw3, rw4 movw rw4, rw4 movw rw5, rw4 movw rw6, rw4 movw rw7, rw4 movw @rw0, rw4 movw @rw1, rw4 movw @rw2, rw4 movw @rw3, rw4 movw @ rw0+, rw4 movw @ rw1+, rw4 movw @ rw2+, rw4 movw @ rw3+, rw4 movw @rw 0+d8, rw4 movw @rw 1+d8, rw4 movw @rw 2+d8, rw4 movw @rw 3+d8, rw4 movw @rw 4+d8, rw4 movw @rw 5+d8, rw4 movw @rw 6+d8, rw4 movw @rw 7+d8, rw4 movw@rw0 +d16, rw4 movw@rw1 +d16, rw4 movw@rw2 +d16, rw4 movw@rw3 +d16, rw4 movw@rw0 +rw7, rw4 movw@rw1 +rw7, rw4 movw @pc+ d16, rw4 movw addr 16, rw4 movw rw0, rw5 movw rw1, rw5 movw rw2, rw5 movw rw3, rw5 movw rw4, rw5 movw rw5, rw5 movw rw6, rw5 movw rw7, rw5 movw @rw0, rw5 movw @rw1, rw5 movw @rw2, rw5 movw @rw3, rw5 movw @ rw0+, rw5 movw @ rw1+, rw5 movw @ rw2+, rw5 movw @ rw3+, rw5 movw @rw 0+d8, rw5 movw @rw 1+d8, rw5 movw @rw 2+d8, rw5 movw @rw 3+d8, rw5 movw @rw 4+d8, rw5 movw @rw 5+d8, rw5 movw @rw 6+d8, rw5 movw @rw 7+d8, rw5 movw@rw0 +d16, rw5 movw@rw1 +d16, rw5 movw@rw2 +d16, rw5 movw@rw3 +d16, rw5 movw@rw0 +rw7, rw5 movw@rw1 +rw7, rw5 movw @pc+ d16, rw5 movw addr 16, rw5 movw rw0, rw6 movw rw1, rw6 movw rw2, rw6 movw rw3, rw6 movw rw4, rw6 movw rw5, rw6 movw rw6, rw6 movw rw7, rw6 movw @rw0, rw6 movw @rw1, rw6 movw @rw2, rw6 movw @rw3, rw6 movw @ rw0+, rw6 movw @ rw1+, rw6 movw @ rw2+, rw6 movw @ rw3+, rw6 movw @rw 0+d8, rw6 movw @rw 1+d8, rw6 movw @rw 2+d8, rw6 movw @rw 3+d8, rw6 movw @rw 4+d8, rw6 movw @rw 5+d8, rw6 movw @rw 6+d8, rw6 movw @rw 7+d8, rw6 movw@rw0 +d16, rw6 movw@rw1 +d16, rw6 movw@rw2 +d16, rw6 movw@rw3 +d16, rw6 movw@rw0 +rw7, rw6 movw@rw1 +rw7, rw6 movw @pc+ d16, rw6 movw addr 16, rw6 movw rw0, rw7 movw rw1, rw7 movw rw2, rw7 movw rw3, rw7 movw rw4, rw7 movw rw5, rw7 movw rw6, rw7 movw rw7, rw7 movw @rw0, rw7 movw @rw1, rw7 movw @rw2, rw7 movw @rw3, rw7 movw @ rw0+, rw7 movw @ rw1+, rw7 movw @ rw2+, rw7 movw @ rw3+, rw7 movw @rw 0+d8, rw7 movw @rw 1+d8, rw7 movw @rw 2+d8, rw7 movw @rw 3+d8, rw7 movw @rw 4+d8, rw7 movw @rw 5+d8, rw7 movw @rw 6+d8, rw7 movw @rw 7+d8, rw7 movw@rw0 +d16, rw7 movw@rw1 +d16, rw7 movw@rw2 +d16, rw7 movw@rw3 +d16, rw7 movw@rw0 +rw7, rw7 movw@rw1 +rw7, rw7 movw @pc+ d16, rw7 movw addr 16, rw7
MB90560 series appendix b instructions 543 table b.9-20 xch ri,ea instruction map (1st byte = 7e h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f 0 xch r0, r0 xch r0, r1 xch r0, r2 xch r0, r3 xch r0, r4 xch r0, r5 xch r0, r6 xch r0, r7 xch r0, @rw0 xch r0, @rw1 xch r0, @rw2 xch r0, @rw3 xch r0, @rw0+ xch r0, @rw1+ xch r0, @rw2+ xch r0, @rw3+ xch r0, @rw0+d8 xch r0, @rw1+d8 xch r0, @rw2+d8 xch r0, @rw3+d8 xch r0, @rw4+d8 xch r0, @rw5+d8 xch r0, @rw6+d8 xch r0, @rw7+d8 xch r0, @rw0+d16 xch r0, @rw1+d16 xch r0, @rw2+d16 xch r0, @rw3+d16 xch r0, @rw0+rw7 xch r0, @rw1+rw7 xch r0, @pc+d16 xch r0, addr16 xch r1, r0 xch r1, r1 xch r1, r2 xch r1, r3 xch r1, r4 xch r1, r5 xch r1, r6 xch r1, r7 xch r1, @rw0 xch r1, @rw1 xch r1, @rw2 xch r1, @rw3 xch r1, @rw0+ xch r1, @rw1+ xch r1, @rw2+ xch r1, @rw3+ xch r2, r0 xch r2, r1 xch r2, r2 xch r2, r3 xch r2, r4 xch r2, r5 xch r2, r6 xch r2, r7 xch r2, @rw0 xch r2, @rw1 xch r2, @rw2 xch r2, @rw3 xch r2, @rw0+ xch r2, @rw1+ xch r2, @rw2+ xch r2, @rw3+ xch r3, r0 xch r3, r1 xch r3, r2 xch r3, r3 xch r3, r4 xch r3, r5 xch r3, r6 xch r3, r7 xch r3, @rw0 xch r3, @rw1 xch r3, @rw2 xch r3, @rw3 xch r3, @rw0+ xch r3, @rw1+ xch r3, @rw2+ xch r3, @rw3+ xch r4, r0 xch r4, r1 xch r4, r2 xch r4, r3 xch r4, r4 xch r4, r5 xch r4, r6 xch r4, r7 xch r4, @rw0 xch r4, @rw1 xch r4, @rw2 xch r4, @rw3 xch r4, @rw0+ xch r4, @rw1+ xch r4, @rw2+ xch r4, @rw3+ xch r5, r0 xch r5, r1 xch r5, r2 xch r5, r3 xch r5, r4 xch r5, r5 xch r5, r6 xch r5, r7 xch r5, @rw0 xch r5, @rw1 xch r5, @rw2 xch r5, @rw3 xch r5, @rw0+ xch r5, @rw1+ xch r5, @rw2+ xch r5, @rw3+ xch r6, r0 xch r6, r1 xch r6, r2 xch r6, r3 xch r6, r4 xch r6, r5 xch r6, r6 xch r6, r7 xch r6, @rw0 xch r6, @rw1 xch r6, @rw2 xch r6, @rw3 xch r6, @rw0+ xch r6, @rw1+ xch r6, @rw2+ xch r6, @rw3+ xch r7, r0 xch r7, r1 xch r7, r2 xch r7, r3 xch r7, r4 xch r7, r5 xch r7, r6 xch r7, r7 xch r7, @rw0 xch r7, @rw1 xch r7, @rw2 xch r7, @rw3 xch r7, @rw0+ xch r7, @rw1+ xch r7, @rw2+ xch r7, @rw3+ xch r1, @rw0+d8 xch r1, @rw1+d8 xch r1, @rw2+d8 xch r1, @rw3+d8 xch r1, @rw4+d8 xch r1, @rw5+d8 xch r1, @rw6+d8 xch r1, @rw7+d8 xch r1, @rw0+d16 xch r1, @rw1+d16 xch r1, @rw2+d16 xch r1, @rw3+d16 xch r1, @rw0+rw7 xch r1, @rw1+rw7 xch r1, xch r1, addr16 xch r2, @rw0+d8 xch r2, @rw1+d8 xch r2, @rw2+d8 xch r2, @rw3+d8 xch r2, @rw4+d8 xch r2, @rw5+d8 xch r2, @rw6+d8 xch r2, @rw7+d8 xch r2, @rw0+d16 xch r2, @rw1+d16 xch r2, @rw2+d16 xch r2, @rw3+d16 xch r2, @rw0+rw7 xch r2, @rw1+rw7 xch r2, @pc+d16 xch r2, addr16 xch r3, @rw0+d8 xch r3, @rw1+d8 xch r3, @rw2+d8 xch r3, @rw3+d8 xch r3, @rw4+d8 xch r3, @rw5+d8 xch r3, @rw6+d8 xch r3, @rw7+d8 xch r3, @rw0+d16 xch r3, @rw1+d16 xch r3, @rw2+d16 xch r3, @rw3+d16 xch r3, @rw0+rw7 xch r3, @rw1+rw7 xch r3, @pc+d16 xch r3, addr16 xch r4, @rw0+d8 xch r4, @rw1+d8 xch r4, @rw2+d8 xch r4, @rw3+d8 xch r4, @rw4+d8 xch r4, @rw5+d8 xch r4, @rw6+d8 xch r4, @rw7+d8 xch r4, @rw0+d16 xch r4, @rw1+d16 xch r4, @rw2+d16 xch r4, @rw3+d16 xch r4, @rw0+rw7 xch r4, @rw1+rw7 xch r4, @pc+d16 xch r4, addr16 xch r5, @rw0+d8 xch r5, @rw1+d8 xch r5, @rw2+d8 xch r5, @rw3+d8 xch r5, @rw4+d8 xch r5, @rw5+d8 xch r5, @rw6+d8 xch r5, @rw7+d8 xch r5, @rw0+d16 xch r5, @rw1+d16 xch r5, @rw2+d16 xch r5, @rw3+d16 xch r5, @rw0+rw7 xch r5, @rw1+rw7 xch r5, @pc+d16 xch r5, addr16 xch r6, @rw0+d8 xch r6, @rw1+d8 xch r6, @rw2+d8 xch r6, @rw3+d8 xch r6, @rw4+d8 xch r6, @rw5+d8 xch r6, @rw6+d8 xch r6, @rw7+d8 xch r6, @rw0+d16 xch r6, @rw1+d16 xch r6, @rw2+d16 xch r6, @rw3+d16 xch r6, @rw0+rw7 xch r6, @rw1+rw7 xch r6, @pc+d16 xch r6, addr16 xch r7, @rw0+d8 notw r7, @rw1+d8 xch r7, @rw2+d8 notw r7, @rw3+d8 notw r7, @rw4+d8 xch r7, @rw5+d8 xch r7, @rw6+d8 xch r7, @rw7+d8 xch r7, @rw0+d16 xch r7, @rw1+d16 xch r7, @rw2+d16 xch r7, @rw3+d16 xch r7, @rw0+rw7 xch r7, @rw1+rw7 xch r7, @pc+d16 xch r7, addr16 @pc+d16
544 appendix b instructions MB90560 series table b.9-21 xchw rwi,ea instruction map (1st byte = 7f h ) +0 +1 +2 +3 +4 +5 +6 +7 +8 +9 +a +b +c +d +e +f 0 0 1 0 2 0 3 0 4 0 5 0 6 0 7 0 8 0 9 0 a 0 b 0 c 0 d 0 e 0 f 0 xchw rw0, rw0 xchw rw0, rw1 xchw rw0, rw2 xchw rw0, rw3 xchw rw0, rw4 xchw rw0, rw5 xchw rw0, rw6 xchw rw0, rw7 xchw rw0, @rw0 xchw rw0, @rw1 xchw rw0, @rw2 xchw rw0, @rw3 xchw r w0, @rw0+ xchw r w0, @rw1+ xchw r w0, @rw2+ xchw r w0, @rw3+ xchw rw0, @rw0+d8 xchw rw0, @rw1+d8 xchw rw0, @rw2+d8 xchw rw0, @rw3+d8 xchw rw0, @rw4+d8 xchw rw0, @rw5+d8 xchw rw0, @rw6+d8 xchw rw0, @rw7+d8 xchw rw0, @rw0+d16 xchw rw0, @rw1+d16 xchw rw0, @rw2+d16 xchw rw0, @rw3+d16 xchw rw0, @rw0+rw7 xchw rw0, @rw1+rw7 xchw rw0, @pc +d16 xchw rw0, addr16 xchw rw1, rw0 xchw rw1, rw1 xchw rw1, rw2 xchw rw1, rw3 xchw rw1, rw4 xchw rw1, rw5 xchw rw1, rw6 xchw rw1, rw7 xchw rw1, @rw0 xchw rw1, @rw1 xchw rw1, @rw2 xchw rw1, @rw3 xchw r w1, @rw0+ xchw r w1, @rw1+ xchw r w1, @rw2+ xchw r w1, @rw3+ xchw rw2, rw0 xchw rw2, rw1 xchw rw2, rw2 xchw rw2, rw3 xchw rw2, rw4 xchw rw2, rw5 xchw rw2, rw6 xchw rw2, rw7 xchw rw2, @rw0 xchw rw2, @rw1 xchw rw2, @rw2 xchw rw2, @rw3 xchw r w2, @rw0+ xchw r w2, @rw1+ xchw r w2, @rw2+ xchw r w2, @rw3+ xchw rw3, rw0 xchw rw3, rw1 xchw rw3, rw2 xchw rw3, rw3 xchw rw3, rw4 xchw rw3, rw5 xchw rw3, rw6 xchw rw3, rw7 xchw rw3, @rw0 xchw rw3, @rw1 xchw rw3, @rw2 xchw rw3, @rw3 xchw r w3, @rw0+ xchw r w3, @rw1+ xchw r w3, @rw2+ xchw r w3, @rw3+ xchw rw4, rw0 xchw rw4, rw1 xchw rw4, rw2 xchw rw4, rw3 xchw rw4, rw4 xchw rw4, rw5 xchw rw4, rw6 xchw rw4, rw7 xchw rw4, @rw0 xchw rw4, @rw1 xchw rw4, @rw2 xchw rw4, @rw3 xchw r w4, @rw0+ xchw r w4, @rw1+ xchw r w4, @rw2+ xchw r w4, @rw3+ xchw rw5, rw0 xchw rw5, rw1 xchw rw5, rw2 xchw rw5, rw3 xchw rw5, rw4 xchw rw5, rw5 xchw rw5, rw6 xchw rw5, rw7 xchw rw5, @rw0 xchw rw5, @rw1 xchw rw5, @rw2 xchw rw5, @rw3 xchw r w5, @rw0+ xchw r w5, @rw1+ xchw r w5, @rw2+ xchw r w5, @rw3+ xchw rw6, rw0 xchw rw6, rw1 xchw rw6, rw2 xchw rw6, rw3 xchw rw6, rw4 xchw rw6, rw5 xchw rw6, rw6 xchw rw6, rw7 xchw rw6, @rw0 xchw rw6, @rw1 xchw rw6, @rw2 xchw rw6, @rw3 xchw r w6, @rw0+ xchw r w6, @rw1+ xchw r w6, @rw2+ xchw r w6, @rw3+ xchw rw7, rw0 xchw rw7, rw1 xchw rw7, rw2 xchw rw7, rw3 xchw rw7, rw4 xchw rw7, rw5 xchw rw7, rw6 xchw rw7, rw7 xchw rw7, @rw0 xchw rw7, @rw1 xchw rw7, @rw2 xchw rw7, @rw3 xchw r w7, @rw0+ xchw r w7, @rw1+ xchw r w7, @rw2+ xchw r w7, @rw3+ xchw rw1, @rw0+d8 xchw rw1, @rw1+d8 xchw rw1, @rw2+d8 xchw rw1, @rw3+d8 xchw rw1, @rw4+d8 xchw rw1, @rw5+d8 xchw rw1, @rw6+d8 xchw rw1, @rw7+d8 xchw rw1, @rw0+d16 xchw rw1, @rw1+d16 xchw rw1, @rw2+d16 xchw rw1, @rw3+d16 xchw rw1, @rw0+rw7 xchw rw1, @rw1+rw7 xchw rw1, xchw rw1, addr16 xchw rw2, @rw0+d8 xchw rw2, @rw1+d8 xchw rw2, @rw2+d8 xchw rw2, @rw3+d8 xchw rw2, @rw4+d8 xchw rw2, @rw5+d8 xchw rw2, @rw6+d8 xchw rw2, @rw7+d8 xchw rw2, @rw0+d16 xchw rw2, @rw1+d16 xchw rw2, @rw2+d16 xchw rw2, @rw3+d16 xchw rw2, @rw0+rw7 xchw rw2, @rw1+rw7 xchw rw2, @pc+d16 xchw rw2, addr16 xchw rw3, @rw0+d8 xchw rw3, @rw1+d8 xchw rw3, @rw2+d8 xchw rw3, @rw3+d8 xchw rw3, @rw4+d8 xchw rw3, @rw5+d8 xchw rw3, @rw6+d8 xchw rw3, @rw7+d8 xchw rw3, @rw0+d16 xchw rw3, @rw1+d16 xchw rw3, @rw2+d16 xchw rw3, @rw3+d16 xchw rw3, @rw0+rw7 xchw rw3, @rw1+rw7 xchw rw3, @pc+d16 xchw rw3, addr16 xchw rw4, @rw0+d8 xchw rw4, @rw1+d8 xchw rw4, @rw2+d8 xchw rw4, @rw3+d8 xchw rw4, @rw4+d8 xchw rw4, @rw5+d8 xchw rw4, @rw6+d8 xchw rw4, @rw7+d8 xchw rw4, @rw0+d16 xchw rw4, @rw1+d16 xchw rw4, @rw2+d16 xchw rw4, @rw3+d16 xchw rw4, @rw0+rw7 xchw rw4, @rw1+rw7 xchw rw4, @pc+d16 xchw rw4, addr16 xchw rw5, @rw0+d8 xchw rw5, @rw1+d8 xchw rw5, @rw2+d8 xchw rw5, @rw3+d8 xchw rw5, @rw4+d8 xchw rw5, @rw5+d8 xchw rw5, @rw6+d8 xchw rw5, @rw7+d8 xchw rw5, @rw0+d16 xchw rw5, @rw1+d16 xchw rw5, @rw2+d16 xchw rw5, @rw3+d16 xchw rw5, @rw0+rw7 xchw rw5, @rw1+rw7 xchw rw5, @pc+d16 xchw rw5, addr16 xchw rw6, @rw0+d8 xchw rw6, @rw1+d8 xchw rw6, @rw2+d8 xchw rw6, @rw3+d8 xchw rw6, @rw4+d8 xchw rw6, @rw5+d8 xchw rw6, @rw6+d8 xchw rw6, @rw7+d8 xchw rw6, @rw0+d16 xchw rw6, @rw1+d16 xchw rw6, @rw2+d16 xchw rw6, @rw3+d16 xchw rw6, @rw0+rw7 xchw rw6, @rw1+rw7 xchw rw6, @pc+d16 xchw rw6, addr16 xchw rw7, @rw0+d8 xchw rw7, @rw1+d8 xchw rw7, @rw2+d8 xchw rw7, @rw3+d8 xchw rw7, @rw4+d8 xchw rw7, @rw5+d8 xchw rw7, @rw6+d8 xchw rw7, @rw7+d8 xchw rw7, @rw0+d16 xchw rw7, @rw1+d16 xchw rw7, @rw2+d16 xchw rw7, @rw3+d16 xchw rw7, @rw0+rw7 xchw rw7, @rw1+rw7 xchw rw7, @pc+d16 xchw rw7, addr16 @pc+d16
appendix c 512k-bit flash memory the 512k-bit flash memory features the following: ? sector configuration of 64k words x 8 bits/32k words x 16 bits (16k + 512 x 2 + 7k + 8k + 32k) ? automatic programming algorithm (embedded algorithm: same as mbm29f400ta) ? erase fault/erase restart function ? detecting the completion of write/erase by data polling or using toggle bits ? detecting the completion of write/erase using the ry and by pins ? detecting the completion of write/erase using a cpu interrupt ? compatible with jedec standard commands ? erasable in units of sectors (free combination of sectors) ? a minimum of 100 write/erase operations embedded algorithm is a trademark of advanced micro device corporation. n sector configuration figure c-1 shows the sector configuration of the 512k-bit flash memory. when the memory is accessed from the cpu, sa0 to sa5 are seen in the ff bank. figure c-1 sector configuration of 512k-bit flash memory n flash memory mode when the mode pins are set to 111 for resetting, the cpu is shut down. when this occurs, the function of the flash memory interface circuit connects the signals from ports 0, 1, 2, 3, and 4 directly to the control signals of flash memory and enables flash memory to be directly controlled from external pins. this mode gives an image where flash memory appears as a single unit on the external pins. the mode is mainly used when data is written or erased using the flash memory writer. in this mode, every operation of the automatic algorithm for the 512k-bit flash memory can be used. sa5 ( 16k b y tes ) sa4 (512 bytes) sa3 (512 bytes) sa2 (7k bytes) sa1 (8k bytes) sa0 (32k bytes) 7ffff h ffffffh 7bfff h ffbfffh 7bdff h ffbdffh writer address cpu address 7bbff h ffbbffh ff9fffh ff7fffh ff0000h 79fff h 77fff h 70000 h
546 appendix c 512k-bit flash memory MB90560 series n normal mode normal mode is specified when the mode pins are set for other than flash memory mode. the settings for use prohibition are excluded, though. the 1m-bit flash memory is allocated in the fe and ff banks on the cpu memory map, so the function of the flash memory interface circuit enables read access or program access from the cpu in the same way as with normal mask rom. in this mode, the 512k-bit flash memory can also be written or erased by an instruction from the cpu via the flash memory interface circuit. this function enables rewriting in the installed state under control of the internal cpu. in this mode, normal writing and erasing can be performed but selector operation such as for enable sector protection cannot be performed. n control signals of 512k-bit flash memory table c.1 lists the flash memory control signals used in normal mode and flash memory mode. l flash memory mode in this mode, external data bus width is limited to 8 bits and therefore only byte access is enabled. d15 to d08 are not used. be sure to set the bytex pin to 0. l normal mode signals other than the reset signal are under control of the flash memory interface circuit. the data bus of flash memory is connected to the internal bus via the flash memory interface circuit. selecting between byte and word access makes no sense. therefore, the bytex signal of flash memory is internally fixed to 1 in this mode. table c-1 correspondence between external control pins and flash memory control signals external control pin flash memory mode pin normal mode rstx rstx rstx p36 bytex internally fixed to h p34 vacant for im (aq17) p33 wex internal and interface control signals p32 oex internal and interface control signals p31 cex internal and interface control signals p30 aq16 internal address bus (a16) p63, p46~ p40 aq15 ~ aq8 internal address bus (a15 to a8) p27~ p20 aq7 ~ aq0 internal address bus (a7 to a0) p07~ p00 dq7 ~ dq0 internal data bus (d7 to d0) md2 ~md0 vid pin (5v5%) md2 ~md0
MB90560 series appendix c 512k-bit flash memory 547 n control status register (fmcs) the control status register (fmcs) is situated in the flash memory interface circuit and used for writing or erasing flash memory when the cpu runs in normal mode. it cannot be used in flash memory mode. l register structure: control status register (fmcs) l bit description [bit 7]: interrupt enable (inte) this bit is used to cause an interrupt to the cpu when the writing or erasing of flash memory is finished. a cpu interrupt is caused when the inte and dyint bits are both 1. it is not caused when the inte bit is 0. [bit 6]: ready interrupt (rdyint) this bit is set to 1 after the writing or erasing of flash memory is finished. the writing or erasing of flash memory is disabled while this bit is 0 even after the writing or erasing of flash memory is finished. flash memory can be written or erased only after the bit is set to 1. writing 0 in the bit clears the bit to 0, but writing 1 in the bit is ignored. the bit is set to 1 at the leading edge of the ry/byx signal from flash memory. read modify write (rmw) always reads 1 from this bit. [bit 5]: write enable (we) this bit is used to enable writing to the flash memory area. when the bit is 1, a write to the ff or fe bank becomes a write to the flash memory area. the bit is used to activate a flash memory write or erase command. a write signal is generated when the bit is 1 and md2 to md0 are all 1. no write signal is generated when the bit is 0 or md2 to md0 are not all 1. [bit 4] : ready (rdy) rdy is a flash memory write/erase enable bit. while the bit is 0, flash memory cannot be written or erased. even in this situation, a read or reset command or a suspend command such as to temporarily stop a sector deletion can be accepted. refer to the mb29f400ta specifications for more information. [bit 3]: reserved bit this bit is reserved for testing. keep it as 0 for normal operation. [bits 2 and 1]: unused bit leave it as 0 for normal operation. 7 6 5 4 3210 address:00000aeh inte rdyi we rdy reserved - - lpm read/write (r/w) (r/w) (r/w) (r/w) ( - ) ( - ) ( - ) (r/w) initial value (0) (0) (0) (0) (0) ( - ) ( - ) (0)
548 appendix c 512k-bit flash memory MB90560 series [bit 0]: low power mode (lpm) when this bit is set to 1, the "l" period of the cex signal supplied to flash memory during access to flash memory is minimized to suppress the power consumption of flash memory. however, the access time is greatly increased compared with that when lpm is 0, and memory access is disabled when the cpu runs in high-speed mode. when lpm mode is used, therefore, run the cpu at frequencies of 4 mhz or less. the rdyint and rdy bits do not change simultaneously. create a program so that it uses one of them for a decision. n read/write access method while flash memory mode requires external-pin control for read or write access to the 1m-bit flash memory, normal mode does not require it because access timing is controlled by the flash memory interface circuit. the write access explained below is a write access to the command register to activate the automatic algorithm and means a write to flash memory. n read/write access in flash memory mode table c-2 lists the pin settings for read, write, and other operations in flash memory mode. control of these pin settings is not a problem when connecting to the flash memory writer but must satisfy the timing specifications of the individual pins in other cases. see the separate section for the timing specifications. since data bus width is limited to eight bits in flash memory mode, fix the bytex pin to 0. table c-2 pin settings for read/write access in flash memory mode operation cex oex wex aq0~16 dq0~7 rstx read l l h read address dout h write l h l write address din h output disable lhh 5 high-z h standby h 555 high-z h hardware reset 5555 high-z l rdy input rdyint bit rdy bit 1 machine cycle
MB90560 series appendix c 512k-bit flash memory 549 l read/write access in normal mode for a read/write access to flash memory in normal mode, the timing of the internal bus access from the cpu is converted, in the flash memory interface circuit, into flash memory access timing. in this mode, one read/write cycle completes in two internal machine clock cycles. for data access with lpm set to 0 in this mode, cex goes "l" for every cycle. however, for data access with lpm set to 1, cex goes "l" after the data decision of the data bus (d15 to d00). thus, the access timing is different. (when lpm is set to 1, the access time increases and the cpu speed must be decelerated.) internal address bits 15 to 0 corresponds to aq15 to 0 in flash memory mode on a one-to- one basis, and internal data bits 15 to 0 correspond to dq15 to 0 on a one-to-one basis. to perform a write access to flash memory, the we bit of the control status register must be set to 1 in advance. the we bit prevents the automatic algorithm from malfunctioning because of an invalid write to flash memory caused by noise. therefore, when no write access is anticipated, the we bit should be reset to 0. when lpm is 0, no restrictions apply to read/write access to flash memory, the same as for access to other types of memory, as long as the access time is within the range of the cpu operation guarantee frequencies. when lpm is 1, the cex timing controls read/write access and restricts the cpu operation frequencies. therefore, to perform a read or write access with lpm set to 1, set the cpu operation frequency to 4 mhz or less. n ready or busy signal the 1m-bit flash memory uses the aforementioned hardware sequence flags, i.e., data polling flag and toggle bit flag, to indicate whether the internal automatic algorithm is being executed or is finished. in addition, this memory also has hardware signals, i.e., ready and busy signals, available for the same purpose. the ready and busy signals operate differently, depending on whether the cpu runs in flash memory mode or normal mode. l flash memory mode for a ready or busy signal, the ry or byx signal from flash memory is asynchronously supplied to the ry or byx pin for the open drain output to the outside of the chip. when a pull-up resistor is connected to vcc, several ry or byx pins can be connected in parallel. when the output of the ry or byx pin is 0, flash memory is busy writing or erasing. in this state, no write or erase command can be accepted. when the ry or byx pin is set to 1 by the connection of an external pull-up resistor, flash memory is ready to accept a read, write, or erase command. in erase temporary stop mode, the ry or byx output is set to 1 by the connection of an external pull-up resistor. l normal mode a ready or busy signal is supplied as an interrupt request signal to the cpu via the flash memory interface circuit. an interrupt request is sent to the cpu when the state of flash memory changes from busy to ready while the inte bit of the control status register (fmcs) is 1. no interrupt request is sent to the cpu even if the state of flash memory changes as above if the inte bit of the fmcs register is 0. clearing the rdyint bit of the fmcs register to 0 after an interrupt request is issued to the cpu cancels the interrupt request to the cpu. this action also resets the inte bit of the fmcs register to 0.

appendix d example of f2mc-16lx mb90f562 connection for serial writing mb90f562 supports serial on-board writing (fujitsu standard) to flash rom. this appendix describes the specifications for serial on-board writing. n basic configuration the af200 flash microcomputer programmer of yokogawa digital computer co., ltd. is used for fujitsu standard serial on-board writing. figure d-1 standard configuration for fujitsu standard serial on-board writing contact yokogawa digital computer co., ltd. for the functionality and operation of the af200 flash microcomputer programmer and information on the general-purpose common cable (az210) and connectors. af200 flash microcomputer programmer + memory card rs232c host interface cable (az201) general-purpose common cable (az210) clock synchronous serial mb90f553a user system operable in stand-alone mode
552 appendix d MB90560 series n pins used for fujitsu standard serial on-board writing note: when the p00, sin0, sot0, and sck0 pins are also used by the user system, the control circuit shown below is required. (the /tics signal of the flash microcomputer programmer can separate the user circuit during serial writing. see the connection example shown later.) pin function description md2,md1, md0 mode pin used to enable write mode for the flash microcomputer programmer. p00 write program start pin C rstx reset pin C sin serial data input pin uart is used in clock synchronous mode. sot serial data output pin sck serial clock input pin vcc power supply pin if write voltage (5v10%) is supplied from the user system, this pin need not be connected to the flash microcomputer programmer. if the pin is connected to the flash microcomputer programmer, do not connect it to the power of the user system. vss ground pin used also as the ground pin for the flash microcomputer programmer. 10k w mb90f562 write control pin af200 write control pin af200 /tics pin user
MB90560 series appendix d 553 n connection example for serial writing figure d-2 is a connection example for serial writing. figure d.2 connection example for mb90f562 serial writing * 2 10k w 10k w 10k 10k w p00 md0 md1 vss vcc gnd tvpp1 /tres rstx sck sot sin trxd ttxd tck tmode taux3 /tics md2 dx10-28s or dx20-28s af200 flash microcomputer programmer mb90f562 taux 10k w (19) (12) (23) (10) (5) (13) (27) (6) (7,8, 14,15, 21,22, 1,28) dx10-28s dx20-28s user power supply (16) user system connector user user pin 1 t pin 14 pin 15 pin 28 pins 3, 4, 9, 11, 17, 18, 20, 24, 25, and 26 are open. pin assignments are viewed from the engagement side. cable connector (made by hirose denki) dx10-28s: right-angle type dx20-28s: straight type mode pin: md2, md1, md0 = 011 w
554 appendix d MB90560 series note: 1. when the sin, sot, and sck pins are also used by the user system, the control circuit shown on the right is required, which is the same as for p00. (the /tics signal of the flash microcomputer programmer can separate the user circuit during serial writing.) note: 2. if the power for writing is supplied by the af200, do not connect the power pin to the power supply of the user system. note: 3. turn off the user system power before connecting to the af200. n system configuration of af200 flash microcomputer programmer (yokogawa digital computer co., ltd.) for more information, contact the sales dept., equipment business center, yokogawa digital computer co., ltd. (telephone: 0423-33-6224) type function af200 advanced on-board flash microcomputer programmer ad200/ acp ac adapter (center +) (option) az201 host interface cable (pcat) az210 general-purpose common probe (type a) ff001 fujitsu f2mc-16lx control module for flash microcomputer ff001/p2 2mb pc card (option) ef001/p4 4mb pc card (option) 10k mb90f562 write control pin af200 / tics pin af200 write control pin user

corrections of MB90560 hardware manual (cm44-10107-1e) 1. a/d converter the total error for the 3v version (MB90560l series) is max. +/-8lsb. the total error for the 5v version (MB90560 series) is max. +/-5lsb adcs1 register sts1-0 bits = 0,0 --> activation by software. sts1-0 bits = 0,1 --> activation by software, and zero detection of free running timer sts1-0 bits = 1,0 --> activation by software, and reload timer sts1-0 bits = 1,1 --> activation by software, zero detection of free running timer, and reload timer. 1. ppg chapter 12.3.4.3 ppg clock control register (pcs01/23/45) the operating clock settings fc/32 and fc/64 are not possible. if these settings are used the ppg output will stay on low level. when ppg is set to 16 bit mode with "gate" function, the output can't produce desired waveform. input capture register chapter 12.3.3 ( page 304 in hw-manual) capture control register ( upper) ics23 the address for upper register 0x69 is incorrect, correct address is 0x6a. timer control status register chapter 12.3.1.3 ( page 294 in hw-manuel) upper timer control status register tccs ( bit 15-8). description of bit8 icre compare interrupt request enable bit is not correct. enable interrupt set '1', disable interrupt set '0'.
uart - synchronous mode chapter 13.6.1 baud rates: synchronous transfer division ratios. page 379 in hw-manual table 13.6-2 division ratio for clk synchronization: values in table are incorrect correct baud rates (div=4): cs2,cs1,cs0,baudrates 0, 0, 0, 4m 0, 0, 1, 2m 0, 1, 0, 1m 0, 1, 1, 500k 1, 0, 0, 250k 1, 0, 1, 125k max. synchronous baud rate with div=1: 8mbaud appendix c, 512k-bit flash memory the sector configuration of the flash memory is 32k/8k/8k/16k low power mode, chapter 5.3 bit 3 of the lpmcr is used to enter the timer mode. write 0 to this bit to enter the timer mode. clearing this bit will enter the timer mode, regardless from the current mode of the cpu. time base timer mode, chapter 5.5.2 time base timer mode is entered by clearing bit3 of the lpmcr register. clearing this bit will enter the timer mode, regardless from the current mode of the cpu. last updated : 16 september'99 ( tka )

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